JPH01264474A - Field discrimination circuit for video printer - Google Patents

Abstract

PURPOSE:To reduce the cost of the title circuit by respectively extracting vertical and horizontal synchronizing signals and measuring the time from the changing point of the vertical synchronizing signals to that of the horizontal synchronizing signals, and then, discriminating odd fields/even fields based on the measured time. CONSTITUTION:Composite synchronizing signals SYC are supplied to an input terminal Tin and vertical synchronizing signals VB and horizontal synchronizing signals HB are respectively extracted from the signals SYC by means of a monostable multivibrator MM1 and DFFDE1 and monostable multivibrators MM2 and MM3. A T-FFTF2 is triggered at the rise of the signals VB and outputs signals VJ. Moreover, a D-FFDF4 reads signals VK at the rise of the signals HB and outputs the inverted signals VL of the read signals. A processor CU measures the time interval between the changing point of time of the signals VJ and that of the signals VL, detects whether the next field is an odd one or even one, and outputs field signals FS. Therefore, the parts constituting the title circuit can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video printer that prints display images.
In particular, the present invention relates to a field discrimination circuit that discriminates whether scanning of a display screen is an odd field or an even field.

[Prior Art] Conventionally, video printers have been provided for printing one frame of video on a television screen onto recording paper. by the way,
In a television receiver, one screen is made up of odd field scanning lines and even field scanning lines. Therefore, in order to faithfully print one frame of the video onto recording paper, it is necessary to determine whether the field is an odd field or an even field in addition to the video signal.

Therefore, in order to discriminate between fields, a field discriminating circuit as shown in FIG. 2 has conventionally been employed.

In this figure, reference numeral Tin is an input terminal to which a composite synchronization signal SYC is supplied. This composite synchronization signal SYC is a combination of a horizontal synchronization signal (period H) and a vertical synchronization signal, and the waveforms of the composite synchronization signal SYC in odd and even fields are shown in Figure 3 (A) and (E). It is as shown. Here, in Fig. 3 (a) and (e), between ae and 1
Each of the five intervals represents a vertical retrace period. Furthermore, between a and b,
Between cd, fg and h i represent equivalent pulses, between 50 and gh represent vertical synchronizing pulses, and between de and 11 represent horizontal synchronizing pulses. Further, the field between e and f represents an odd field, and the field between j and a represents an even field. The image of the odd field starts from point 0, and the image of the Q'A losing field starts from point j. MMI is a monostable multivibrator (hereinafter referred to as monomulti), which is triggered by the falling edge of the composite synchronization signal SYC and receives a signal VA with a pulse width of 11-1/4 (Fig. 3 (b), (W) shows the signal waveform).

DPI is D (delay)-flip-flop,
At the rising edge of signal VA, composite synchronization signal SYC is read and output as vertical synchronization signal VB (signal waveforms are shown in FIG. 3).

DF2 is also a D- flip-flop similar to the D-flip-flop DPI.
It's a flip flop. This D-flip-flop
) F2 is the rising of the signal VA, and the vertical synchronizing signal VB
is read, and the inverted signal VD of the read signal (Figure 3 (
D) and (Y) show the signal waveforms). AND is a negative logic AND circuit, and when both the vertical synchronization signal VB and the signal VD are input at the "L" level, the signal VE which becomes "L" level (Fig. 3 (E) and (E)) (signal waveform shown) is output. MM2 is a monomulti, is triggered by the falling edge of the composite synchronization signal SYC, and is 31
A signal HA (the signal waveform is shown in FIG. 3) with a pulse width of -1/4 is output. MM3 is a monomulti, and is triggered by the rising edge of the signal HA, and outputs a narrow pulse width horizontal synchronizing signal 1-IB (signal waveforms are shown in FIGS. 3(g) and 3(b)). DF3 is a D-flip-flop, which reads the signal vE at the rising edge of the horizontal synchronizing signal I (B) and outputs it as a signal VF (signal waveforms are shown in FIG. 3 (H) and (S)). TFI is This is a T (trigger) flip-flop. This T-flip-flop TF1 is a D-flip-flop whose output terminals and input terminals are shorted together, and is triggered by the rising edge of the signal VC, and the signal VF' reset by .

The waveform of the signal VC output from the output terminal Q of this T-flip-flop TFI is shown in FIGS.

C[J is a processing device that discriminates between odd and even fields based on the level of signal VG.

In the field 'l' JI separate circuit configured in this way, mono multi MM! , D-flip-flop DPI
is a circuit that creates a vertical synchronization signal VB from a composite synchronization signal SYC, monomulti MM2° MM3 is a circuit that creates a horizontal synchronization signal HB from a composite synchronization signal SYC, and D-flip-flop DF2. AND circuit A N D
, D-flip-flop DF3. The T-flibbing flop 'I' F1 is a circuit that creates a signal VC based on the vertical synchronizing signal VB and the horizontal synchronizing signal HB, and this signal VC indicates whether the next succeeding field is odd or even.

That is, when the vertical synchronization signal VB is at the "L" level, when the signal VG is at the "I4" level, the next field is an odd field, and when the signal VG is at the "L" level, the next field is an even field. become.

The reason for this is as follows. First, the `r-flip-flop TFI is triggered at the rising edge of the signal VC, which is an inversion of the vertical synchronizing signal VB. Therefore, the output signal VG of this T-flip-flop TFI becomes an inverted shift signal for each field, as shown in FIG. On the other hand, as shown in FIG. 3 (E) and (E), the output signal VE of the AND circuit AND is generated at the falling edge of the vertical synchronizing signal VB.
It becomes “I7” during 4/2. Here, if the next succeeding field is an odd field, at the time when the signal VE becomes "L", the horizontal synchronizing signal) IB is monomultiple MM.
3 (see Figure 3 (e), 0)), on the other hand,
If the next succeeding field is an even field, the signal V
At the time when E becomes “L”, the horizontal synchronizing signal tt I3
is output from the monomulti MM3 (Fig. 3(ri)
, (see)). This makes the D-flip-flop D
The output signal VF of F3 becomes the "■7" level as shown in FIGS. 3 and 4 only when the next field is an even field, and this L level signal
- It is supplied to the reset terminal R of the flip-flop TI"l. As a result, the output signal VC of the T-flip-flop TFI is at "L" level when the next succeeding field is an even field, as shown in FIG. , it becomes "■" level when it is an odd field.

[Problems to be Solved by the Invention] By the way, in the above-mentioned conventional field discrimination circuit,
Since the circuit configuration was complicated, there was a problem in that the manufacturing cost was high.

This invention was made in view of the above problems, and by reducing the number of circuit components of the field discrimination circuit,
The purpose is to reduce manufacturing costs.

[Means for Solving the Problems] The present invention includes a first circuit that extracts a vertical synchronization signal from a composite synchronization signal including a horizontal synchronization signal and a vertical synchronization signal; and a measuring means for measuring the time from the change point of the vertical synchronizing signal to the changing point of the horizontal synchronizing signal, based on the measurement result of the measuring means. /The above problem is solved by determining even fields.

"Operation" In the above configuration, the time from the change point of the vertical synchronization signal to the change point of the horizontal synchronization signal is measured differently depending on whether it is an odd feed or an even field, so based on the 11 measurement results, can be determined.

[Embodiments] Hereinafter, embodiments of the field discrimination circuit of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and is a block diagram of a field discrimination circuit. In this figure, the same reference numerals are attached to the same components as those of the above-mentioned conventional example to simplify the explanation.

The field discrimination circuit of this example is different from the conventional one shown in FIG.
, a D-flip-flop DF4 is installed).

The third r-flip-flop TF2 is constructed by short-circuiting the output terminals of the D-flip-flop and the input terminal I, and is triggered by the fall of the vertical synchronizing signal VB.

The waveform of the signal VJ output from the output terminal Q of this T-flip-flop TP2 is shown in FIGS.

1) - The flip-flop DF4 reads the signal VK at the rising edge of the flat synchronization signal LIB and outputs an inverted signal VL of the read signal (signal waveforms are shown in FIGS. 3(R) and 3(S)). The processing unit CU determines whether the next succeeding field is an odd number or an even number based on the time interval between the change points of the signals V1, J and 2 described above.

In the above configuration, the T-flip-flop 'rF2 is triggered at the falling edge of the vertical synchronizing signal VB, and therefore the output signal VJ of this T-flip-flop TF2
is a signal that is inverted for each field, similar to the signal VC in FIG. Further, the D-flip-flop DF4 outputs the signal VJ at the rising edge of the horizontal synchronizing signal 1-IB.
Read the inverted signal VK. Here, when the next field is an odd field, the horizontal synchronizing signal HB is the third
As is clear from the figure (G), from the falling edge of the vertical synchronizing signal vB.

When the time Ta=3H/4=47.625 μsec has elapsed, the signal is output from the monomulti MM3, and on the other hand,
If the next field is an even field, as is clear from FIG. The signal is output from the monomulti MM3 after a time of 875 μsec has elapsed. Therefore, if the next field is an odd field, the output signal VL of the D-flip-flop DF4 changes when time 'ra has elapsed from the fall of the vertical synchronizing signal VB, and if the next field is an even field. In this case, the time 'L' from the fall of the vertical synchronization signal VB l)
It will change over time. Here, since the signal V, 1 changes at the fall of the vertical synchronizing signal VB, if the next field is an odd number, the change point of the signal VJ and the signal VL
The time interval between the change points of the signal VJ and the signal VL changes is Ta, and if the next field is an even number, the time interval between the change points of the signal VJ and the signal VL is `rb. That is, the signal V
By measuring the time interval between the time of change of J and the time of change of signal vL, it is possible to detect whether the next field is an odd number or an even number. In the circuit of FIG. 1, the processing device Ct
J measures that time interval to find the next field,
It outputs a field signal 1"S indicating the detected field. Note that when the processing unit CU detects an even field, it outputs a reset signal RS to the T-flip-flop T.
If you output to P2, you will not have to measure time from now on.
Field detection can be performed by checking the level of signal VJ.

According to the above configuration, the number of components of the field discrimination circuit can be reduced, so that the manufacturing cost of the field discrimination circuit can be reduced.

In the above example, the case was described in which the signal VK is inverted at the falling edge of the vertical synchronizing signal VB, but the invention is not limited to this, and at the rising edge of the vertical synchronizing signal VB,
The above state may be reversed.

Furthermore, in the above example, the vertical synchronizing signal VB
Although the circuit for creating the circuit is constructed using a monomulti MMI and a delay flip-flop DPI, it may be constructed using an integrating circuit instead.

[Effects of the Invention] As explained above, according to the field discrimination circuit of the present invention, the number of circuit components can be reduced, so that the manufacturing cost of the field discrimination circuit can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the field discrimination circuit of the present invention, FIG. 2 is a block diagram showing a conventional field discrimination circuit, and FIG. 3 is a block diagram of each field discrimination circuit shown in FIGS. 1 and 2. Each signal waveform diagram, FIG. 4 is a signal waveform diagram of the field discrimination circuit of FIG. 2. SYC...Composite synchronization signal, VI3...
...Vertical synchronization signal, 11[3...Horizontal synchronization signal, MML, M~12. ~iM3...Monostable multivibrator, D P I, D
I;' 4...Delay-flip-flop,
T F2...Trigger flip-flop, Ct
J...Processing device (measuring means).

Claims (1)

[Claims] In a video printer that prints an image displayed in an interlaced manner on a display screen of a display device, a first circuit extracts a vertical synchronization signal from a composite synchronization signal including a horizontal synchronization signal and a vertical synchronization signal; , a second circuit for extracting a horizontal synchronization signal from the composite synchronization signal, and a measuring means for measuring a time from a change point of the vertical synchronization signal to a change point of the horizontal synchronization signal, the measuring means A field discrimination circuit for a video printer, characterized in that it discriminates between an odd field and an even field based on measurement results.