JPH01261915A - Pulse generator - Google Patents

Abstract

PURPOSE:To obtain a pulse generator which can considerably reduce circuit scale by using two frequency-dividing circuits for the clock of a shift register, loading them and alternately switching the outputs. CONSTITUTION:The master clock 1 is frequency-divided in a first frequency- dividing means 10, and signals Q1 and XQ1 with a period N, and with 50% of duty factor are generated, whereby the signals are set to be the switching inputs of a switching means 40 and the data output of a storage means 50. Flame pulses L and XL which are generated in the first frequency-dividing means 10 in synchronizing with the output signals Q1 and XQ1 are set to the load signals of a second frequency-dividing means 20. The outputs Q2 and XQ2 of the second frequency-dividing means 20 are alternately switched in the switching means 40 and are transmitted as the clocks of the storage means 50. The storage means 50 sets the signals CK1 and CK2 from the switching means 40 to be the clocks, sequentially shifts the outputs Q1 and XQ1 from the first frequency-dividing means 10 in plural stages, stores them and generates (M+1)-kinds of pulses P01-Pm+1.

Description

[Detailed Description of the Invention] [Summary] Multiple types of pulses with a period of N bits and a duty factor of 50%, each phase difference consisting of the number of focuses divided by a positive integer and the number of bits left over. Regarding pulse generators that generate The first frequency dividing means divides the mask clock by N/2, the second frequency divider divides the mask clock by N/M, and the first frequency dividing means divides the mask clock by N/M.
a switching means for switching the output of the frequency dividing means with the output of the second frequency dividing means; and a signal outputted from the switching means as a clock, and storing the output from the first frequency dividing means while sequentially shifting the output through multiple stages. , and storage means for generating (M+1) types of pulses.

[Industrial application field]

In the present invention, the period is N bits and the duty factor is 50.
The present invention relates to a pulse generator that generates a plurality of types of pulses, each of which has a phase difference of 1.5% and a remainder of the number of bits divided by a positive integer.

For example, in digital relay exchange, in order to connect input data to one of multiple lines, 0 lines of data that have a temporal transition are rearranged in the same column temporally, and the temporal positions are swapped. There is a time switch that performs the operation of time-division multiplexing the data, transmitting it, and then replacing it with zero data that has a temporal transition on the receiving side.

The timing signal for performing such an operation requires a plurality of special types of pulses depending on the usage state.

That is, for example, the phase difference is the number of bits that cannot be divided by dividing the data bits constituting one frame by a positive integer. A pulse consisting of the divided number of bits and the remainder number of bits is required.

Normally, a circuit for creating these from one mask clock is required to have a simpler circuit configuration from the viewpoint of overall device installation space requirements and power consumption.

[Conventional technology]

FIG. 8 is a block diagram illustrating a conventional example, FIG. 9 is a diagram illustrating the state of a pulse signal to be generated, and FIG. 10 is a diagram illustrating a row-to-column conversion situation of a time switch.

For example, as shown in FIG.
28 columns (bits) of parallel data (bits) -
In order to convert into 10 columns of time-division data, the following special pulses are required.

That is, the same period, the same waveform (duty factor 50%)
), the phase difference is not too small with respect to the mask clock, and it is made up of the period divided by a positive integer (if necessary, the number of locks minus 1) and the remainder, and the difference between the pulse groups is A pulse whose rising and falling edges do not coincide is required.

In the case of this example, as shown in Figure 9, one period has 256 focuses and 10 types of phase differences (9 types with a 28-bit phase difference from the previous position and 4-bit phase difference). This is a case where 10 types of pulses POI to PIO are generated.

A conventional example for this purpose is shown in FIG. That is, in the example of FIG. 8, the mask clock ■ is divided by 1/2 to 1/256.
56 frequency divider 1, 1/4 frequency divider 2 that divides the mask clock ■ into 1/4, and 1/7 frequency divider that divides the output of 1/4 frequency divider 2 into 1/7. 3, a 1/9 frequency divider 4 that divides the output of the 1/7 frequency divider 3 into 1/9, and a duty factor of 256 bits per cycle based on the output from each frequency divider 1 to 4. Based on the output from the pulse detection circuit (hereinafter referred to as DET) 5 (1) which detects a 50% pulse and each frequency divider 1 to 4, one cycle is 256 bits, and the duty factor is 50%.
) to detect a pulse whose phase is shifted by 28 bits from
ET5 (2) and DET5 (3) which similarly detects a pulse whose phase is shifted by 28 bits from the previous pulse.
Based on ~5 (9) and the output from each frequency divider 1 to 4, detect a pulse with one period of 256 bits, a duty factor of 50%, and a phase shift of 4 bits from the preceding DET5 (9). DET5 (10) and each DET5
(1) to 5 The pulses detected and output in (10) are
First, a selector circuit (hereinafter referred to as SEL) 7 selects a pulse to be output from DET5 (1), and then sequentially selects the pulse.
It is equipped with.

In the circuit described above, DET5 (1) has a half period of 128
A bit pulse POI is output, and in DET5(2), a pulse P whose phase is shifted by the output of the 177 frequency divider 3, that is, 28 bits, is output from the pulse POI.

DET5 (3) outputs a pulse PO3 whose phase is shifted by 28 bits from the pulse Po2.

In this way, up to DET5 (9), a pulse whose phase is shifted by 28 bits from the previous pulse is output, but at DET5 (10), the output of the 1/9 frequency divider 4 is turned off, and the previous pulse is output. The detection is performed so as to output a pulse PIO whose phase is shifted by 4 bits with respect to the pulse.

The 5EL7 sequentially selects these pulses POI to PIO to create 10 types of pulses shown in FIG. 9.

Note that the operation order of each DET5 (1) to 5 (10) is determined from the smallest number, and during one cycle (frame), while one DET is operating, the other DETs do not output their output. It is assumed that the detection pulse is stopped and the above-mentioned detection pulse is sent out.

[Problem to be solved by the invention]

In the conventional example described above, in order to generate each type of pulse POI to PIO, the functional block 5 corresponding to the number of generated pulses is used.
(1) to 5 (10) are required, and therefore, the more types of pulses that are generated, the larger the circuit scale becomes.

The present invention provides a pulse generator that can significantly reduce the circuit scale by using two frequency dividing circuits for the shift register clock and configuring them to be loaded and to alternately switch their outputs. The purpose is to

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 10 is a first frequency dividing means that divides the frequency of the mask clock ■ by N/2, and 20 is a second frequency divider that divides the frequency of the mask clock ■ by N/M. Means 40 converts the outputs Ql and XQI of the first frequency dividing means 10 to the outputs Q2 . 50 is a signal CKI outputted from the switching means 40;

Using CR2 as a clock, the output Q of the first frequency dividing means 10
l, XQI are stored while sequentially shifting in multiple stages, and (M,
+1) It is a storage means for generating pulses of different types, and by providing such means, it is a means for solving the present problem.

[For production]

The mask clock ■ is divided by the first frequency dividing means 10 to obtain signals Ql and XQI with a period N and a duty factor of 50%.
is created and used for switching of the switching means 40 and data input of the storage means 50.

Also, the first frequency dividing means 10 outputs its output signal Ql.

Frame pulse I5°XL created in synchronization with XQI
is the load signal of the second frequency dividing means 20, and the output Q2. By configuring XQ2 to be alternately switched by the switching means 40 and sent as a clock to the storage means 50, and to create and send out (N+1) types of pulses from the storage means 50, it is possible to generate (N+1) types of pulses with a simple configuration. This makes it possible to create special pulses.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 to 7.

FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the configuration of the 1/25.6 frequency dividing section in the embodiment of the present invention, and FIG. /2
FIG. 5 is a diagram illustrating the configuration of the 8 frequency divider section, FIG. 5 is a diagram illustrating the configuration of the switch section and shift register section in the embodiment of the present invention, and FIG. 6 is a diagram illustrating the time chart in the embodiment of the present invention. , and FIG. 7 respectively show diagrams illustrating signal situations processed in an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout all the figures.

The embodiment of FIG. 2 uses the first frequency dividing means I explained in FIG.
As O, divide the mask clock ■ into 1/256.
/256 frequency divider 10a, second frequency divider 20, two 1/28 frequency dividers 20a and 2Qb, which divide the mask clock 2 to 1728, switch unit 40 as switching means 40 and storage means 50.
a and two shift register sections soa.

50b.

Moreover, each functional block 10a, 20a, 20 shown in FIG.
b, 40a, 50a, and 50'b are shown in Fig. 3~
It is shown in FIG.

That is, the 1/256 frequency dividing section 10a is as shown in FIG.
Two 128-decimal power counter circuits 11 and 12, an eight-power NOR square circuit (hereinafter referred to as NOR circuit) 13, and two D-type flip-flop circuits (hereinafter referred to as DF).

(referred to as F circuit) 14.15, and two AND circuits (referred to as AND circuit hereinafter) 16.1
It consists of 7.

Furthermore, the 1/28 frequency dividers 20a and 20b shown in FIG. It consists of a counter circuit 23, two DF and F circuits 26 and 27, and two inverter circuits 22 and 24.

Furthermore, the switch section 40a and shift register sections 5Qa and 50b shown in FIG. 5 include four AND circuits 41 to 44 and two (7) NOR circuits 45.
a, and five D-F and F circuits 51 (1) to 51 (
5), 61 (i) 61 (5) constitute shift register sections 50a and 66a.

The 1/256 frequency divider 10a generates pulses 256Q and 256XQ with one period (one frame) of 256 bits and a duty factor of 50% in a 128-decimal power counter circuit 11.12 based on the mask clock ■. (XQ is Q
, and the same applies hereafter), and convert it to D
-F, a switch section 40a shown in FIG. 5 in the F circuit 15,
It is output as a data input to the shift register sections 50a and 60a.

Note that the time charts and pulse waveforms described below are shown in FIGS. 6, 7, and 9.

Next, frame pulse LDI (reverse polarity of LDI is L
D2) is the NOR output of the outputs of the 128-decimal power counter circuits 11 and 12, which is multiplied by the D-F, F circuit 14, and the positive output Q and the positive output Q and the inverted output of the D-F, F circuit 15 are X
It is generated by ANDing Q and ' with AND circuits 16 and 17.

The 28-decimal counter circuit 23 in the 1/28 frequency dividers 20'a and 20b loads LDI or LD'2 and outputs a carrier I-CO signal of every 28 bits to the D-F, F circuit 26. , 4 pins 1- of the 28-decimal power counter circuit 23 at that time.
The output data QA-QD of 28C1 and 28C2 shown in FIGS. 6 and 7 are created by ORing the output data obtained by ORing the output data QA-QD in the OR circuit 25 in the OR circuit 28.

The switch unit 40a uses the output 28C1 of the 1/28 frequency dividing unit 20a and 256XQ or 256Q as a clock for the shift register unit 50 that shifts the pulse of 256Q using an AND circuit 41, 42 and an OR circuit 45! 1/2 as the clock for the shift register unit 60 that processes the 5CKI and 256XQ pulses from shift 1 to
Similarly, the output 28C2 of the 8 frequency divider 20b is connected to the AND circuit 43.
, 44 and the OR circuit 46 to create the 5CK.
2 and send out alternately, 256Q and 256XQ
Shift processing of pulses.

Each of the D-F and F circuits 51 (1) to 51 connected in series within the shift register sections 5Qa and 50b
(5), 61 The pulses taken out from (1) to 61(5) have one cycle of 256 bits as shown in Figure 9.
Ten types of pulses POI to PLO are generated with 0 types of phase difference (28 bits x 9□ 4 bits x 1 phase difference).

By configuring as described above, it is possible to reduce the circuit scale to about 115 or less when explained in FIG. 8.

〔Effect of the invention〕

According to the present invention as described above, a plurality of types of clocks are generated which are pulses with a period of N bits and a duty factor of 50%, and each phase difference has a number of bits divided by a positive integer and a remainder of the number of bits. A pulse generator realized with a simple configuration can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a diagram explaining the configuration of the 1!256 frequency divider in the embodiment of the present invention. , FIG. 4 is a diagram explaining the configuration of the 1/2B frequency dividing section in the embodiment of the present invention, FIG. 5 is a diagram explaining the configuration of the switch section and shift register section in the embodiment of the present invention, and FIG. is a diagram for explaining a time chart in an embodiment of the present invention, FIG. 7 is a diagram for explaining a signal situation processed in an embodiment of the present invention, FIG. 8 is a block diagram for explaining a conventional example, and FIG. 9 is a diagram for explaining a conventional example. FIG. 10 is a diagram for explaining the state of the pulse signal to be created, and FIG. 10 is a diagram for explaining the row-to-column conversion situation of the time switch. In the figure, 1 is a 1!256 frequency divider, 2 is a 1!4 frequency divider, and 3 is a 1!
7 frequency divider, 4 is 1!9 frequency divider, 5 (1) ~ 5
(10) is DBT. 7 is SEL, 1o is first frequency dividing means, 10
a is the 1!256 frequency divider, 11.12 is the 128-base counter circuit, 13.21 is the NOR circuit, 14.15.2!6,27.5H1) ~ 51 (5)
, 61 (1) to 61 (5) are D-F and F circuits, 16 and 17.41 to 44 are AND circuits, 20 is a second frequency dividing means, 20a and 20b are 1!28 frequency dividing units, 22 .24 is an inverter circuit, 23 is a 28-decimal power counter circuit, 25.28, 45.46 are OR circuits, 40 is a switching means, 40a is a switch section, 50
50a and 50b are shift register units, respectively. ~17- l 6- good, to 1

Claims (1)

[Claims] Based on the master clock ([1]), the pulse has a period of N bits and a duty factor of 50%, and each phase difference consists of (N bits/M) bits and α bits, and The rising and falling edges of each do not match (M
+1) types of pulses (P01 to Pm+1), the pulse generator comprising: a first frequency dividing means (10) that divides the frequency of the master clock ([1]) by N/2; a second frequency dividing means (20) that divides the output (Q1, XQ1) of the first frequency dividing means (10) by N/M; and a second frequency dividing means (20) that divides the output (Q1, a switching means (40) that switches using the outputs (Q2,
Output (Q1, XQ1) from the first frequency dividing means (10)
) for generating (M+1) types of pulses (P01 to Pm+1) by sequentially shifting them in multiple stages.
0).