JPH01260309A - Operation circuit - Google Patents

Abstract

PURPOSE:To take out a digital signal with high resolving power without increasing the circuit scale, by a method wherein two analogue signals are compressed to logarithmic values which are, in turn, inputted to output an analogue signal corresponding to the ratio of the aforementioned two analogue signals and said analogue signal is converted to a digital signal. CONSTITUTION:Current sources 21a, 21b are respectively connected between a power supply Vcc and the anodes of diodes 22a, 22b for logarithmic compression and currents IA, IB show the photocurrent (analogue signal) taken out from a position detecting element 21. This photocurrent is inputted to a double integrating type A/D converter 28 as the output current of the transistor 24a of a differential amplifier 23. In the converter 28, the count value corresponding to the time before the voltage of a capacitor 33 reaches reference voltage Vref is held in a counter 36. This counted value is taken out as digital signals q1-qn from output terminals Q1-Qn. These digital signals are proportional to IA/(IA+ IB).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic circuit used in an autofocus distance measuring device of a camera, and the like.

Conventional technology As a distance measuring device used for autofocus aim of a camera, infrared light is emitted from the camera side toward the subject, and the reflected light is emitted from the infrared light projection position to a distance corresponding to the base line length in triangulation. A position detection element (abbreviated as PSD, Po5ition 5en) placed at a certain distance away.
An active type distance measuring device that measures the distance to the subject based on the projected position by projecting the image onto a position detecting element consisting of a plurality of photodiodes or a plurality of photodiodes is known. The PSD used as one is a pair of PSDs that distribute and extract light generated according to the amount of infrared light projected onto its light-receiving surface in proportions according to the projection position of the infrared light. The arithmetic circuit calculates the ratio of two photocurrents, which are analog signals taken out from these two output terminals, and the distance to the subject is measured from the ratio.

FIG. 2 is a circuit diagram showing a conventional example of an arithmetic circuit that calculates the ratio of two photocurrents taken out from the above-mentioned PSD. PSDl is here represented by two current sources 1a and lb, and the currents supplied from the respective current sources 1a and lb are the photocurrents taken out from the two output terminals of pSD1. It shows.

One current source 1a is connected between the power supply Vcc and the anode of the logarithmic compression diode 2a, and the other current source 1b is connected between the power supply Vcc and the anode of another logarithmic compression diode 2b, 'Two diodes 2a, 2
A reference voltage Vref is applied to the cathode of the transistor b.

3 is a differential amplifier that receives the anode voltages of the two diodes 2a and 2b as two inputs, and has two NP
It is composed of N transistors 4a and 4b, a resistor 5, and a constant current source 6. The anode of the diode 2a is connected to the base of the NPN transistor 4a via a voltage follower circuit 7 which is a buffer, and the anode of another diode 2b is connected to the base of the NPN transistor 4a via another voltage follower circuit 8.
It is connected to the base of transistor 4b.

The emitters of the two NPN transistors 4a and 4b are both connected to one terminal of a constant current source 6, and the collectors of the NPN transistors 4a and 4b are connected directly to the power supply Vcc through a resistor 5, respectively. The other terminal of the constant current source 6 is grounded. 9 is an analog-to-digital converter for converting the analog signal taken out from the differential amplifier 3 into a digital signal, and includes a constant current source 10 and four resistors 11, 12, .
13.14 and four comparators 15, 16.17.1
It consists of 8.

One input terminal of each comparator 15 to 18 is both N
PN) - connected to the collector of transistor 4a.

Constant current source 10 and four resistors 11 to 14 are connected in series, one terminal of the series circuit is connected to power supply VCC,
The other terminal is grounded, and the voltage of the power supply Vcc is divided into several stages and the divided voltages are applied to each of the comparators 15 to 18.
It has the function of supplying the other input terminal as a reference voltage for comparison.

That is, the connection point of resistors 11 and 12 is the comparator 15.
is connected to the input terminal of the resistor 11 from the voltage of the power supply Vcc.
The voltage dropped by the voltage between the terminals of is given as the comparison reference voltage of the comparator 15. Further, the connection point of the resistors 12 and 13 is connected to the input terminal of the comparator 16, and a voltage that is lower than the comparison reference voltage of the comparator 15 by the voltage between the terminals of the resistor 12 is given as the comparison reference voltage of the comparator 16. Similarly, the connection point of resistors 13 and 14 is connected to the input terminal of comparator 17, and
A voltage that is lower than the comparison reference voltage of 6 by the voltage across the terminals of the resistor 13 is given as the comparison reference voltage of the comparator 17. Further, the connection point between the resistor 14 and the constant current source 10 is connected to the input terminal of the comparator 18,
A voltage that is lower than the comparison reference voltage by the voltage across the terminals of the resistor 14 is given as the comparison reference voltage of the comparator 18.

In the conventional arithmetic circuit described above, the anode voltage Va of the diode 2a and the anode voltage V of the diode 2b
b is each where k: Boltzmann's constant q: electron charge T: absolute temperature ■. : Reverse saturation current of diodes 2a and 2b. In addition, the collector current of the NPN transistor 4a is Icl, and the collector current of the NPN transistor 4b is Ic.
2, the base-emitter voltage Vl of the NPN transistor 4a (I and the base-emitter voltage ■axz of the NPN) transistor 4b is, however, 1. :NPNl-Reverse saturation current of transistors 4a, 4b. On the other hand, each NPN) transistor 4a.

Each voltage follower circuit 7 is installed at the base of 4b.
．． Anode voltage Va of diodes 2a, 2b via 8
, Vb is given, so ■+t+ Vatz=Va
Substituting equations 1 to 4 into equation 5, where the relationship of Vb ''' (5) holds, we get...(6), and the relationship from these is derived, and the relationship from equation 7 is Now, let us assume that the constant current source supplied by the constant current source 6 is 11, and the NPN transistors 4a and 4b
Ignoring the base current of Ic++Iez=I+
-(9), so from the 8th and 9th equations, the following relationship holds true.This collector current Ic+, that is, the output current of the differential amplifier 3, is the sum of the currents I^ and Im, in other words, projected onto PSDI. The current IA, 1. It changes depending on the ratio of That is, an analog signal corresponding to the projection position of the infrared light on the light receiving surface of the PSDI is extracted from the differential amplifier 3. The voltage dropped from the voltage of the power supply V c c by the voltage between the terminals of the resistor 5 due to the collector current 1c1 is N
Since this is the collector voltage of the PN transistor 4a, the collector voltage given to each of the comparators 15 to 18 is also an analog signal that changes depending on the projection position of the infrared light.

In the 10th equation, the current IA, 1. When the ratio Is/1 is sufficiently large (therefore, the collector current I C1 is sufficiently small) and the collector voltage of the NPN transistor 4a is higher than the comparison reference voltage of the comparator 15, the collector voltage is higher than that of the other comparators 16 to 18. The comparison reference voltage of the four comparators 15 to 18 is higher than that of the reference voltage of
The output Di.

C2, C3, and C4 are all r) IJ. From this I
, / I A is slightly small, NPN) transistor 4a
When the level of the collector voltage of is between the comparison reference voltage of the comparator 15 and the comparison reference voltage of the comparator 16, the output D1 is "OFF" and the other outputs D2 to D4 are "r" (
It becomes J.

Similarly, the level of the collector voltage of the NPN transistor 4a is the comparison reference voltage of the comparator 16 and the level of the collector voltage of the comparator 1.
7, the output DI, D2 is "L", and the other outputs D3. When D4 becomes rH and is between the comparison reference voltage of the comparator 17 and the comparison reference voltage of the comparator 18, the outputs D1 to D3 are "L",
When the output D4 becomes r)(J and is further below the comparison reference voltage of the comparator 18, all outputs D1 to D
4 becomes rl, J. That is, the analog signal taken out from the differential amplifier 3 is sent to the analog-to-digital converter 9.
is converted into a digital signal consisting of a combination of four outputs D1 to D4. In this case, the digital signal will display the projection position of the infrared light on the light-receiving surface of the PSD 1, or in other words, the distance to the subject, divided into five stages.

Problems to be Solved by the Invention However, in the conventional arithmetic circuit described above, in order to increase the resolution of data that is converted into a digital signal and extracted, the number of comparators must be increased.
There was a problem that the scale of the circuit became too large.

Therefore, an object of the present invention is to provide an arithmetic circuit that can extract a digital signal corresponding to the ratio of two input analog signals with high resolution from two input analog signals without increasing the circuit scale. be.

Means for Solving the Problems The present invention provides a first method that receives an analog signal, compresses it into a logarithmic value containing the quantity of the analog signal as an antilog number, and outputs the compressed value.
and a second logarithmic compression circuit, which receives two outputs obtained by the first and second logarithmic compression circuits as two inputs, and receives an analog signal input to the first logarithmic compression circuit and a second logarithmic compression circuit. A differential amplifier that outputs an analog signal corresponding to the ratio of the analog signal input to the differential amplifier, and a double integral type analog-to-digital converter that converts the output of the differential amplifier into a digital signal. This is an arithmetic circuit.

According to the present invention, an analog signal corresponding to the ratio of two input analog signals is extracted from the differential amplifier, and the extracted analog signal is converted into a digital signal by a double integral type analog-to-digital converter. be done.

Embodiment FIG. 1 is a circuit diagram showing the configuration of an embodiment of the arithmetic circuit of the present invention. This embodiment shows an arithmetic circuit used in an active type distance measuring device, and in FIG. 1, a PSD 21 used as a position detection element is represented by two current sources 21a and 21b. , the currents IA, I supplied from the respective current sources 21a, 21b
s indicates the photocurrent taken out from the two output terminals of the PSD 21.

One current source 21a is connected between the power supply Vcc and the anode of the logarithmic compression diode 22a, and the other current source 21a is
1b is connected between the power supply Vcc and the anode of another logarithmic compression diode 22b, and the two diodes 2
A first reference voltage V r e is applied to the cathodes of 2a and 22b.
f 1 is given. 23 are the two diodes 22a mentioned above.

It is a differential amplifier that receives the anode voltage of 22b as two inputs, and has two NPN transistors 24a.

24b and a constant current source 25. The anode of the diode 22a is connected to the base of the NPN transistor 24a through a voltage follower circuit 26 which is a buffer, and the anode of another diode 227 is connected to the base of the NPN transistor 24a through another voltage follower circuit 27.
It is connected to the base of 4b.

The emitters of the two NPN transistors 24a and 24b are both connected to one terminal of a constant current source 25, and the NPN
) The collector of the transistor 24b is connected to the power supply Vcc, and the other terminal of the constant current source 25 is grounded.

28 is a double integral type analog-to-digital converter for converting the analog signal taken out from the differential amplifier 23 into a digital signal, and includes a constant current source 29, three switches 30, 31, 32, and a capacitor 33. , a comparator 34, a timing control circuit 35, a counter 36, and a clock generator 37.

One terminal of constant current source 29 is connected to power supply Vcc, the other terminal is connected to one terminal of capacitor 33 via switch 31, and the other terminal of capacitor 33 is grounded. The connection point A between the switch 31 and the capacitor 33 is connected to the NPN transistor 24 via the switch 30.
a and the comparator 34
is also connected to one input terminal of the . Its input terminal is connected to the output terminal of a comparator 34 via a switch 32, and the other input terminal of the comparator 34 is supplied with a second reference voltage Vref2. The output terminal of the comparator 34 is connected to the enable input terminal E of the counter 36, and the clock input terminal C of the counter 36 is connected to the clock generator 37. The timing control circuit 35 has a function of turning each switch 30 to 32 on and off at a predetermined timing, and a function of providing a reset signal to a counter 36 at a predetermined timing.

Next, the operation of the arithmetic circuit described above will be explained.

As in the case of the conventional arithmetic circuit, the anode voltage Va of the diode 22a and the anode voltage Vb of the diode 22b are respectively . :If the collector current of the NPN transistor 24a is Ie2, which is expressed as the reverse saturation current of the diodes 22a and 22b, then the base-emitter voltage V of the NPN transistor 24a. l and NPN)
Base-emitter voltage of transistor 24b■++tz
are expressed as the reverse saturation currents of the NPN transistors 24a and 24b, respectively, so that a relational expression similar to Equation 8 in the case of a conventional arithmetic circuit can be obtained from Equations 11 to 14.

The constant current supplied by the constant current source 25 is I.

If we ignore the base currents of NPN) transistors 24a and 24b, we get the same relational expression as Equation 9: IC++ IC2=
Since I l-(16), the same equation as the 10th equation can be obtained from the 15th equation and the 16th equation. As described above, the collector current Icl obtained as the output current of the differential amplifier 23 is an analog signal corresponding to the projection position of the infrared light on the light receiving surface of the PSD 21.

On the other hand, in the double integral type analog-to-digital converter 28,
First, the timing control circuit 35 turns off the switches 30 and 31 and turns on the switch 32, and also applies a reset signal to the counter 36, so that the counter 36 is reset.

With this setting, the comparator 34 starts operating as a voltage follower circuit, and the second reference voltage Vref2
is taken out from the output terminal of the comparator 34, and the reference voltage Vref2 is applied to the capacitor 3 through the switch 32.
3 is applied. In this dynamic phase, capacitor 33
acts as a phase compensation element for the comparator 34 to prevent oscillation, so there is no need to perform special phase compensation to prevent oscillation, unlike when a voltage follower circuit is constructed using an operational amplifier.

The above operation causes the capacitor 33 to become the second reference voltage Vr.
After being charged to cf2, the timing control circuit 35 turns on the switch 30 and turns on the switch 32, thereby starting the first integration operation of the double integration type analog-to-digital converter 28. That is, for a predetermined period T1 from the start of this operation, the capacitor 33 transfers the charged charge to the NPN transistor 24a.
It is discharged as collector current IC+.

When time T1 has elapsed, the timing control circuit 35 turns off the switch 30 and turns on the switch 31, and the capacitor 35 switches from discharging to the NPN transistor 24a to charging by the constant current source 29.

Assuming that the capacitance of the capacitor 33 is C, the voltage vL of the capacitor 33 at the time of switching is as follows. Substituting the 17th equation into the 18th equation yields.

Further, at the above switching point, the timing control circuit 35 releases the counter 36 from the reset state, and the counter 36 starts counting the clock input from the clock generator 37. That is, the second integration operation of the double integration type analog-to-digital converter 28 is started. The voltage of the capacitor 33 charged by the constant current 2 supplied from the two constant current sources is the second reference voltage Vre f
2, the output signal of the comparator 34 is inverted from "LJ to rH", the counter 36 which receives this output signal at the enable input terminal E stops counting operation, and the voltage of the capacitor 36 becomes equal to A count value corresponding to the time T2 from the voltage VL at the start of the 2-integration operation to V r e f2 is held in the counter 36. This count value is transmitted from the output terminals Q1 to Qn to digital signals ql, q2゜... , qn. Since the amount of displacement of the voltage of the capacitor 33 from VL to V r e f 2 is , the relationship between Equations 19 and 20 holds, and from Equation 21, I + , 12.T, are all constant values, so the digital signal taken out during the period T2, that is, the counter 3d, has a value proportional to IA/(IA+l11).In other words, the analog signal taken out by the differential amplifier 23 The collector current I c+ given by Equation 17 is converted into n-bit digital signals ql, q2 by the double integral type analog-digital converter
．． ..., it has been converted to qn.

Effects of the Invention As described above, according to the arithmetic circuit of the present invention, a digital signal corresponding to the ratio of the two input analog signals can be extracted with high resolution from two input analog signals without increasing the circuit scale. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an arithmetic circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional arithmetic circuit. 22a, 22b... Logarithmic compression diode, 23...
・Differential amplifier, 28...double integral type analog-to-digital converter Agent Patent attorney Keiichi Kazu

Claims (1)

[Claims] First and second devices that receive an analog signal, compress it into a logarithmic value that includes the quantity of the analog signal as an antilog number, and output the compressed value.
2 obtained by the logarithmic compression circuit and the first and second logarithmic compression circuits.
a differential amplifier that receives two outputs as two inputs and outputs an analog signal corresponding to the ratio of the analog signal input to the first logarithmic compression circuit and the analog signal input to the second logarithmic compression circuit; An arithmetic circuit comprising: a double integral type analog-to-digital converter that converts the output of a differential amplifier into a digital signal.