TWI512954B - Ambient light sensing with stacked photodiode - Google Patents

Description

Stacked photodiode structure and photosensor

The invention relates to an ambient light sensor, and in particular to a stacked light diode structure and a light sensor thereof.

An Ambient Light Sensor (ALS) provides an output that approximates the response of the human eye to light. In order to extend the power supply time of the mobile battery and provide an optimal viewing experience in the case of indoor or outdoor light, ambient light sensors are useful for managing the brightness of the display.

Existing ambient light sensors are implemented in the following manner. The first way is that a single photodiode can be coated to mimic the human eye's response to light. The second way is to use two diodes in order to mimic the response of the human eye to light. One diode is in response to the spectrum of visible light and infrared light, and the other diode is mainly in response to infrared light. . The first approach described above results in higher manufacturing costs due to the additional coating process and the detection of sub-lux light conditions is also quite challenging. The second method described above requires occupying the area of two twin planes (due to the use of two diodes), and the difference between components and components of each photosensor is highly dependent on the photosensor. The goodness of the two diodes matching each other.

The invention provides a stacked photodiode structure and a photosensor thereof.

Embodiments of the present invention provide a stacked photodiode structure including a first conductivity type substrate, a second conductivity type well region, and a first conductivity type well region. The first conductive type substrate has a first surface and a ground. The second conductivity type well region is formed within the first conductivity type substrate and adjacent to the first surface. The first conductivity type well region is formed in the second conductivity type well region and adjacent to the first surface. A first photocurrent is generated between the first conductivity type well region and the second conductivity type well region, the first photocurrent being primarily responsive to a visible light spectrum of the first surface of the incident stacked photodiode structure. A second photocurrent is generated between the second conductivity type well region and the second PN junction of the first conductivity type substrate, and the second photo current is primarily responsive to the infrared light spectrum of the first surface of the incident stacked photodiode structure. The first photocurrent is collected by the endpoints of the first conductivity type well region and the second photocurrent is collected by the endpoints of the second conductivity type well region.

Embodiments of the present invention provide a photo sensor including a stacked photodiode structure, a first charge balance analog/digital converter, a second charge balance analog/digital converter, and a control circuit. The stacked photodiode structure includes a first conductivity type substrate, a second conductivity type well region, and a first conductivity type well region. The first conductive type substrate has a first surface and a ground. The second conductivity type well region is formed within the first conductivity type substrate and adjacent to the first surface. The first conductivity type well region is formed in the second conductivity type well region and adjacent to the first surface. A first photocurrent is generated between the first conductivity type well region and the second conductivity type well region, the first photocurrent being primarily responsive to a visible light spectrum of the first surface of the incident stacked photodiode structure. A second photocurrent is generated between the second conductivity type well region and the second PN junction of the first conductivity type substrate, and the second photo current is primarily responsive to the infrared light spectrum of the first surface of the incident stacked photodiode structure. The first photocurrent is provided by the endpoint of the first conductivity type well region and the second photocurrent is generated by the endpoint of the second conductivity type well region. The first charge-to-digital converter (ADC) has a first capacitor and is coupled to an end of the first conductivity type well region, receives the first photocurrent, and converts the first photocurrent to The first voltage. The first charge balance analog/digital converter has a first discharge reference current, and the current direction of the first discharge reference current is opposite to the current direction of the first photo current to make the first electricity The capacity is charged to the originally preset bias level. The second charge balance analog/digital converter (ADC) has a second capacitance and is coupled to an end of the second conductivity type well region. The second charge balance analog/digital converter receives the sum of the photocurrents of the first PN junction and the second PN junction, and the sum of the converted photocurrents is the second voltage. The control circuit is coupled to the first charge balance analog/digital converter and the second charge balance analog/digital converter. The second charge balance analog/digital converter has a second discharge reference current, and the current direction of the second discharge reference current is opposite to the current direction of the second photo current to discharge the second capacitor to an originally preset bias level . The control circuit receives the first voltage and the second voltage and controls the first charge balance analog/digital converter to de-integrate the first voltage from the bias voltage in response to the first photocurrent of the visible light spectrum to Below the first threshold voltage of the bias voltage, the first capacitor is then charged with a preset reference current until the first voltage is equal to the bias voltage, and the first capacitor is estimated to be responsive to the charging time of the first photo current. a control circuit controlling the second charge balance analog/digital converter to integrate the second voltage from the bias voltage to be higher than the bias voltage by a sum of photocurrents of the first PN junction and the second PN junction The second threshold voltage is then discharged to the second capacitor using the preset reference current until the second voltage is equal to the bias voltage, and the second capacitor is estimated to be responsive to the discharge time of the second photo current.

In summary, the stacked photodiode structure and the photosensor provided by the embodiments of the present invention can realize ambient light detection without using a coating process on the surface of the photodiode, which can achieve less cost and The effect of better stability. The stacked photodiode structure eliminates the coating process and eliminates the difference between components and components between the two diodes used in conventional photosensors (the two diodes of a conventional photosensor are mutually Need to match). The stacked photodiode structure can reduce the footprint of the photodiode while maintaining the same performance.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

1,21,31‧‧‧Stacked photodiode structure

101‧‧‧First Conductive Type Substrate

102‧‧‧Second conductivity type well area

103‧‧‧First Conductive Type Well Area

104‧‧‧ first surface

101a, 103a‧‧‧ heavily doped first conductivity type region

102a‧‧‧ heavily doped second conductivity type region

2,3‧‧‧Light sensor

211,212,311,312,351,352‧‧‧Light diode

I1‧‧‧First photocurrent

I2‧‧‧second photocurrent

Ig‧‧‧current

22,32‧‧‧First Charge Balance Analog/Digital Converter

23,33‧‧‧Second charge balance analog/digital converter

245,345‧‧‧Control circuit

221,321‧‧‧first capacitor

231,331‧‧‧second capacitor

222,232,322,332‧‧‧Operational amplifier

223,233,323,333‧‧‧current source

S1, S2‧‧" switch

241,341‧‧‧First multiplexer

242,342‧‧‧Second multiplexer

243,343‧‧‧First comparator

244,344‧‧‧Second comparator

V1, V2, V3, V4‧‧‧ voltage

GND‧‧‧ Grounding

IC1, IC2‧‧‧ current

35‧‧‧Dark stacked photodiode structure

X’‧‧‧dark anode end

X‧‧‧ anode end

Y’‧‧‧dark cathode end

Y‧‧‧ cathode end

1 is a cross-sectional view showing a stacked photodiode structure according to an embodiment of the present invention.

2 is a graph showing changes in optical responsivity of a stacked photodiode structure as a function of wavelength of light according to an embodiment of the present invention.

FIG. 3 is a circuit block diagram of a photosensor having a stacked photodiode structure according to an embodiment of the present invention.

4 is a timing diagram of a photosensor provided by an embodiment of the present invention.

FIG. 5 is a circuit block diagram of a photosensor having a stacked photodiode structure according to another embodiment of the present invention.

[Example of stacked photodiode structure and photosensor thereof]

1 is a cross-sectional view showing a stacked photodiode structure according to an embodiment of the present invention. The stacked photodiode structure 1 includes a first conductive type substrate 101, a second conductive type well region 102, and a first conductive type well region 103. The first conductivity type may be a p-type or an n-type, while the second conductivity type is an N-type or a P-type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the first conductivity type substrate 101 is a P-type substrate, and the second conductivity type well region 102 is an N-type well region (NWell), and the first The conductivity type well region 103 is a P-type well region (PWell). Similarly, when the first conductivity type is N-type and the second conductivity type is P-type, the first conductivity type substrate 101 is an N-type substrate, the second conductivity type well region 102 is a P-type well region, and the first conductivity type Well area 103 is an N-type well area.

The first conductive type substrate 101 has a first surface 104 and a ground end 101a (two ground ends 101a are illustrated in FIG. 1). The second conductivity type well region 102 is formed within the first conductivity type substrate 101 and adjacent to the first surface 104. The first PN junction J1 is interposed between the first conductivity type well region 103 and the second conductivity type well region 102 and generates free electrons in response to visible light incident on the first surface 104 of the stacked photodiode structure 1. The first conductivity type well region 103 is formed in the second conductivity type well region 102 and adjacent to the first A surface 104. The second PN junction J2 is interposed between the second conductivity type well region 102 and the first conductivity type substrate 101, and generates free electrons in response to infrared light incident on the first surface 104 of the stacked photodiode structure 1. The free holes generated by the first PN junction J1 may be collected at the end point 103a of the first conductivity type well region 103 (two endpoints 103a are depicted in FIG. 1), thereby generating a primary response to the visible spectrum. A photocurrent. Free electrons generated by the first PN junction J1 and the second PN junction J2 according to the photoelectric effect may be collected at the end point 102a of the second conductivity type well region 102, thereby generating a response to the visible spectrum and the infrared spectrum. Second photocurrent.

The first conductivity type is a P type, and the second conductivity type is an N type as an example. The ground terminal 101a may include at least one heavily doped P-type region formed on the P-type substrate 101, and the heavily doped P-type region is adjacent to the first surface 104 of the P-type substrate 101. At this time, the end point 102a of the N-type well region 102 is a cathode end, which may include at least one heavily doped N-type region formed in the N-type well region 102, and the heavily doped N-type region is adjacent to the P-type substrate 101. The first surface 104. The end point 103a of the P-type well region 103 is an anode end, which may include at least one heavily doped P-type region formed in the P-type well region 103, and the heavily doped P-type region is adjacent to the first of the P-type substrate 101 Surface 104. However, the invention is not so limited, the ground terminal 101a, the terminal end 102a (cathode end) and the end point 103a (anode end) may be any ohmic contact terminal, such as a metal end point. Those skilled in the art will be aware of the manner in which the above endpoints are implemented and will not be described again.

Please refer to FIG. 2. FIG. 2 is a graph showing the optical responsivity of the stacked photodiode structure according to the wavelength of the light according to an embodiment of the present invention. According to the stacked photodiode structure described above, the two diodes are vertically stacked to generate two photocurrents, one photocurrent mainly responding to visible light and the other photocurrent being responsive to visible light and infrared light (especially mainly infrared light) ),as shown in picture 2. The negative optical responsivity shown in Figure 2 is representative of the opposite polarity of the generated photocurrent (i.e., the current direction is opposite).

Please refer to FIG. 3. FIG. 3 is a circuit block diagram of a photosensor having a stacked photodiode structure according to an embodiment of the present invention. The circuit is integrated in a stacked photodiode junction To convert the photocurrent to a voltage level and then to a digital code. The photo sensor 2 includes a stacked photodiode structure 21, a first charge balance analog-to-digital converter (ADC) 22, a second charge balance analog/digital converter 23, and a control circuit 245. The stacked photodiode structure 21 may be the stacked photodiode structure 1 of FIG. 1 , wherein the photodiode 211 represents a combination of the first conductive type substrate 101, the second PN junction J2 and the second conductive type well region 102, and the photodiode Body 212 represents a combination of second conductivity type well region 102, first PN junction surface J1 and first conductivity type well region 103. The ground terminal 101a of the first conductive type substrate 101 is connected to the ground GND.

The first charge balance analog/digital converter 22 has a first capacitor 221 and is coupled to the anode terminal 103a of the first conductivity type well region 103 (ie, the anode of the photodiode 212). The second charge balance analog/digital converter 23 has a second capacitor 231 coupled to the cathode end 102a of the second conductivity type well region 102 (ie, the cathode of the photodiode 211). The control circuit 245 is coupled to the first charge balance analog/digital converter 22 and the second charge balance analog/digital converter 23.

The first charge balance analog/digital converter 22 receives the first photo current I1 and converts the first photo current I1 to a first voltage V1. In more detail, the first photocurrent I1 discharges the first capacitor 221 to the first voltage V1. The second charge balance analog/digital converter 23 receives the second photo current I2 and converts the second photo current 23 to the second voltage V2. In more detail, the second photocurrent I2 charges the second capacitor 231 to the second voltage. The control circuit 245 receives the third voltage (first comparison signal) V3 and the fourth voltage (second comparison signal) V4, and controls the first charge balance analog/digital converter 22 to decouple the first voltage V1 from the bias voltage VBIAS. De-integrate to a first threshold voltage (VBIAS-VTH) below the bias voltage VBIAS, which is a predetermined threshold voltage. Then, the control circuit 245 integrates (charges) the first capacitor 221 with the current source 223 until the first voltage V1 is equal to the bias voltage VBIAS, and estimates that the first capacitor 221 is responsive to the charging time T1 of the first photo current I1. Control circuit 245 and controlling second charge balance analog/digital converter 23 to integrate second voltage V2 from bias voltage VBIAS to greater than said bias voltage The second threshold voltage of VBIAS (VBIAS+VTH), VTH is the preset threshold voltage. Then, the control circuit 245 discharges the second capacitor 231 with the current source 233 until the second voltage V2 is equal to the bias voltage VBIAS, and estimates that the second capacitor 231 is responsive to the charging time T2 of the second photo current I2.

The second photocurrent I2 flows into the photodiode 211 and the photodiode 212, representing that the second photocurrent I2 is responsive to visible light and infrared light. The first photocurrent I1 flows out of the photodiode 212, and represents that the first photocurrent I1 is mainly responsive to visible light. The first photocurrent I1 is a part of the second photocurrent I2, and the second photocurrent I2 is subtracted from the ground current Ig flowing into the photodiode 211 to obtain the first photocurrent I1.

Specifically, the first charge balance analog/digital converter 22 further includes an operation amplifier 222, a current source 223, a first multiplexer 241, and a first comparator 243. The operational amplifier 222 has an inverting input, a non-inverting input, and an output. The non-inverting input receives the bias voltage VBIAS. The current source 223 is coupled to the inverting input of the operational amplifier 222 and is controlled by the control circuit 245 to provide a reference current IREF to charge the first capacitor 221. The first capacitor 221 is coupled between the inverting input terminal and the output terminal of the operational amplifier 222 to establish a feedback path. The first multiplexer 241 selectively provides a bias voltage VBIAS or a first threshold voltage VBIAS-VTH as a first reference signal. The first comparator 243 compares the first voltage V1 with the first reference signal and outputs the first comparison signal V3.

The second charge balance analog/digital converter 23 further includes an operational amplifier 232, a current source 233, a second multiplexer 242, and a second comparator 244. The operational amplifier 232 has an inverting input, a non-inverting input, and an output. The non-inverting input receives the bias voltage VBIAS. The current source 233 is coupled to the inverting input of the operational amplifier 232 and is controlled by the control circuit 245 to provide a reference current IREF to discharge the second capacitor 231. The second capacitor 231 is coupled between the inverting input terminal and the output terminal of the operational amplifier 232 to establish a feedback path. The second multiplexer 242 selectively provides a bias voltage VBIAS or a second threshold voltage VBIAS+VTH as a second reference signal. The second comparator 244 compares the second voltage V2 with the second reference signal and outputs a second comparison signal V4.

Control circuit 245 can be a digital control unit. Control circuit 245 receives the first Comparing the signal V3 with the second comparison signal V4, and controlling the first multiplexer 241 and the second multiplexer 242, and controlling the first charge balance analog/digital converter 22 and the second charge balance analog/digital converter 23 Points/de-integration time.

The reference current IREF of the current source 223 represents the largest measurable second current I2, and the polarity of the reference current IREF of the current source 223 is opposite to the first photo current I1 (at the inverting input of the operational amplifier 222). The reference current IREF can be a variety of current levels and can be programmed by the user, thereby adjusting a portion of the sensitivity level of the photosensor. The reference current IREF of the current source 233 represents the maximum possible second photocurrent I2, and the polarity of the reference current IREF of the current source 233 is opposite to the first photocurrent I2 (at the inverting input of the operational amplifier 232). The second capacitor 231 can be charged by the second photocurrent I2 and discharged by the current source 233 (having a reference current IREF) to operate as a charge balance analog/digital converter. Likewise, the first capacitor 221 can be discharged by the first photocurrent I1 and charged by the current source 223 (with the reference current IREF) to operate as a charge balance analog/digital converter.

Figure 4 illustrates the waveform of the integrated output, including the waveforms of the first voltage V1 and the second voltage V2. FIG. 4 also discloses the waveform output by the comparator, including the first comparison signal V3 and the second comparison signal V4. The integrator used represents a feedback path formed by the first capacitor 221 (or the second capacitor 231) to which the operational amplifier 222 (or 232) is connected.

The second capacitor 231 is charged by the second photocurrent I2 and is boosted by the bias voltage VBIAS to the second threshold voltage VBIAS+VTH, at which time the output of the comparator (comparison signal V4) becomes a logic H (High). The digital control circuit 245 detects this logic H and switches the reference voltage (ie, the reference signal) from VBIAS+VTH to VBIAS through the multiplexer 242. This action is to ensure that the second comparison signal V4 output by the second comparator 244 can be maintained at a logic H throughout the discharge period. At this time, the current source 233 can be turned ON (transmitted through the switch S2), and when the second capacitor 231 is discharged by the current I2-IREF (refer to the discharge time T2 of FIG. 4), the counter of the digital control circuit 245 (FIG. 4) Not counting) starts counting until the second voltage V2 returns to VBIAS. When the second voltage V2 returns to the bias voltage VBIAS, the second comparison signal V4 output by the second comparator 244 returns to the logic L (Low), The reference voltage is switched back to VBIAS+VTH, current source 233 is turned off (via switch S2), and the counter stops counting. The cycle of the next charge and discharge can be repeated again until the set integration time, where the count value of the counter is proportional to the second photocurrent I2. The logic H of the second comparison signal V4 may be interchanged with the logic L (High or Low), or may instead be pulsed only during the transition phase of integration and de-integration, as long as the reference current source 233 is turned "ON" The counter of the control circuit 245 continues to count.

The integrator composed of the operational amplifier 222 and the first capacitor 221 and the second comparator 243 operate in a similar procedure. Because the polarity of the first photocurrent I1 and the second photocurrent I2 are opposite, the voltage (1) of the first capacitor 221 can start to be discharged by the first photocurrent I1, and discharged by the reference voltage VBIAS to the voltage VBIAS-VTH, at this time, The first comparison signal V3 output by the comparator 243 is a logic H. The digital control circuit 245 senses this logic H and switches the reference voltage (ie, the reference signal) from VBIAS-VTH to VBIAS through the first multiplexer 241. This action is to ensure that the first comparison signal V3 output by the first comparator 243 can be maintained at logic H throughout the discharge period. At this time, the current source 223 can be turned ON (transmitted through the switch S1), and when the first capacitor 221 is discharged with the current -I1+IREF, the counter of the digital control circuit 245 (not shown in FIG. 4) starts counting until The first voltage V1 returns to VBIAS. When the first voltage V1 returns to the bias voltage VBIAS, the first comparison signal V3 output by the first comparator 243 returns to logic L (Low), the reference voltage is switched back to VBIAS-VTH, and the current source 233 is turned off (OFF) ( Pass switch S1) and the counter stops counting. The period of charging and discharging can be repeated again until the set integration time, wherein the counter value is proportional to the first photo current I1. The logic H of the first comparison signal V3 may be interchanged with the logic L (High or Low), or may be generated only during the transition phase of integration and de-integration, as long as the reference current source 223 is turned "ON" The counter of the control circuit 245 continues to count.

[Another embodiment of a stacked photodiode structure and its photo sensor]

As shown in FIG. 5, FIG. 5 is a stack light 2 according to another embodiment of the present invention. A circuit block diagram of a photosensor of a polar body structure. A dark stacked photodiode structure 35 is incorporated in the circuit of FIG. The photo sensor 3 includes a stacked photodiode structure 31, a dark stacked photodiode structure 35, a first charge balance analog/digital converter 32, a second charge balance analog/digital converter 33, and a control circuit 345. The stacked photodiode structure 31 can be the same as the stacked photodiode structure 1 shown in FIG. 1. At this time, the photodiode 311 represents the first conductive type substrate 101, the second PN junction J2, and the second conductive type well region 102. In combination, photodiode 312 represents a combination of second conductivity type well region 102, first PN junction J1 and first conductivity type well region 103.

The first charge balance analog/digital converter 32 has a first capacitor 321 and is coupled to the anode terminal end 103a of the first conductivity type well region 103 (ie, the anode of the photodiode 312). The second charge balance analog/digital converter 33 has a second capacitor 331 and is coupled to the cathode end point 102a of the second conductivity type well region 102 (ie, the cathode of the photodiode 311). The control circuit 345 is coupled to the first charge balance analog/digital converter 32 and the second charge balance analog/digital converter 33. The first charge balance analog/digital converter 32, the second charge balance analog/digital converter 33 and the control circuit 345 can respectively be the first charge balance analog/digital converter 22, the second charge balance analog/digital converter 23 and the control Circuit 245 is the same and will not be described again.

The dark stacked photodiode structure 35 can be completely covered by the metal cover to prevent all light (including visible light and infrared light) from being incident to produce the same dark current as the stacked photodiode structure 31, thereby Good sensing accuracy is achieved with high ambient temperature or low ambient temperature. The dark anode end X' of the dark stacked photodiode structure 35 is coupled to the anode end X of the stacked photodiode structure 31, and the dark cathode end Y' of the dark stacked photodiode structure 35 is coupled to the stacked photodiode The cathode end Y of the bulk structure 31.

[Possible effects of the examples]

According to an embodiment of the present invention, the above-described stacked photodiode structure and its photosensor omits the use of a plurality of parallel arranged photodiodes, thereby simulating the human eye's response to light. In this way, half of the area of the photodiode can be reduced, and the conventional light is eliminated. The critical needs of the sensors' diodes need to match each other.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

2‧‧‧Light sensor

211,212‧‧‧Light diode

I1‧‧‧First photocurrent

I2‧‧‧second photocurrent

Ig‧‧‧current

22‧‧‧First Charge Balance Analog/Digital Converter

23‧‧‧Second charge balance analog/digital converter

245‧‧‧Control circuit

221‧‧‧first capacitor

231‧‧‧second capacitor

222,232‧‧‧Operational Amplifier

223, 233‧‧‧ Current source

S1, S2‧‧" switch

241‧‧‧First multiplexer

242‧‧‧Second multiplexer

243‧‧‧First comparator

244‧‧‧Second comparator

V1, V2, V3, V4‧‧‧ voltage

GND‧‧‧ Grounding

IC1, IC2‧‧‧ current

Claims (6)

A light sensor comprising: a stacked photodiode structure comprising: a first conductivity type substrate having a first surface and a ground; a second conductivity type well region formed on the first conductivity type substrate And adjacent to the first surface; and a first conductivity type well region formed in the second conductivity type well region adjacent to the first surface; wherein the first conductivity type well region and the second conductive region a first PN junction between the type well regions generates free electrons according to a spectrum of visible light corresponding to the incident first surface; wherein a second portion of the second conductivity type well region and the first conductivity type substrate The PN junction generates free holes and free electrons mainly according to a spectrum of infrared light corresponding to the first surface; wherein a first photocurrent is collected by an anode end of the first conductivity type well region, the first light The current is in response to the visible light spectrum, and a second photocurrent is collected by the cathode end of the second conductivity type well region, the second photocurrent is in response to the visible light spectrum and the infrared light spectrum, a first charging level An analog-to-digital converter (ADC) having a first capacitor coupled to the anode/cathode of the first conductivity type well region, receiving the first photocurrent and converting the first light The current is a first voltage; a second charge-to-digital converter (ADC) has a second capacitor coupled to the anode/cathode of the second conductivity type well region, and receives The second photocurrent and converting the second photocurrent to a second voltage; and a control circuit coupled to the first charge balance analog/digital converter and the second charge balance analog/digital converter to receive the second photocurrent a voltage and the second voltage, controlling the first charge balance analog/digital converter to integrate the first voltage and by a bias The voltage is integrated to a first threshold voltage, the first threshold voltage is lower than the bias voltage by a predetermined voltage, and then the first capacitor is charged until the first voltage is equal to the bias voltage, and the first capacitor is estimated to be responsive to the a charging time of the first photocurrent, the control circuit controls the second charge balance analog/digital converter to integrate the second voltage and integrate the bias voltage to a second threshold voltage, the second threshold voltage being higher than the bias voltage The preset voltage is pressed, and then the second capacitor is discharged until the second voltage is equal to the bias voltage, and the second capacitor is estimated to be responsive to the discharge time of the second photo current. The optical sensor of claim 1, wherein the first charge balance analog/digital converter further comprises: an amplifier having an inverting input, a non-inverting input, and an output, the non-reverse Receiving the bias voltage to the input terminal; a current source coupled to the inverting input terminal of the amplifier, controlled by the control circuit to provide a reference current to discharge the first capacitor, wherein the reference current is greater than the first a second photocurrent; a first multiplexer selectively providing the bias voltage or the first threshold voltage as a first reference signal; a first comparator comparing the first voltage and the first reference signal, and Outputting a first comparison signal; wherein the first capacitor is coupled between the inverting input terminal of the amplifier and the output terminal; wherein the control circuit receives the first comparison signal and controls the first charging balance The integration/de-integration time of the analog/digital converter and the second charge balance analog/digital converter. The optical sensor of claim 1, wherein the second charge balance analog/digital converter further comprises: an amplifier having an inverting input, a non-inverting input, and an output, the non-reverse Receiving the bias voltage to the input terminal; a current source coupled to the inverting input of the amplifier, controlled by the control circuit to provide a reference current to charge the second capacitor, wherein the reference current is greater than the second photocurrent; The device selectively provides the bias voltage or the second threshold voltage as a second reference signal; a second comparator compares the second voltage and the second reference signal and outputs a second comparison signal; The second capacitor is coupled between the inverting input terminal of the amplifier and the output terminal; wherein the control circuit receives the second comparison signal and controls the first charge balance analog/digital converter and the first The integration/de-integration time of the second charge balance analog/digital converter. The optical sensor of claim 1, further comprising: a dark stacked photodiode structure having the same structure as the stacked photodiode structure, and further comprising: a metal cover covering the dark stack a photodiode structure for preventing visible light and infrared light from entering the dark stacked photodiode structure; wherein a dark anode end of the dark stacked photodiode structure is coupled to the anode end of the stacked photodiode structure, One dark cathode end of the dark stacked photodiode structure is coupled to the cathode end of the stacked photodiode structure. The photosensor of claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The photosensor of claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type.