JPH01259643A - Serial communication circuit - Google Patents

Abstract

PURPOSE:To enhance reliability of transfer data and to transfer them at high speed by so constructing the title circuit that it can perform a transmitting and receiving operation based on either a serial transfer synchronizing clock generated inside or a serial transfer synchronizing clock inputted from the outside. CONSTITUTION:A communication circuit F on the left side of the figure operators in accordance with a control signal generated based on a serial transfer synchronizing clock SCK generated inside a clock generator control circuit 6F of the circuit itself and a communication circuit F on the right side operates in accordance with a control signal generated in a synchronous circuit control logic circuit 7F of the circuit itself based on a serial transfer synchronizing clock SCK inputted from the left-side circuit F. Since the right and left communication circuits F and F operate synchronously and transmit and receive the serial data mutually, serial communication between microcomputers can be made and the functions of a microcomputer system can be strengthened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a serial communication circuit that serially transmits and receives data.

(Conventional technology) As a conventional serial communication circuit, the following three
Seed methods are known.

(1) A method of inputting or outputting a shift clock only during transfer. As shown in FIG. 5(a), this is a communication circuit equipped with a transmission/reception shift register IA and a clock generator 2A that supplies a shift clock SCK to it. A and a communication circuit B including a transmission/reception shift register IB which operates upon receiving a shift clock SCK from the circuit A. In this method, as shown in FIG. 5(b), the shift clock SCK
are output only when data is to be transferred, and only at that time data DI, D2 .・・・
, D7 is transferred.

This method uses the communication circuit A as an interface between the microcomputer and peripheral circuits of a microcomputer system, for example.

If you use circuit A on the microcomputer side and circuit B on the peripheral circuit side to generate the shift clock SCK based on the microcomputer clock, the interface will have a shift clock SCK. Since only registers are required, the configuration is extremely simple, and there are advantages in that data transfer can be performed at high speed.

However, without configuring the transferred data into a special format,
Since data is transferred solely in accordance with the shift clock, erroneous transfers are likely to occur due to noise and the like, resulting in problems with the reliability of the transferred data.

(2) Start-stop synchronization method As shown in FIG. 6(a), this method consists of a clock generator 92C that generates an internal sampling clock, a reception shift register 3C that receives data, a transmission shift register 4C that transmits data, and It is made up of a combination of a community circuit C2C having the same configuration and a control logic circuit 5C which provides a shift clock generated by frequency-dividing the internal sampling clock by 8 or 16 to the shift registers 3C and 4C.

In this method, as shown in FIG. 6(b), the transfer data Do, D1 . . . . The data format is determined to be transferred with predetermined start bits and stop bits before and after D7, and the control logic circuit 5
C detects the start bit from the reception signal SIN to confirm the start of data reception, detects the stop bit and confirms the completion of data reception, and controls the operation timing of the reception shift register 3C based on these confirmations. It is designed to check for errors in transferred data.

In this method, since the format of the transfer data is fixed, it is possible to confirm the start and end of reception based on this, so there is no need to synchronize between circuits C9C, and transfer is based on the presence or absence of stop bits and start bits. Since data errors can be checked, the reliability of transferred data is high, and it is the basic configuration of serial communication circuits.

Furthermore, the start bit and stop bit detection method used to perform these checks involves sampling these bits using an internal sampling clock that normally has a rate of 8 or 16 times the transfer rate. Since a majority decision method that makes decisions based on majority decision can be adopted, noise resistance can be improved.

However, in this method, the transfer rate is limited to 1/8 or 1/16 of the internal sampling clock, so only a relatively low transfer rate can be achieved.

(3) Synchronization method As shown in FIG. 7(a), this synchronization method uses a reception shift register 3D, a transmission shift register 4D, and a reference signal that provides a shift clock to these shift registers 3D and 4D and generates a shift clock. A communication circuit includes a clock generator/control logic circuit 6D that outputs a serial transfer synchronization clock SCK to the outside, a reception shift register 3E, a transmission shift register 4E, and a communication circuit that receives the serial transfer synchronization clock SCK from the circuit. shift register 3E of own circuit
, 4E in combination with a communication circuit E provided with a control logic circuit 5E that generates shift clocks for 4E.

Even in this method, as shown in FIG. 7(b), the format is determined so that the transfer data DO, DI, . . . Generator control logic circuit 6D and control logic circuit 5E each confirm the start of data reception by detecting a start bit, and confirm the completion of data reception by detecting a stop bit.

In this method, since the format of the transferred data is fixed, it is possible to check for errors in sending and receiving, so the data reliability is high, and the transfer rate can be increased, which is the method described in (1) and (2) above. It combines the advantages of each.

However, it is necessary to combine a circuit that operates actively using an internally generated clock and a circuit E that operates passively using an externally supplied clock. Circuits E cannot be combined. Therefore, when applying this method as an interface between a microcomputer and a peripheral circuit in a microcomputer system, for example, an active circuit is used on the microcomputer side that has a clock generation means, and an active circuit is used in the peripheral circuit that does not have a clock generation means. Although a passive circuit E can be used on the side, this method cannot be applied to interfaces between microcomputers each having its own internal clock.

(Issue 8 to be solved by the invention) As described above, conventional serial communication circuits are capable of increasing the speed of transfer data using method <1), but lack reliability, and method (2) According to the method (3), the reliability of the transferred data can be improved, but the high speed is lacking.Also, the method (3) can improve both the reliability and the high speed of the transferred data, but it is not possible to improve the reliability and high speed of the transferred data. It cannot be applied to interfaces between circuits that have

The present invention has been made in view of the above, and provides a serial communication circuit that can improve both the reliability and high speed of transferred data, and can also interface between circuits that have their own internal clocks, such as microcomputers. The purpose is to provide

[Structure of the invention]

(Means for Solving the Problems) To achieve the above object, the present invention provides a serial communication circuit that transmits and receives serial data in a predetermined format, internally generates a serial transfer synchronization clock and outputs it to the outside. an internal control circuit that generates a control signal for controlling the transmission/reception operation based on the internally generated serial transfer synchronization clock and a detection result of the format of the transmitted/received data; and an externally generated serial transfer synchronization clock and the transmitted/received data. an external synchronization control circuit that generates a control signal for controlling the transmission/reception operation based on the detection result of the format; and control from a circuit selected by selecting one of the internal control circuit and the external synchronization control circuit. a selection circuit that controls the transmission/reception operation based on a signal, and the external synchronization control circuit is configured such that the phase relationship between the externally input serial transfer synchronization clock and the control signal generated based thereon is determined by the internal control circuit. The present invention provides a serial communication circuit characterized in that the control signal is generated so that the phase relationship between the serial transfer synchronization clock and the control signal is substantially the same as that of the control signal.

(Function) When the communication circuit with the above configuration is used as a communication interface between microcomputers, the communication circuit on one computer side selects the internal control circuit using the selection circuit and performs control based on the internally generated serial transfer synchronization clock. Sends and receives signals. In the communication circuit on the other computer side, a selection circuit selects an external synchronization control circuit, and transmission and reception are performed using a control signal based on a serial transfer synchronization clock externally inputted from the communication circuit on the other side. The phase relationship between the serial transfer synchronization clock generated by the internal control circuit and the control signal is almost the same as the phase relationship between the externally input serial transfer synchronization clock and the control signal generated by the external synchronization control circuit based on this clock. The communication circuits of both computers perform transmission and reception operations in synchronization, and communication between the microcomputers is realized.

In addition, the transferred data is sent and received in a predetermined format,
Since transmission and reception are controlled based on the detection of the format, the reliability of transferred data is high. It is also possible to speed up the transfer.

(Example) Examples will be explained below.

FIG. 1 is a block diagram showing the configuration of an embodiment of the serial communication circuit according to the present invention, FIG. FIG. 4 is a timing chart showing the operation of this embodiment.

As shown in FIG. 1, this embodiment includes a reception shift register 3F, a transmission shift register 4F, and a clock that internally generates a serial transfer synchronization clock SCK and generates various control signals for controlling transmission and reception based on the serial transfer synchronization clock SCK. Generator control logic circuit 6F,
A synchronization circuit that generates the various control signals mentioned above based on the serial transfer synchronization clock SCK given from the outside.
It is constituted by a combination of communication circuits F and F having the same configuration, each including a control logic circuit 7F and a selection circuit 8F for selecting one of the circuits 6F and 7F. In the circuit F on the left side of the drawing, the clock generator and control logic circuit 6F are selected by the selection circuit 8F, and the circuit F operates according to the internally generated serial transfer synchronization clock SCK.
The control logic circuit 7F is selected and operates according to the externally input serial transfer synchronization clock SCK.

Clock generator/control logic circuit 6F
As shown in FIG. 3, the basic timing clock Φ1 is based on the internally generated sampling clock
．． Φ2 is generated, and based on this, a serial transfer synchronization clock SCK is generated.

This serial transfer synchronization clock SCK can be output externally as described above. Furthermore, this circuit 6F
are various control signals for controlling transmission and reception based on the basic timing clock Φ1゜Φ2 and the serial transfer synchronization clock SCK, such as a reception register shift signal, a transmission register shift signal, a reception completion request signal, and a transmission start request. Generate signals etc. Note that this embodiment is assumed to be used as an interface between microcomputers, and the sampling clock
A signal divided by 1/n (n-1 or 2) of the crystal oscillation clock of the microcomputer can be used for OUT. The receiving register shift signal and the transmitting register shift signal are respectively applied to the receiving shift register 3F and the transmitting shift register 4F via the selection circuit 8F, thereby performing a receiving operation and a transmitting operation. Furthermore, the format is defined so that a start bit and a stop bit are added before and after the transfer data to be sent and received, and the detection of the start bit and stop bit confirms the start of reception and the confirmation of completion of reception. The components involved in the generation of control signals are the same as in the conventional method.

The reception completion request signal and the transmission start request signal are output when a stop bit is detected during reception and when the next bit is transmitted after the start bit is transmitted during transmission, respectively, and are sent to the microcomputer via the selection circuit 8F. Sent.

The reception completion signal and transmission start signal sent to the microcomputer are closely related to the operation of the microcomputer, and therefore requirements corresponding to the operation of the microcomputer are usually imposed. For example, in this embodiment, it is required to have the same pulse width as the basic operating cycle of the microcomputer.

As shown in FIG. 4, the synchronization circuit/control logic circuit 7F receives an externally input serial transfer synchronization clock SC.
Based on K, external basic timing chart EXTO1
, EXTO2, and EXTΦ2', and generates various control signals such as a reception register shift signal, a transmission register shift signal, a reception completion request signal, and a transmission start request signal based on this and an externally input serial transfer synchronization clock SCK. It is something. At that time, the external input serial transfer synchronization clock SCK and the external basic timing clock E
XTΦ1. The basic timing clocks Φ1. The external basic timing clock EXTΦ1. EXTΦ2. EXTΦ2′
generate. In other words, after the external manual serial transfer synchronization clock SCK rises, the first sampling clock
External basic timing clock EX at the falling edge of OUT
Generate TΦ1 and use it as the sampling clock
The external basic timing clock EXTΦ2 is generated by shifting the UT by three clocks, and this is further shifted by three clocks to generate the external basic timing clock EXTΦ2'. In addition, external basic timing clock EXTΦ
2' is used to generate a pulse width signal for the basic operation cycle of the microcomputer when the transfer rate of the external input serial transfer synchronization clock SCK is slow. By adopting this signal generation method, the phase relationship between the externally input serial transfer synchronization clock SCK and various control signals based on it can be ignored, although there is an error within the pulse width range of the sampling clock x our. , is substantially the same as the phase relationship between the internally generated serial transfer synchronization clock SCK and various control signals based thereon, as shown in FIG. Therefore, it is possible to perform the same transmission and reception operations as in the case of following the externally input serial transfer synchronizing clock SCK and following the internally generated serial transfer synchronizing clock SCK. In that case, the externally input serial transfer synchronization clock SCK does not necessarily occur at the same timing as the internally generated serial transfer synchronization clock SCK, and the two normally have different phases. This is not a problem at all because it can be overcome by adjusting the time when transmitting received data to the microcomputer and when receiving transmitted data from the microcomputer.

From the above explanation, external basic timing clock EXTΦ
1. EXTΦ2. EXTΦ2' is an externally input serial transfer synchronization clock SCK as a sampling clock
It can be seen that the signal can be formed by combining signals sequentially shifted by the UT.

Therefore, as shown in FIG. 2, the synchronization circuit/control logic circuit 7F includes, for example, a shift register 10 formed by connecting D-type flip-flops 9 in multiple stages, and an externally input serial transfer synchronization clock SCK as an input. , the sampling clock X OUT as a shift signal
, and the output signals of each stage of the shift register 10 are combined in the control logic circuit 11 to generate a desired external basic timing clock EXTΦ1. EXTΦ21EX
An extremely simple configuration can be adopted in which TΦ2' is generated. In the case of this embodiment, since the time width from the rise of EXTΦ1 to the fall of EXTΦ2' corresponds to 11 clocks of the sampling clock X OUT, 11 stages of flip-flops 9 are connected. If the above-mentioned time width is different from the above, it can be easily handled by changing the number of stages of the flip-flops 9.

As mentioned above, the communication circuit F on the left side of Figure 1
operates according to the control signal generated based on the serial transfer synchronization clock SCK internally generated by the clock generator control logic circuit 6F of its own circuit, and the communication circuit F on the right side operates based on the serial transfer synchronization clock SCK externally input from the left circuit F. It operates according to a control signal generated by the synchronous circuit command control logic circuit 7F of its own circuit.

The phase relationship between the externally input serial transfer synchronization clock SCK and the control signal generated by the synchronization circuit/control circuit 7F is the phase relationship between the serial transfer synchronization clock SCK internally generated by the clock generator/control logic circuit 6F and the control signal. Since the relationship is almost the same, the left and right communication circuits F and F in FIG. 1 operate synchronously and mutually transmit and receive serial data. Therefore, serial communication between microcomputers becomes possible, and the functionality of the microcomputer system can be greatly enhanced.

〔Effect of the invention〕

As explained above, according to the present invention, the configuration is such that transmission and reception operations can be performed based on either an internally generated serial transfer synchronization clock or an externally input serial transfer synchronization clock, so that it can be used as a communication interface between microcomputers. Since it is configured to control transmission and reception operations based on the format of the transferred data, the reliability of the transferred data is high, and high-speed transfer is also possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a serial communication circuit according to the present invention, FIG. 2 is a block diagram showing a synchronization circuit/control logic circuit of the embodiment, and FIG. FIG. 4 is a time chart showing signal timing when the same embodiment operates according to an internally generated serial transfer synchronization clock; FIG. 5 is a time chart showing signal timing when the same embodiment operates according to an externally input serial transfer synchronization clock; FIGS. 6 and 7 are explanatory diagrams showing the configuration and operation of a conventional serial communication circuit. F...Serial communication 32 circuits, 3F...
Shift register for reception, 4F...Shift register for transmission, 6F...Clock generator or control logic circuit, 7F...Synchronization circuit or control logic circuit, 8F...Selection circuit, 9...D type flip-flop 10...shift register, 11...control logic circuit. Procedural City Official Book May 130, 1988] Indication of the case 1986 Patent Application No. 86600 2 Name of the invention Serial Communication Circuit 3 Relationship with the amendment person case Patent applicant (307) Toshiba Corporation 4 representative Person 7 Subject of amendment 1'・-'2J Destroyed drawing 8 Contents of amendment

Claims (1)

[Claims] 1. In a serial communication circuit that transmits and receives serial data in a predetermined format, a serial transfer synchronization clock is internally generated and outputted to the outside, and the internally generated serial transfer synchronization clock and the detection result of the format of the transmitted and received data are an internal control circuit that generates a control signal for controlling the transmitting/receiving operation based on an externally input serial transfer synchronization clock and a detection result of the format of the transmitted/receiving data. an external synchronization control circuit that generates a signal; and a selection circuit that selects one of the internal control circuit and the external synchronization control circuit and controls the transmission and reception operation by a control signal from the selected circuit, and the external synchronization control circuit The circuit has a phase relationship between the externally input serial transfer synchronization clock and the control signal generated based on the clock.
A serial communication circuit characterized in that the control signal is generated so that the phase relationship between the control signal and the serial transfer synchronization clock generated by the internal control circuit is substantially the same.