JPH01258185A - Network controller - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to determine one connection state of a network with a simple control by controlling input signal busses, which should be connected, in accordance with bus connection information supplied from an external host by plural first bus selecting means provided for respective output signal busses respectively. CONSTITUTION:When an input signal bus #1 5 will be connected to an output signal bus #2 6, bus connection information 8 is outputted from a host 7 to L-number of bus selecting means 4-1 (#2)-4-L (#2) connected to the output signal bus #2 6 to select the input signal bus #1 5. This control is performed for each of output signal busses #1-#N 6 to determine the connection state of the whole of the network. Thus, integration is facilitated because of the simple circuit constitution and the device scale is reduced, and the network is easily set and confirmed without requiring a special algorithm.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a network control device for controlling the pipeline connection structure (network), etc. of a pipeline image processing system, which is an image processing system with excellent high-speed performance, and which has a simple circuit configuration. The connection state of one network can be determined by simple control, there is no limit to the number of nodes, and the connection state of one input/output can be known just by detecting the connection state of a certain switch. In addition, the purpose is to make it possible to control the switches corresponding to each signal line simultaneously at one time, and to control the second plurality of input signals for the signal bus consisting of the first plurality of signal lines. The plurality of first bus selection means individually performs the operation of connecting any one of the buses to the output signal bus for each signal line, corresponding to each of the third plurality of output signal buses. Configure it as follows.

Further, which of the input signal buses each of the first plurality of bus selection means provided for each output signal bus connects is controlled by bus connection information supplied from an external host, and the host One bus connection information is simultaneously supplied to the first plurality of bus selection means, and a response signal indicating whether or not the bus connection information is normally supplied is only from one of the first plurality of bus selection means. By sending the signal back to the host, the connection control of the first plurality of bus selection means corresponding to each signal line of a desired output signal bus among the respective output signal buses is performed simultaneously.

[Industrial application field]

The present invention relates to a network control device for controlling a pipeline connection structure (network), etc. of a pipeline image processing system, which is an image processing system with excellent high speed performance.

[Conventional technology]

2. Description of the Related Art In recent image processing systems and the like, there has been a demand for moving image processing that performs various types of image processing at high speed as vision systems for automatic monitoring devices, robots, and the like.

An image processing system using a pipeline architecture is a technology that meets these demands. Pipeline architecture implements basic operations such as binarization, density conversion, edge extraction, feature point extraction, labeling, and spatial filtering on image signals in hardware as module units, and operates each module in parallel using a basic clock. High-speed performance is achieved by connecting them to each other.

In this case, since the type and order of performing the above-mentioned basic operations differ depending on the type of image processing, it is necessary to be able to flexibly change the pipeline connection structure in order to respond to these changes one by one.

A network control device connects a basic calculation module for image processing to each node (connection point) of a network, and realizes various types of image processing by changing the connection state of the network.

Such a network control device can be applied not only to image processing but also to audio processing and the like.

The conventional network control device is B P N (Ben
Based on the principle of Permutation Network), by combining switches 3 having four connection states as shown in Fig. 5(a) to (d) and providing a link connection structure as shown in Fig. 4. , for example 8
A configuration in which each image output 1 of #00 to #07, which is an output from each basic calculation module, can be arbitrarily connected to each image output 2 of #00 to #07, which is an input to the same basic calculation module. It had

[Problem to be solved by the invention]

However, in the case of the conventional example with the configuration shown in Figure 4, it takes ml to realize an 8x8 network as shown in the figure.
- 20 switches 3 of 11h20 must be prepared, and the input/output of each basic calculation module is usually 12
Since it is about a bit, it is necessary to provide 12 configurations as shown in FIG. 4 in parallel, and in the end, the total number of switches 3 is 20 x 12 = 240.

Therefore, when the number of nodes increases to several dozen, there is a problem in that the number of switches becomes enormous.

In addition, in order to determine the connection state of one of the networks, it is necessary to control all the connection states of the switches 3 of Ilh 1-N120 in FIG. This has the problem of requiring a special algorithm and complicating network control.

Therefore, if you want to know the current network connection status, for example, you cannot immediately know which image output 1 is connected to which image output 2 just by looking at the connection status of one switch 3. Can't do it, positive 1~N
Since the connection status of the network cannot be known until after the connection status of all the switches 3 of 1120 has been detected, there is a problem in that a prompt response cannot be taken.

Furthermore, the principle of the BPN that implements the configuration shown in FIG. 4 has a problem in that the number of nodes is basically limited to a power of two.

Furthermore, when the configuration of FIG. 4 is provided in parallel corresponding to each of the 12 bits, for example, when bit 1 of image output 1 of #00 is connected to bit 1 of image output 2 of #07, Similarly, bits 2 to 12 of image output 1 in #00 are bits 2 to 12 in image output 2 in #07.
Connected to bit 12. That is, the connection states of the switches 1 to 20 in the configuration shown in FIG.
2 and all are the same. However, in the past, control signals were sent to each of the switches 3 of the switch 1 to 20 corresponding to each bit separately, so it took a long time to complete the connection control of the switches 3 of the entire network. It had some problems.

The present invention has a simple circuit configuration, allows the connection state of one network to be determined by simple control, has no limit to the number of nodes, and only detects the connection state of a certain switch. It is an object of the present invention to make it possible to know the connection state of input and output, and to control the switches corresponding to each signal line at the same time.

[Means to solve the problem]

FIG. 1 (al and 2) is a block diagram of a network control device according to the present invention. First, in FIG. 1(a), there are M input signal buses 5 #1 to #M connected to the outputs of a second plurality, that is, M basic arithmetic modules for image processing, for example, and a third plurality of input signal buses 5. That is, #1 connected to inputs to N basic calculation modules similar to those above, for example.
It has N output signal buses 6 of ~#N, and each input signal bus 5 and each output signal bus 6 are connected to 5-1 to 5-L and 6, respectively.
It consists of a first plurality of signal lines from -1 to 6-L, that is, L signal lines. Here, for example, M-N, M(-N
) input signal buses 5 and N(-M) output signal buses 6 of #1 to #N are connected to each output and input of M(-N) basic arithmetic modules, respectively. In this case, FIG. 1 shows a network control device for an image processing system having a Vibrine architecture consisting of M(-N) basic arithmetic modules. In addition, M or N
The value of is not restricted at all.

In FIG. 1 (al), the #1 output signal bus 6 has #
Any one of the input signal buses 5 from 1 to #M to #1 above.
L bus selection means 4-1 (#1) to individually perform the operation of connecting to the output signal bus 6 for each of the L signal lines;
4-L (#1) is connected.

For each output signal bus 6 from #2 to #N, bus selection means 4-1 (#2) to 4-L (
#2) , ..., 4-1 (#N) ~ 4-L (
#N) is connected.

Also, for example, 4-1 connected to the output signal bus 6 of #l
(#1) to 4-L (#1) bus selection means #1 to #
Which of the M input signal buses 5 to connect is determined by the first
As shown in Figure (b), bus connection information is supplied from an external host 7, for example a CPU! l! 8. And host 7 is 4-1 (#1) to 4-L
One piece of bus connection information 8 is simultaneously supplied to each bus selection means (#1). In contrast, bus connection information 1
The response signal 9 indicating whether or not 18 is normally supplied is 4.
The data is configured to be sent back to the host 7 from only one of the L bus selection means -1 (#1) to 4-L (#1).

Specifically, the L bus selection means 4-1 (#1) to 4-L (#1) each select the #1 input signal from the M input signal buses 5, for example, #1 to #M. A selector that connects any one of the M signal lines 5-1 of ~#M to the signal line 6-1 (#1) of the output signal bus 6 of #1, and a host 7
a selector control means that receives bus connection information 8 supplied from the bus connection information 8 and changes the connection state of the selector based on the bus connection information 8; I! and a response suppression control means for controlling whether or not to output a response signal 9 indicating whether or not reception of 8 has been successfully completed to the host 7.

The configuration of FIG. 1(b) above and its specific example are #2 to #N
bus selection means 4-1 connected to each output signal bus 6 of
(#2) ~4-L (#2) ,...,4-1 (
The same applies to #N) to 4-L (#N).

However, host 7 has only one bus selection method for all bus selection means.
The bus selection means 4-1 to 4-L of #1 to #N may be connected by a common bus, and which one of them should be provided.
Whether to send out the bus connection information 8 individually may be selected, for example, using an address signal line (not shown) or the like.

[For production]

In each of the above means, for example, the #1 input signal bus 5 is
If you want to connect to the #2 output signal bus 6, L bus selection means 4- connected to the #2 output signal bus 6.
1 (#2) to 4-L (#2), the host 7 outputs bus connection information 8 to select the input signal bus 5 of #1 (see FIG. 1 (bl)).

By performing such control for each of the output signal buses 6 #1 to #N, the connection state of the entire network can be determined. For example, #N output signal bus 6
If you want to change the connection state to the bus selection means 4-
It is only necessary to change the connection states of 1 (#N) to 4-L (#N), and there is no need to change the connection states of other bus selection means. In this way, the connection state of the entire network can be determined with simple control.

Also, for example, bus selection means 4-1 (#2) to 4-L
When outputting bus connection information 8 to the effect that input signal bus 5 of #l is selected from host 7 to (#2), only one bus connection information 8 is output from host 7, and each of the above bus selection means For example, since the bus connection information 8 is set in the selector control means at the same time, the host 7 does not need to control each bus selection means. As a result, each of the bus selection means 4-1 (#2) to 4-L (#2)
The selector means, for example, selects each signal line 5-1 (#1) to 5-L (#1) of the input signal bus 5, for example, #1.
1).

In the above case, the response signal 9 indicating whether or not the bus connection information 8 was received normally is 4-1 (#2) to 4-L (
#2) If all bus selection means output,
A collision of signals occurs and the host 7 is unable to perform normal control. Therefore, in each bus selection means, the response signal 9 is outputted in advance to the response suppression control means in the bus selection means, for example, only to one bus selection means, for example, the bus selection means 4-1 (#2). Configure the other 4
-2 (#2) to 4-L (#2) bus selection means should be set in advance so as not to output the response signal 9 to the response suppression control means in each means. This allows only one response signal 9 to be output. In addition, during a test or the like, if settings are made such that each bus selection means outputs a response signal 9 to, for example, the response suppression control means in each bus selection means, each bus selection means receives the bus connection information 8 from the host 7. It is possible to perform tests to determine whether or not the information is being received normally.

On the other hand, if the host 7 wants to know, for example, the current connection state to the #2 output signal bus 6, select one of the #2 bus selection means 4-1 to 4-L via a bus (not shown) or the like. By reading out the set bus connection information 8 from one of the two, the connection state can be easily known.

Here, in the configuration as shown in FIG. 1 (8), #1 to
Since it is only necessary to provide L bus selection means 4-1 to 4-L for each output signal bus 6 of #N, the total number of switches can be reduced, and the circuit configuration can be simplified. Since it has a simple configuration centered on wiring, it is easy to integrate circuits and the scale of the device can be reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

FIG. 2 is a configuration diagram of an embodiment of the present invention, and #00 to #
47 (not particularly shown), which are connected to 48 image processing basic calculation modules, which are connected to 12-bit wide image input buses 25 from #OO to #47, and image output buses 26 from #00 to #47. It is a 48 x 48 network control device.

In FIG. 2, #0 is input from 48 12-bit wide image input buses 25, #00 to #47, through 48 image interface groups 11, #OO to #47.
48 types of 12-bit width images from 0 to #47 1
5 are grouped into 12 types of image input groups 17 (bits 1 to 12) of 48 inputs for each bit.

These 12 types of image input groups 17 (bits 1 to 12) are divided into 12 sets corresponding to bits 1 to 12, and are input to 48 sets of select circuits 10, #00 to #47. do.

The above 48 sets of select circuits #00 to #47 1° Karaha, 48 types of 12 focus width image outputs 16 of #00 to #47 are output, and the 48 image bus interface units 11 of #00 to #47 The image data is outputted to 48 image output buses 26 #00 to #47 via.

Input/output to each image input bus 25 and image output bus 26 from #00 to #47 is performed by each image bus interface unit 11 from #00 to #47 using a clock driver 1.
This is done synchronously by operating under a common clock CLK via 2.

On the other hand, MPU data 21 input from a host (MPU, the same applies hereinafter), not shown, to the MPU bus interface unit 13 and an R/W signal 18 instructing reading or writing of the data are transmitted to each select circuit 10 (# 0
0. Bit 1~12°..., #47. Bit 1~
12). Also, from each select circuit
PU data 21 may also be output. Conversely, the ACK signal 19 from each select circuit 10 is outputted to the MPU (not particularly shown) via the MPU bus interface section 13. Further, the address 20 inputted from the MPU to the MPU bus interface section 13 is input to the decode ROM 14.
The signals are decoded and output as a mode signal group 23, and are given as mode signals 22 #OO to #47 to 48 sets of select circuits 10, 12 each of #00 to #47.

In addition, an inactive bus response suppression signal 24 is input to the select circuit 10 corresponding to bit 1 of #00 to #47, and an active bus response inhibit signal 24 is input to the select circuit lO corresponding to the other bits 2 to 2. A bus response suppression signal 24 is input.

Next, FIG. 3 shows each of the 48 sets of select circuits 10 in FIG.
FIG. #00~#47 Image human power 15
A group of 48 image inputs 17 containing any of the bits shown in FIG.

M! ” The MPU data 21 from the U bus interface unit 13 (FIG. 2) is set in the register 27.
This content is decoded by the decoder 30, and the selector 31
control the connection state of Also, through the gate 28, the MP
MPU bus interface unit 13 as U data 21
(FIG. 2) is output to the MPU, which is not specifically shown.

R/ from the MPU bus interface section 13 (Fig. 2)
W signal 18, mode signal 22 and bus response inhibition signal 24
is input to the mode select circuit 26. An ACK signal 19 is output from the mode select circuit 26 via a gate 29.
is outputted from the MPU bus interface unit 13 (FIG. 2) to the MPU (not specifically shown). Further, the mode select circuit 26 controls the gates 1-28 and 29. Note that the mode signal 22 consists of two signals, chip select #1 and chip select #2.

The operation of the embodiment shown in FIGS. 2 and 3 will be described above, focusing on the operation for configuring the network.

The network setting means that 48 sets of select circuits 10, 12 each of #OO to #47, are connected to the corresponding ones of #00 to #47.
For each of the 48 image outputs 16 of #47, #00 to #4
This refers to the operation of deciding which of the 7 image human forces 15 to connect. This operation is performed by the MPU (not shown) setting MPU data 21 in each select circuit 10 via the MPU bus interface section 13.

In this case, as a feature of this embodiment, the MPLJ data 21
The settings can be made simultaneously for any 1Mi of 12 select circuits 10 among #00 to #47.

Now, an example will be explained in which a setting is made to connect the image output 16 of #OO to the image output 25 of #47.

First, by outputting address 20 from MPLJ (not shown), chip select #1 (see FIG. 3) of mode signal #00 in mode signal group 23 output from decode ROM 14 is activated. As a result, 1 corresponding to bits 1 to 12 of #00
Each mode select circuit 26 in the two select circuits 10
(FIG. 3) makes it possible to input and output the MPU data 21 to and from each register 27. In this state, the R/W signal 18 indicating writing and MPtJ data 21 are output from the MPU (not shown), so that each mode select circuit 26 (FIG. 3) sets each register 27 in a writable state, The same MPU data 21 is 12
are simultaneously written to each register 27 in the select circuits 10.

By the above operation, each decoder 30 (
3) decodes the contents of the MPU data 21 set in each register 27, and selects #4 from each image input group 17 of bits 1 to 12 to each selector 31.
The signal of each bit for the image input 15 of 7 is selected. As a result, the above 12 select circuits 10 are
#47 image human power 15 #OO image output 16
works to connect to.

In the above case, when the MPU data 21 is normally received in each register 27 (FIG. 3) in the 12 select circuits 10, each mode select circuit 26 detects it and outputs an ACK signal 19. However, if the 12 ACK signals 19 are output from the 12 select circuits 10 at the same time, a signal collision occurs, and the MPU bus interface unit 13 (FIG. 2)
Since the ACK signal 19 output to is no longer a normal signal, the MPU will not be able to perform correct signal control. Therefore, in this embodiment, among the twelve select circuits 10, only the select circuit 10 corresponding to bit 1 of #OO operates so that the ACK signal 19 is output.

In order to realize the above operation, first, when the address 20 is output, the chip select #1 of the mode signal 22 is activated, and the address is set so that the chip select #2 (see FIG. 3) is also activated. 20 designations are made. When CH knob select #2 is active, the mode is called bus response suppression mode, and #00's 1
Each mode select circuit 2 in each of the two select circuits 10
6 (FIG. 3) is in a mode in which the bus response inhibit signal 24 is accepted.

As described above, the inactive bus response inhibition signal 24 is input to the mode select circuit 26 of the select circuit 10 corresponding to bit 1 of #00.
Select circuit 1 corresponding to bits 2 to 12 of OO
Conversely, an active bus response inhibit signal 24 is input to each mode select circuit 26 of 0.

As a result, the mode select circuit 26 of the select circuit 10 corresponding to bit l of #OO selects the gate 28.29 (
(Fig. 3) is turned on, and each mode select circuit 26 of the select circuit 10 corresponding to bits 2 to 12 of #00 is turned on.
turns off gates 28,29. Therefore, the ACK signal 19 is output only from the select circuit 10 corresponding to bit 1 of #00, and the ACK signal 19 is not output from each select circuit 10 corresponding to bits 2 to 12.

On the other hand, if the MPU (not shown) wants to check the connection state to the image output 16 of #00,
R/W signal 1 which activates both chip selects #1 and #2 of mode signal 22 and instructs readout.
Give 8. As a result, bit 1 to bit 1 of #00
Each mode select circuit 26 of each select circuit 10 of 2
(FIG. 3) instructs each register 27 to output the MPU data 21 set therein.

However, as described above, the gate 28 of the select circuit 10 corresponding to bit 1 is on, but each gate 28 of each select circuit 10 corresponding to bits 2 to 12 is off.

Therefore, the select circuit 10 corresponding to bit 1 of #00
Since the MPLI data 21 is read only from the MPLI data 21, the same MP
It is possible to avoid wasteful reading of the U data 21 and the resulting collision of signals. The MPU data 21 read in this way causes the MPU (not shown) to
can easily know the connection state of #00 to the image output 16.

Incidentally, during a test or the like, the mode signal 22 of #00 is used to activate chip select #1 and to inactivate chip select #2. When chip select #2 is inactive, the mode is called normal mode, and each mode select circuit 26 (FIG. 3) in the 12 select circuits 10 of #OO does not accept the bus response suppression signal 24. mode. As a result, each mode select circuit 26 turns on each game (28, 29) so that all 12 of them can output the ACK signal 19, and each register 27 can output the MPU data 21. Therefore, it becomes possible to test each of the 12 select circuits 10 individually.

In this case, control is performed by means not particularly shown so that only one of the twelve select circuits 10 can be operated.

By performing the same operation as the operation for the 12 select circuits 10 of #00 shown above for 48 sets of select circuits 10 of 12 each of #00 to #47, network settings for all image outputs 16 can be made.

In the embodiments of FIGS. 2 and 3, the image human power 15
As can be seen from the fact that the number of losses for image output 16 and image output 16 are both 48, it is not necessary to set the number to a power of 2, and there is no limit. Further, the output of the image input 25 and the image output 26 do not have to be the same, allowing a large degree of freedom, and furthermore, the bus width is not limited to 12 bits.

Note that this embodiment can also be applied to processes other than image processing.

Furthermore, since this embodiment has a regular circuit configuration and a small number of select circuits, it is easy to integrate and the scale of the device can be made smaller than before.

〔Effect of the invention〕

According to the present invention, the simple circuit configuration facilitates integration, and the scale of the device can be reduced.

Furthermore, since the connection state of the bus selection means (select circuit) corresponding to each output signal bus directly indicates the connection relationship between nodes, network settings and confirmation can be easily performed without requiring any special algorithm.

Also, each signal (bit) connected to a certain output signal bus
Connection control of a plurality of line pair window bus selection means can be performed simultaneously regardless of the number of signal lines, thereby simplifying and speeding up the control.

Furthermore, since there is no limit to the number of nodes to which the input signal bus and output signal bus are connected, a network with a large degree of freedom can be constructed.

[Brief explanation of the drawing]

FIG. 1 (at, (bl is a block diagram of the present invention,
Figure 3 is a configuration diagram of an embodiment of the present invention, Figure 3 is a configuration diagram of a select circuit, Figure 4 is a configuration diagram of a conventional example, and Figure 5 (al to +d) is a connection state diagram of switches. be. 4-1 to 4-L... bus selection means, 5... input signal bus, 6... output signal bus, 7... host, 8... bus connection information, 9... response signal . Patent applicant Fujitsu Limited

Claims (1)

[Claims] 1) Regarding the signal bus consisting of the first plurality (L) of signal lines, any one of the second plurality (M) of input signal buses (5)
a first plurality (L) of bus selection means (4) for individually connecting one signal line to the output signal bus (6) for each signal line;
-1 to 4-L) to a third plurality (N) of output signal buses (
6) A network control device comprising a network control device corresponding to each of the above. 2) Each of the first plurality (L) bus selection means (4-1 to 4-L) provided for each of the output signal buses (6) connects which of the input signal buses (5). is controlled by bus connection information (8) supplied from an external host (7), and the host (7)
) simultaneously supplying one piece of the bus connection information (8) to the bus selection means (4-1 to 4-L), and a response signal indicating whether or not the bus connection information (8) has been normally supplied. (9) The host (7) is selected only from one of the first plurality (L) of bus selection means (4-1 to 4-L).
) of the first plurality (L) of bus selection means (4-1 to 4-L) corresponding to each signal line of a desired output signal bus among the output signal buses (6). 2. The network control device according to claim 1, wherein the network control device simultaneously performs connection control for the following. 3) Each of the bus selection means (4-1 to 4-L) selects a second plurality of (
a selector for connecting any one of the signal lines of the output signal bus (6) to one of the signal lines of the output signal bus (6) to which the bus selection means is connected; selector control means for receiving the bus connection information (8) and changing the connection state of the selector based on the bus connection information; and determining whether or not the selector control means has successfully completed reception of the bus connection information (8). response suppression control means for controlling whether or not to output a response signal (9) indicating to the host (7); ) bus selection means (4-1 to 4-L)
Only the response suppression control means of one bus selection means outputs the response signal to the host (7), and the response suppression control means of the other bus selection means outputs the response signal (9) to the host (7). 3. The network control device according to claim 2, wherein the network control device performs control so as not to output to the network. 4) The second plurality (M) and the third plurality (N) are the same number, and each of the input signal buses (5) and each of the output signal buses (6)
) is connected one by one to the second plurality (M or N) of image processing basic calculation modules provided at each node of the network, which is the pipeline connection structure of the pipeline image processing system. Claim 1
, 2, or 3. The network control device according to .