JPH01256221A - Gate array integrated circuit - Google Patents

Abstract

PURPOSE:To fix the logic value of an input terminal not in use without using a wiring area and a cell by connecting the input terminal not in use among input terminals to an emitter (source) of a transistor(TR) element. CONSTITUTION:The base and emitter of a TR2 are connected by a wire 1 by fixing a logic value of the input terminal 1 not in use to level '1'. Thus, the level of the input terminal 11 is always logical '1'. That is, since the logic value of the input terminal not in use is fixed by using only a wire of a short- distance as the connection of the base and emitter of the TR, it is not required to use the wire area or the other cell for the constitution of the circuit. Thus, the chip size is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate array integrated circuit, and more particularly to a gate array integrated circuit in which the bases (gates) of a plurality of transistor elements serve as input terminals.

In general, gate array integrated circuits have two methods: one in which the basic gate is placed on the entire surface of the chip, and the other in which the basic gate is placed on the entire surface of the chip. There is a method of designing using function blocks.

In a logic circuit constructed using such a gate array integrated circuit, it is necessary to fix unused input terminals to a logical value of "1" or "0".

Therefore, in the conventional gate array integrated circuit, a circuit that fixedly outputs the logic gate 8'IJ or "0" is configured with cells, and the output is distributed to each unused input terminal. A conventional example thereof will be explained using FIG. 2. In the figure, a function block 10 is a well-known AND/NAND circuit (negative logic) constructed using cells of a gate array, and has three inputs 41, 11, 12 and 13,
It is configured to include an AND output terminal -21 and a NAND output terminal 22, and the terminal VR has a reference voltage and the terminal VE[
A negative voltage is applied to each.

Now, input terminal 1 in function block 10
1 is an unused terminal. Therefore, this input terminal 11
must be fixed to the logical value "1" 6 Therefore, a function bronch 20 is provided and its output! ? −
Input the output of 14 M4! -i' 11, the logical value r1. It is fixed at .

However, in this case, there is a drawback that the area used for the wiring area increases and the chip size increases. Another drawback is that current always flows in the function block that outputs a fixed logical value of "1" or "0".

An object of the present invention is to provide a gate array integrated circuit that can fix the logic values of unused input terminals without using wiring areas or cells.

Structure of the Invention The gate array integrated circuit of the present invention has a plurality of transistor elements, and uses the bases (gates) of these transistor elements as input terminals, wherein an unused input terminal among the input terminals is a gate array integrated circuit. The device is characterized in that the terminal is connected to the emitter (source) of the transistor element.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a gate array integrated circuit according to the present invention. Parts equivalent to those in FIG. 2 are indicated by the same reference numerals. In FIG. The base and emitter of the transistor 2 are connected by a wiring 1 in order to fix the voltage. As a result, the input terminal 11 always has a logical value of "1".

In other words, in this embodiment, it is possible to fix the logical value of an unused input terminal by simply connecting the base and emitter of the transistor with the shortest wiring distance. There is no need to construct a circuit using .Therefore, the chip size can be reduced.

Although the above is a case of a bipolar type gate array integrated circuit, it is possible to similarly fix the logic value of an unused input terminal in the case of a MOS type gate array integrated circuit. The embodiment will be explained using FIG. 3 and FIG. 4.

In FIG. 3, the function block 10 is a circuit in which a well-known NAND circuit is constructed using a MOS type gate array. In this case, by providing the wiring 1 between the gate and source of the P-channel transistor 3, the input terminal 11 can always be fixed at the logical value "1".

In FIG. 4, a function block 10 is a circuit in which a well-known NOR circuit is constructed using a MOS type gate array. In this case, by providing the wiring 1 between the gate and source of the N-channel transistor 4, the input terminal 15 is always connected to the logic Ii! It can be fixed to "0".

As described above, the present invention connects the base and emitter of a transistor element in a gate array 4Jc product circuit in the case of a bipolar type, and connects the source and gate in the case of a unipolar type charge effect transistor. All that is required is to turn off the transistor element.

As explained above, according to the present invention, the logical values of unused input terminals can be fixed without using the wiring area, so the size of the chip metal body can be reduced. There is an effect.

Further, according to the present invention, there is no need to configure a funxing block for fixing the logic value of an unused input terminal using cells, so there is an effect that current consumption can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a gate array integrated circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional gate array integrated circuit, and FIGS. 3 and 4 are MOS type gates according to an embodiment of the present invention. FIG. 2 is a circuit diagram of an array integrated circuit. Explanation of symbols of main parts 1... Wiring 2... Transistor 3... MOS type l-transistor <1) Channel type) ・1... MO3 type Transistor (N channel type)

Claims (1)

[Claims] (1) A gate array integrated circuit that has a plurality of transistor elements and uses the bases (gates) of these transistor elements as input terminals, wherein unused input terminals among the input terminals are connected to the emitters (sources) of the transistor elements. ) A gate array integrated circuit characterized in that it is connected to.