JPH01253376A - Time base correction device - Google Patents

Abstract

PURPOSE:To make a operating point setting circuit and its adjusting works unnecessary by providing a reference generating circuit which generates triangle waves according to reference signals and two phase comparators and automatically setting the operating points of a CCD and VCO by using the differential output of the 1st and 2nd phase comparators so as to eliminate the necessity of adjustment. CONSTITUTION:A reference generating circuit 19 generates triangle waves to be used for converting the phase variation produced by the output signal of a reference oscillator 10 into a voltage in the cycle of reference synchronizing signals. Sample hold circuits 22 and 23 respectively sample and hold the output of the same reference generating circuit. A differential circuit 24 detects the difference in the outputs of the sample hold circuits 22 and 23 and adds and synthesizes the output difference to and with the output of the sample hold circuit 22 for output signal of a CCD through a low-pass filter 25 and adder circuit 26. When the supply of the synthesized signal to a VCO 13 is started through a phase compensation filter 11 and switch 12, the oscillation frequency of the VCO is automatically changed so that an original delayed time quantity can be set by the time constant of an operating point automatically setting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a time axis correction device (hereinafter abbreviated as jitter) that uses a variable delay element such as a COD to correct time axis fluctuations (hereinafter abbreviated as jitter) of a video signal including a synchronization signal. (hereinafter abbreviated as TBC).

BACKGROUND OF THE INVENTION In recent years, many devices such as VTRs and video discs that record and reproduce video and audio signals on tape or disk-shaped media have been proposed. The jitter due to CCD (Charg
TBCs that use variable delay elements such as e-cuplad devices and memories to provide images with extremely little screen shake are attracting attention.

An example of the TBC described above will be described below with reference to the drawings.

Figure 6 shows a TB for video discs, etc. using conventional COD.
This shows an example of the configuration of C.

1 is a disk, and 2 is a medium for recording or reproducing information signals including synchronization signals such as video signals.
Rotation is controlled with high precision by a disc motor. Reference numeral 3 is a pickup device, which also has the function of detecting a signal recorded on a disk, and in the case of a recording/reproducing device, recording an input signal of the device on a disk. Reference numeral 4 denotes an amplifier means, which constitutes a circuit for amplifying the detection signal, which is a very small signal, with a good S/N ratio. 5 is a demodulation circuit and FM
It has the function of returning a signal recorded using a modulation method such as to the signal form before recording.

Depending on the modulation method, the demodulation circuit uses NTSC or PAL, which combines a luminance signal and a color signal (chroma signal), in the case of a video signal.
, FM (die reflex) FM system that directly records and reproduces synthesis formats such as SECAM, etc., and low-frequency conversion systems (VTR, etc.) that records color signals shifted from their original frequency band and electrically removes jitter from the color signals during playback and synthesis. ), Perirad chroma method, line sequential method, etc., but since the basic configuration of all the methods can be handled in common, the details will not be explained here.

6 is a variable delay element COD, which has the function of connecting hundreds of capacitive elements in series and sequentially transmitting analog signal information to subsequent elements, and is a voltage-controlled oscillator (VCO).
) is an element that can vary the amount of delay by changing the output frequency of 13. Such a function can also be realized by a D/A converter or a memory-to-memory controller.

The end is filtered by a low-pass filter, and the VCC of the ccDs is
This is to remove the clock component by H3. Reference numeral 8 denotes a horizontal synchronization signal separation circuit, which has a function of detecting only the horizontal synchronization signal from the above-mentioned reproduced composite video signal. 9 is a phase comparator, and the output of the reference oscillator 10;
This detects a voltage corresponding to the phase difference between the outputs of the horizontal synchronization signal separation circuit described above. This output is supplied to the next-stage phase compensation filter 11, and is also supplied to the control circuit of the disk motor 2 in order to set the operating point of the phase comparator 9 as necessary, but it will not be described in detail here. do not.

Reference numeral 1o is a reference oscillator, which uses a crystal oscillator or the like to extremely accurately generate the frequency of the period that the horizontal synchronizing signal should have. In some cases, the device may have a function of switching to a horizontal synchronization signal supplied from outside the device, depending on the device's needs. 11 is a phase compensation filter, T
In order to ensure the gain and stability of the entire B Ctv-de, it is composed of a low-pass filter, distortion compensation, band-pass filter, etc. The configuration differs slightly depending on the needs of the equipment, but the gain of the fundamental wave component, which is the frequency of 10 rotations of the disk, is set sufficiently high (60 to 70 dB).
The characteristic of feedback looseness is that the gain curve near the cutoff frequency of the system is a first-order system.
There's a lot in common. Furthermore, a notch filter or the like that sharply removes the horizontal synchronizing signal frequency component, which is the phase comparison frequency, and other specific frequency components may be inserted as necessary. The output of the filter 11 is combined by an adder circuit 16 with the detection signal before being input to the CCDe.

Reference numeral 12 denotes a switch, which is controlled on/off by a microcomputer, etc., which checks the operation of the disk motor 2 and the presence or absence of a demodulated signal, and controls the entire apparatus.

13 is the aforementioned vCo, and the center frequency determined by the number of elements of the CCD 6 is inputted to the variable resistor 14 at point d.
p-, which is set by the output of the operating point setting circuit configured by the above, outputs an output frequency proportional to the control signal input to the 0 point to the e point, and controls the delay amount of the CCDa described above.
It makes up the group. Generally, the amount of delay is selected to be the period of the horizontal synchronization frequency (63.5 μB) or an integral multiple thereof, although it varies depending on the expected amount of jitter of the device.

Reference numeral 16 denotes a horizontal synchronization signal separation circuit which separates the horizontal synchronization signal before being input to the CCD 6 from the video signal, and compares the phase with the reference signal mentioned above by the phase comparator 17, and passes it through the bandpass filter 18 to the addition circuit. 16.

16 to 18, a feedforward system is purchased to compensate for the band above the cutoff frequency of the feedback loop, reduce the gain burden in the feedback loose band, and stabilize the overall loop characteristics. .

In this way, the output of the phase comparator 9 using feedback and the phase comparator 1 using feed forward
CC, which is a variable delay element,
A device for controlling De to suppress jitter in a video signal reproduced from a disc is disclosed in, for example, Japanese Patent Publication No. 60-56358.
It has been proposed in the following publications.

Problems to be Solved by the Invention However, in the above configuration, CCDe and VC
An operating point setting circuit is required to accurately set the operating point of Ol 3, which requires difficult work. Further, there is a problem in that the transfer characteristics of CCDe are likely to deteriorate due to operating point fluctuations such as temperature changes, and countermeasures such as a temperature compensation circuit are required.

Furthermore, it was necessary to provide completely independent dual phase comparison loops, a feedback system and a feedforward system, which required a complex configuration.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide an automatic operating point setting circuit that always sets a COD or VCO at an optimal operating point, and a TBC with a simple configuration and a feedforward system.

Means for Solving the Problems In order to solve the above problems, the TBC of the present invention includes a reference generation circuit that generates a triangular wave based on a reference signal, and samples and holds the output of the reference generation circuit using a synchronization signal of the input signal of the COD. It is equipped with a first phase comparator and a second phase comparator that samples and holds the output of the reference generation circuit according to the synchronization signal of the output signal of the COD, and the differential output of the first and second phase comparators allows The COD and VCO operating points are automatically set and no adjustment is required.

At the same time, the jitter of the signal passing through the COD is suppressed to an extremely small level by the differential output and the composite signal of the first or first and second phase comparator outputs.

In addition, when implementing two sets of phase comparators, by sampling and holding the same reference generator, variations in the balance between the feedback loop and feedforward loop due to variations in phase comparison sensitivity and temperature fluctuations are extremely small. It also provides an extremely simple method for constructing a double loop.

According to the present invention, with the above-described configuration, by simply selecting the delay time determined by the number of COD stages at the design stage to be the same as the period of the original synchronizing signal or an integral multiple thereof, the differential between the first and second phase comparators can be adjusted. Since the /l/- output voltage works to make the delay time determined by the operating points of the CCD and VCO the same as the period of the reference synchronization signal, the operating point setting circuit and its adjustment work that were previously required are no longer required. It is something that can be done. Furthermore, since the two sets of phase comparators are constructed by sampling and holding the same reference signal, the number of components required for constructing a conventional dual loop of feedback loop and feedforward loop is extremely high. This makes it possible to realize a highly accurate double TBC/L/-p.

EXAMPLE Hereinafter, a TBC according to an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a TBC in a first embodiment of the present invention. In addition, here, the conventional example No. 6
Each element explained in the figures is given the same number and will not be described in detail.

Reference numeral 19 denotes a reference generation circuit, which generates a triangular wave (or trapezoidal wave, etc.) generated by the output signal of the reference oscillator 1o and used to convert phase fluctuations into voltage at a reference synchronization signal period.

Reference numerals 20 and 21 are pulse generation circuits, 2o and 21 respectively pulse the output signal of the CCD 6 and the COD input signal, respectively, to pulse the horizontal synchronizing signal, and use them as signals for sampling.

Sample and hold circuits 22 and 23 sample and hold the output of the same reference generation circuit, 22 the sync signal edge of the COD output, and 23 the sync signal edge of the COD input. It consists of analog switches and voltage/current conversion circuits such as voltage followers.

24 is a differential circuit, sample and hold circuit 22.2
Detect the output difference between 3 and apply a low-pass filter (or band-pass filter, etc.) 25. Add 'JE circuit 26 to CCD
After adding and synthesizing the output signal with the output of the sample and hold circuit 22, the phase compensation filter 11 explained in FIG.
and switch 12. The signal is supplied to the CCD 6, which is a variable delay element, via the vCo 13.

Here, in the low-pass filter 26, when the TBC is operating normally, the jitter component of the output of the sample-and-hold circuit 22 is almost eliminated, whereas the jitter component of the output of the sample-and-hold circuit 23 remains as it is. Therefore, it becomes a signal that interferes with jitter compensation of the fundamental wave component, so it is necessary to realize characteristics that sufficiently suppress the fundamental wave.

The operation of the TBC configured as described above will be explained using FIG. 2.

vl is the output of the reference generation circuit, which generates a triangular wave as shown in the figure with a precise synchronization signal period.

P2 is a synchronizing signal edge separated by υ from the input signal of CCDe, and is the output of the pulse generator 21.

Also, Vs2 is the output v1 of the reference generation circuit by P2.
is the voltage sampled and held, in this case, VC
This corresponds to the bias for measuring the frequency of O13.

Pl is a synchronization signal edge separated from the output signal of CCDe, and is the output of the pulsing circuit 22.

Also, Vsl is the output v of the reference generation circuit depending on Pl.
The voltage sampled and held at 1 is the same as Vs2 mentioned above.
By comparing the voltage with the frequency of the VCO 13, a voltage proportional to the frequency of the VCO 13 can be detected.

The first half of FIG. 2 in the Tm1 region shows the general operation when the VCO frequency is a little high, and the second half in the Tm2 region shows the general operation when the vCo frequency is a little low.

Further, in order to make the explanation easier to understand, the operation of the low-pass filter 25 will be omitted and the explanation will be given using a response that is faster than the actual operation point automatic setting operation. Therefore, here, within 3 cycles (
200 μs), but in reality, an extremely low frequency response of about 1 to 10 seconds is sufficient to achieve the purpose. Furthermore, since fluctuations due to jitter are not directly related to operating point setting, the explanation will be made without including jitter components.

CCD 6 (7) The number of delay element stages is N, and the VCO13
The frequency of is F, and the delay time between input and output signals of CCDe is T
d, the following relationship holds.

Td=N/F (sea) Jitter suppression, which is the main function of TBC, is achieved by controlling the delay time Td by changing the frequency F of the VCO 13 with a polarity that suppresses time axis fluctuations of the CCDe input signal. are doing.

If we assign the corresponding numbers 81 to Ss and So'-85' to the synchronous signal engineer/Fuji pulse P2 and Pl in FIG. 2, S1→92. ......S6→S6 and Sσ→S11...34'→S15', the synchronization signal period is the same as the actual adjacent synchronization signal period, excluding the amount of jitter. (The amount of jitter between signals is extremely small) The period is kept the same as the standard synchronization signal period. However, at the beginning of the Tm1 region, S1→S1
The actual delay amount Td1 of ' is shorter than the synchronizing signal period Th by 71 minutes, indicating that the frequency of VCO13 is higher than the designed value. If this amount is small, it will have almost no effect on the TBC operation or the signal characteristics of the CCDe output, but if it becomes large, the delay operation of the CCDe itself will become unstable, causing the TBC to malfunction or the output Since this is accompanied by significant signal deterioration, the conventional operating point setting circuit 14 and the like are required.

v2 is a signal for automatic operating point setting, which is a feature of the present invention, and is a differential output of the aforementioned V s 2 and Vsl. T
At the beginning of the m1 region, an error voltage called vdl corresponding to the high VCO frequency is generated, but Vd1 is synthesized with the output of the sample-and-hold circuit 22, which is the main signal of the TBC, in the adder circuit 26, and the phase compensation filter 11.
Once it starts being supplied to VCOl 3 via switch 12,
The oscillation frequency of the VCO is automatically changed to match the original delay time by the time constant of the automatic operating point setting circuit, and ΔT1. Only a residual error of ΔVd1 remains.

It operates similarly in the T m 2 region, and S4→S4
Ta2 between ' is 72 minutes longer than the design value because the oscillation frequency of vCo13 is low, but at S6, Δ
T2. Only a residual error of Δvd2 remains.

As described above, according to this embodiment, the first phase comparator samples and holds the output of the reference generation circuit according to the synchronization signal of the input signal of the COD.

a second phase comparator that samples and holds the output of the reference generation circuit according to the synchronization signal of the output signal of the COD;
, the operating point of the VCO is automatically set and no adjustment is required, and the jitter of the signal passing through the COD is reduced to an extremely small level by the composite signal of the differential output and the first or first and second phase comparator outputs. A time axis correction device (T
BC), very good delay operation is achieved.

The COD transfer characteristics and TBC operation can be realized even when the ambient environment such as temperature changes. Furthermore, the design of 700 parts can also be simplified because temperature compensation and the like are not required.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of a TBC showing a second embodiment of the present invention.

In the same figure, 27 is a band pass filter, C
The output of the sample hold circuit 23 based on the synchronization signal edge of the input signal of CDa is inputted and outputted to the adder circuit 2e. The other components in FIG. 3 are exactly the same as in FIG. 1, and by using the output of the sample and hold circuit for the input signal of the CCD 6, which constitutes the automatic operating point setting circuit, By simply adding a simple filter, it is possible to reduce the burden of feedback loops and construct a feedforward loop capable of high-speed response.

Next, a third embodiment in which the configuration is further simplified will be described using FIG. 4.

Reference numeral 28 denotes a phase compensation filter, which plays a role equivalent to the filter 11 in FIGS. 1 and 3, but requires some changes in components such as impedance conversion. Reference numeral 29 denotes a low-pass filter, which corresponds to the filter 25 described above, but similarly requires some modification.

In this way, by inserting a filter that satisfies the required characteristics for each input signal of the differential circuit, it is possible to construct a TBC that combines a vCO operating point automatic setting circuit and a feedforward loop with a simpler configuration. It is something that can be done.

Figure 5 is an application example of the embodiment of 1.2.3, which is effective when the delay time is set to more than twice the synchronization signal period mentioned above due to a large number of shifters or for other reasons. This is the method.

30 is the second COD, and in FIG.
Although it is inserted before the , the reverse case can be handled in the same way. In this way, by connecting the CCDs 30 in series, the delay time can be increased, but since each CCD 30 is accompanied by some signal deterioration, generally two CCDs 30 are connected in series.
~3rd stage.

Reference numeral 31 is a low filter having characteristics similar to those of filter 7. Reference numeral 32 denotes a synchronizing signal separation circuit that separates the synchronizing signal from the output signal of the second CCD 30. The synchronizing signal is supplied as a sampling pulse to the sampling circuit 34 via a pulse generator 33. 36 is a differential circuit, which is similar to 24 in FIG. 36
In this case, unlike in FIG. 1, the wrinkle component is suppressed to a sufficiently small level by the 2000Dso, so noise suppression is sufficient.

37 is an adder circuit, and C for suppressing jitter mentioned above.
Sample and hold circuit 23 using a synchronization signal that does not pass through OD. It is added and synthesized with the feedforward system signal that has passed through the bandpass filter 27, and is added to the phase compensation circuit 11. It is configured to control the VCO 13 via the switch 12.

With this configuration, there is no need to consider the fundamental wave suppression gain of the low-pass filter in FIG. 1, so the gain of the automatic operating point setting circuit described above can be further increased, and the delay time at each COD The second CO
Since it is possible to treat the D output as a 1H delay line, it is possible to have a new function that can sufficiently compensate for the drawbacks of the increased number of circuit elements compared to the one shown in FIG.

In the embodiment, the reference signal was supplied as a triangular wave to the sample and hold circuit, but it is also possible to use the above-mentioned regenerated synchronization signal. This can be realized by changing the input polarity of each differential circuit, the polarity of the addition/synthesis circuit, etc.

In addition, although the phase comparison means is explained as a sample-hold method, although this includes a proposal for simplifying the configuration of the detection stage, it is a consideration to reduce malfunctions due to noise in the reproduced signal, and the phase comparison means is a sample-hold method. The types are not limited to these.

Furthermore, although the embodiments have been described using a synchronization signal of a video signal, the present invention has a synchronization signal with a constant period, and controls the COD and other delay elements using the synchronization signal to correct jitter of the signal. It can be applied to all devices.

Effects of the Invention As described above, according to the present invention, the first phase comparator that compares the phase of the reference signal and the synchronization signal of the input signal of the variable delay element dedicated to CCI, and the Equipped with a second phase comparator that compares the phases of the synchronization signal and the reference signal, the differential output of the first and second phase comparators automatically sets the operating points of the COD and VCO, eliminating the need for adjustment. By using the differential output and the composite signal of the first or first and second phase comparator outputs, it is possible to suppress the jitter of the signal passing through the variable delay element to an extremely small level.

In addition, when implementing two sets of phase comparators, by sampling and holding the same reference generator, fluctuations in the balance between the feedback loop and feedforward μm loop due to variations in phase comparison sensitivity and temperature fluctuations are extremely minimized. , and can realize a double loop with an extremely power-saving configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a time axis correction device according to a first embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the same embodiment, and FIG. 3 is a diagram showing a second embodiment of the present invention. FIG. 4 is a block diagram showing a time axis correction device according to a third embodiment of the present invention, and FIG. 6 is a block diagram showing a time axis correction device according to a fourth embodiment of the present invention. FIG. 6 is a block diagram showing a conventional time axis correction device. 1...disc, 2...disc motor, 3...pickup, 4...RF
Amplifier, 5... Demodulation circuit 16930...
CCD17...Low pass filter, 8,16
, 32... Synchronization signal separation circuit, 9.17...
... Phase comparator, 10 ... Reference generator, 11
．． 28... Phase compensation filter, 12...
...Switch, 13...VCO114...
...Operating point setting circuit, 15,26.37...Additional circuit, 18.27...Band pass filter, 19...Triangular wave generation circuit, 20,21, 33
...Pulsing circuit, 22゜23.34...
...Sample hold circuit, 24°35...Differential circuit, 25,29,36...Low pass filter. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
VSz〉 ＜VSt＞

Claims (3)

[Claims] (1) A variable delay element that delays a signal such as a video signal including a synchronization signal, a delay amount control means such as a voltage controlled oscillator (VCO) that controls the delay amount of the variable delay element, and a period of the synchronization signal. a reference generator that generates a frequency with an originally desired period; a first synchronization separation circuit that separates a synchronization signal from the input signal of the variable delay element; and a second synchronization separation circuit that separates the synchronization signal from the output signal of the variable delay element. a synchronous separator circuit, a reference waveform generator that generates a triangular wave or the like for converting time fluctuation into voltage using the output of the reference generator, and pulses the outputs of the first and second synchronous separator circuits, respectively. first and second pulse generation circuits, first and second sample and hold circuits that sample and hold the output of the same reference generator in the first and second pulse generators, respectively; a differential circuit that takes the difference between the outputs of the sample and hold circuits, and supplies the output of the differential circuit through a first filter to a synthesis circuit that adds and synthesizes the output of the second sample and hold circuit; A time axis correction device characterized in that the output of the synthesis circuit is input to the delay amount control means through a second filter. (2) The time axis correction device according to claim (1), wherein the output of the first sample and hold circuit is added and synthesized by a synthesis circuit through a third filter. (3) a third synchronous separation circuit that connects a second variable delay element in series with the variable delay element and separates a synchronous signal from the output signal of the second variable delay element; a third pulsing circuit that pulses the output; and a third sample and hold circuit that samples and holds the output of the reference generator at the output of the third pulsing circuit; The delay amount control means is controlled by a composite signal of the output of the second differential circuit that takes the difference between the hold circuit outputs and the output of at least one of the first, second, and third sample and hold circuits. The time axis correction device according to claim (1).