JPH0578993B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a magnetic recording/reproducing device (hereinafter referred to as
The present invention relates to VTRs (abbreviated as VTRs), and in particular to recording and reproducing circuits for after-recording PCM audio signals.

[Background of the invention]

For example, in a helical scan type VTR that records a video signal and a PCM audio signal (hereinafter abbreviated as PCM audio signal) in an overlapping manner, a method for after-recording the PCM audio signal (hereinafter abbreviated as PCM post-recording) was developed in Japanese Patent Laid-Open No. 57. −
As shown in Japanese Patent No. 190476, a method is known in which a PCM audio signal is recorded while reproducing video on a monitor.

In this known example, during the overlap period, the high-level recorded signal affects the reproduced signal, causing the reproduced signal to become abnormal, and as a result, the reproduced image during this period becomes distorted. By replacing the normal reproduction signal with another normal video signal, disturbances occurring in the reproduced image are prevented.

However, this known example does not mention that when a color video signal is recorded and reproduced, the operation of the chroma reproduction system is disturbed during the overlap period, and as a result, no color is applied to the entire reproduction screen at all times. In other words, the abnormal reproduction signal greatly disturbs the oscillation frequency and phase of the conversion carrier generation oscillator in the chroma reproduction system.
The color killer circuit installed on the VTR side or TV side operates and the color fades out, but if the oscillator is greatly disturbed, it will take at least several fields to recover to the normal state. Since this is repeated every field, the faded state ends up continuing.

[Purpose of the invention]

The purpose of the present invention is to ensure the performance of normal recording characteristics and playback characteristics, to ensure playback image quality during PCM dubbing, and to ensure sound quality of PCM audio played back after after-recording, and to ensure high quality monitor images during dubbing. An object of the present invention is to provide a magnetic recording/reproducing device obtained by the present invention.

[Summary of the invention]

That is, the present invention alternately switches between recording and reproduction.
An oscillation means for generating a conversion carrier for converting the frequency of reproduced color information (reduced carrier color signal) in order to minimize interference from the recording side to the reproduction side during PCM dubbing, and a reproduction signal and the oscillation means. The chroma reproduction system includes a control means for controlling the oscillation operation of the oscillation means by comparing the output signal with the output signal of the oscillation means, and one of the two rotating magnetic heads is in the reproduction state and the other is in the recording state. By providing prohibition means for prohibiting the control means from controlling the oscillation means during the period, abnormal fluctuations in the frequency of the reproduced chroma signal other than the PCM signal period are prevented.

[Embodiments of the invention]

First, in explaining the embodiments of the present invention, the above-mentioned PCM dubbing will be explained. FIG. 1 shows a track pattern on a magnetic tape, where 1 is the magnetic tape, 2 and 3 are tracks, 4 is the traveling direction of the magnetic heads 6 and 7, and 5 is the traveling direction of the magnetic tape. Adopts overlap recording method
In a VTR, the magnetic tape is rotated by a cylinder (not shown).
Since the wire is wrapped more than 180 degrees, an overlapping area is created as shown by the diagonal lines in Figure 1. Figure 1 shows the track pattern when a magnetic tape is wrapped 210 degrees around a rotating cylinder. Video signals are recorded in the white area, and time axis compressed signals are recorded in the shaded area, for example. It is possible to record PCM audio. As shown in the figure, there is a period in which the two magnetic heads 6 and 7 mounted on the rotary cylinder are located on the magnetic tape 1 at the same time (hereinafter abbreviated as the overlap period), so the video signal and
It is possible to simultaneously record and reproduce PCM audio signals simultaneously, and furthermore, it is possible to perform an after-sales operation in which, for example, the magnetic head 6 plays back the video signal on track 2, and the magnetic head 7 records the PCM audio signal on track 3. Recording is possible.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3. Figure 2 shows a recording and reproducing circuit that realizes PCM dubbing, with adders 11 and 12;
13, 18, 19, 20, 25 are switches, 14
is buffer amplifier, 17 is recording amplifier, 23,2
6 is an inverter, 21 is a rotary transformer, 22
is a magnetic head, 24 is a reproduction head preamplifier, 2
8 is a tracking servo circuit that controls the capstan motor 32 based on the pilot signal; 55 is a drum servo circuit that controls the rotation of the rotary head;
56 is a drum motor, 40 and 41 are audio input terminals, 33 and 36 are audio output terminals, 39 is a video signal input terminal, 34 is a video signal output terminal, 60 is a luminance signal recording circuit, 61 is a chroma signal recording processing circuit,
40 is an audio FM signal recording processing circuit, 57 is a pilot signal generation circuit, 59 is a chroma signal, audio FM
Signal, pilot signal recording level adjustment circuit, 5
1 is an audio FM signal reproduction processing circuit, 52 is a luminance signal recording processing circuit, 53 is a chroma signal reproduction processing circuit,
54 is a luminance signal and chroma signal addition circuit; 35 is an addition circuit for luminance signal and chroma signal;
PCM audio processing circuit, 37 is logic circuit, 38
is the system control circuit.

First, the flow of signals during recording will be explained.

The signal passing through the switch 13a is amplified by a buffer amplifier 14a and input to a recording amplifier 17a. The output of 17a removes the DC component by capacitor _C1 , passes through switch 18a, and then is transferred to capacitor _C2 , rotary transformer 21a, and switch 19.
It flows into the earth through a. At this time, the current _i1 flowing to the stator side of the rotary transformer 21a is transmitted to the magnetic head via the rotary transformer, and the recording operation is completed. Here, the capacitor _C2 functions to cut off the DC component generated there when 18a is configured as an electronic switch, and to prevent DC current from flowing through the magnetic head. During recording, the switches 18a,
19a is conductive, and switch 20a is disconnected. Generally, the optimum recording current to be passed through the magnetic head is approximately 20 to 3 mA for current home VTRs, and the recording amplifier 17a is required to have a sufficiently large drive capacity.

Below, the PCM audio signal, pilot signal, chroma signal, FM audio signal, and FM brightness signal are respectively A _POM ,
Let P, C, A _FM and Y _FM . The switch 13a is
Output of adder 11 (A _PCM P) and adder 12
The output (Y _FM CPA _FM ) is sent to the magnetic head 22.
It has the function of switching depending on the position of a. That is, when the magnetic head 22a is located in the overlap area shown by diagonal lines in _FIG .
P), otherwise (Y _FM CP)
A _FM ).

When a recording current is applied to the magnetic head 22b, a signal is transmitted through the circuit from 13b to 19b in the same way as described above.

The switching timing of each switch during the above-described recording will be explained with reference to the time chart shown in FIG. Signal A is a head switching pulse made from a tack pulse that indicates the position information of the magnetic head. For example, a period _T1 in which signal A is at a low level means that the magnetic head 22a is located on the white track in FIG. and the section where signal A is high level
T ₂ means that the magnetic head 22b is located on the white track.

Further, signal B is a signal synchronized with signal A, and is the first signal.
This is a signal that is generated almost coincident with the overlap area (30 degree section) indicated by diagonal lines in the figure.In section _T3 , the magnetic head 22a is located in the overlap area, and in section _T4 , the magnetic head 22b is overlapping. Located in a barrage area. Therefore, switch 13
The signals (Sig1) and (Sig2) that control the magnetic heads 22a and 13b are (A・B) and (・B), respectively, and for example, in the section where the magnetic head 22a is located in the overlap area.
At _T3 , the switch 13a is connected to the output side of the adder 11 as shown, and at other times, the switch 13a is connected to the output side of the adder 12. Similarly, switch 13b is connected to section T ₄
Contrary to what is shown in the figure, it is connected to the output side of the adder 11, and at other times it is connected to the output side of the adder 12. The control signal (Sig3) is a signal for controlling the output DC voltage of the buffer amplifiers 14a and 14b, and during normal recording, the output DC voltage sufficient to drive the recording amplifiers 17a and 17b is maintained. As shown in FIG. 3, at this time (Sig3) the level is low.

(Sig4) is at a high level during recording, making the switches 18 and 19 conductive, and is inverted by the inverter 23, causing signal 20 to be cut off at (4).

Next, circuit operation during reproduction will be explained. During playback, the (PB) signal becomes high level, the aforementioned (Sig4) becomes low level, and switches 18 and 19
is cut off, and the switch 20 is made conductive. The signals reproduced from the magnetic heads 22a and 22b are passed through rotary transformers 21a and 21b to capacitors.
C ₃ , C ₃ '
After being sufficiently amplified by a and 24b, the switch 25
a, 25b. 25a is the magnetic head 22
a, 22b played field by field (Y _FM
CPA _FM ) is switched by the head switching pulse A to output a continuous reproduction signal, and the output waveform is as shown in C in FIG. 3.

Further, 25b outputs a continuous reproduction signal D by switching the ( _APCM P) reproduced field by field by the magnetic heads 22a and 22b with a signal inverted by the inverter 26.

The output signal of the switch 25a is processed by an audio FM signal reproduction processing circuit, a luminance signal reproduction processing circuit 52, and a chroma signal reproduction processing circuit, and the audio signal is sent to the terminal 3.
3, the video signal is output to the terminal 34.

The output signal ( _APCM ) of the switch 25b is processed by the PCM signal processing circuit and then outputted to the terminal 36 as an audio output.

During playback as explained above, there is a possibility that the current (10 to 20mA) flowing through the recording amplifier may excite the signal to the input side of the playback head preamplifier 24 via the power supply and ground, which may cause oscillation etc. due to the high gain amplifier. becomes. Therefore, during reproduction, it is necessary to set Sig3 to a high level, sufficiently lower the output DC voltage of the buffer amplifier 14, and stop the operation of the recording amplifier 17.

Next, circuit operation during PCM post-recording will be explained. As described in FIG. 1, PCM dubbing records a PCM audio signal while reproducing a video signal. During PCM dubbing, considering the user's operations, it is necessary to switch from playback mode to dubbing mode, and at the same time, the playback circuit must be constantly operating, so the (PB) signal is at a high level as shown in Figure 3. When the (Arec) signal is at a high level, the dubbing mode is activated. Magnetic head 22a, 2
The signals (Sig4) and (Sig5) that control switches 18, 19, and 20 are respectively ( Similar to Sig1) and (Sig2), (A・B) and (・B) can be used. Also, since a PCM audio signal for recording is required, the PCM signal processing circuit 35 must be set to recording mode, and the mode switching signal (Sig6) is set to the same level during dubbing and recording, as shown in Figure 3. There is a need.

Also, during playback, to avoid interference from the recording side to the playback side, the output DC of buffer amplifiers 17a and 17b is
It is necessary to lower the voltages V ₁ and V ₂ , and as shown in FIG. 3, (Sig3) is kept at a high level except for the overlap section, and the recording amplifiers 18a and 18b are stopped. As a result, the image quality in areas other than the overlap section during dubbing can be ensured in the same way as during playback.

The recording currents i ₁ , i ₂ and the reproduction preamplifier output C during dubbing are as shown in FIG. The shaded area in C is caused by the recording currents i ₁ and i ₂ of the PCM audio signal leaking to the reproduction side due to crosstalk of the rotary transformer.

Next, the logic circuit that generates the control signals (Sig1) to (Sig5) will be specifically explained. (Sig1) to (Sig5) are generated by (PB), ((REC), (Arec) output from the system controller in response to the VTR operation buttons, head switching pulse A, and B indicating the overlap section.

As shown in FIG. 3, the output signal of the switch 25a lacks the reproduced signal during the period in which the PCM signal is being recorded. Therefore, on the monitor screen
The video signal is not reproduced at the bottom of the screen, which corresponds to the PCM signal recording period. Chroma signal reproduction processing circuit 53
In order to eliminate time axis fluctuations in the reproduced chroma signal, a synchronization circuit is provided for the frequency of the reference oscillator and the reproduced chroma signal. This synchronization circuit needs to use a burst signal of the reproduced chroma signal, and uses a burst gate pulse generated by a horizontal period signal or a signal equivalent thereto. Therefore, when performing PCM dubbing as described above, if the playback signal is missing, a normal burst gate pulse cannot be obtained, and the frequency of the playback chroma signal will not be stabilized, causing the color killer circuit to operate and causing the colors on the monitor screen to change. It may disappear. In the embodiment shown in FIG. 2, the operation of the synchronization circuit of the chroma signal reproduction processing circuit 53 is temporarily stopped by the signal B indicating the PCM signal recording period, thereby preventing malfunctions such as color fading as described above.

Next, the operation of the chroma signal reproduction processing circuit 53 will be explained in detail.

FIG. 4 shows an embodiment of the chroma signal reproduction processing circuit 53. 101 is a reproduction signal input terminal, 102 is a low pass filter (abbreviated as LPF), and 103 is an ACC
104 is a frequency conversion circuit (abbreviated as converter), 105 is a band pass filter (hereinafter abbreviated as BPF), 106 is a comb filter circuit for removing adjacent crosstalk, and 107 is a de-enhance circuit, a color killer circuit, etc. processing circuit,
108 is a reproduced chroma signal output terminal, and 109 is a reproduced chroma signal output terminal.
BPF 126 is a conversion carrier generation circuit.
For example, in the NTSC system, the conversion carrier generation circuit is
_SC + (47 + 1/4) _H ( _SC ;
Color subcarrier frequency, _H ; horizontal sync frequency), CH-2
_SC + (47-1/4) _H on the CH-1 track, _SC + (47-1/8) _H on the CH-1 track, _SC + (47-5/8) _H on the CH-2 track in the PAL system generates a carrier signal. The conversion carrier generation circuit 126 is
Voltage controlled oscillator circuit (abbreviated as VCO) 124, phase detection circuit 123, reference oscillator 121, VCO that oscillates at 378 _H in the NTSC system and 375 _H in the PAL system.
116, frequency dividing circuit 114, phase detection circuit 115,
It consists of a 1/8 frequency divider circuit 113, a phase shift circuit 111, a converter 110, an equivalent pulse removal circuit 118, and a burst gate pulse generation circuit 120. The frequency dividing circuit 114 is 1/378 in the NTSC system.
In the PAL system, by setting the frequency to 1/375, the VCO 116 oscillates at the frequency mentioned above. Therefore, the output of the 1/8 frequency divider circuit 113 has a frequency of (47+1/4) _H in the NTSC system and (47-1/8) _H in the PAL system.

The phase shift circuit 111 is controlled by the head switching pulse of the terminal 112, and in the NTSC system, it remains unchanged for the CH-1 track, and for the CH-2 track, it is reversed by 180 degrees every horizontal water period, and for the PAL system, it changes by 180 degrees every horizontal water period.
The CH-2 track outputs a signal that is phase-shifted by -90° every horizontal period. The converter 110 and BPF 109 convert the output signal of the phase shift circuit 111 and approximately
A sum signal is extracted from the output signal of the VCO 124 oscillated by _{the SC} and is supplied to the converter 104. The phase detector 123 inverts the phase ratio of the burst signal output from the comb filter 106 and the output signal from the reference oscillator 121, and outputs the VCO 1 so that the phases of the two match.
24. On the other hand, as mentioned above, during PCM signal post-recording, as shown in Figure 5C, the PCM
The reproduced signal is lost during the signal recording period. In the figure, B', E, and F are enlarged periods of G, E and F indicate the input signals of the synchronizing signal input terminal 117 in FIG. 4, and F indicates the output signal of the switch circuit 119, respectively. H indicates the horizontal period. The signal at the synchronization signal input terminal 117 corresponds to the output signal of a period separation circuit (not shown) that extracts only the synchronization signal from the luminance signal. As shown in Figure 5, this synchronization signal E becomes a noise signal because the PCM signal is input to the synchronization separation circuit during the PCM recording period (the period in which B and B' are at high level in the figure). Become. Switch circuit 119 in FIG. 4 prevents this noise signal from being input to phase detection circuit 115 and burst gate pulse generation circuit 120. terminal 13
0 is the input terminal for the signal corresponding to the PCM recording period (corresponding to B in the above-mentioned Fig. 3), and terminal 311 is the input terminal for the signal indicating the dubbing mode (corresponding to (Arec) in the above-mentioned Fig. 3). terminal,
129 is a game. The switch circuit 119 is controlled by a PCM signal recording period signal input to a control signal input terminal 125. The PCM signal recording period signal is output by gate 129 in the post-recording mode.
It is high level only during the period when the PCM signal is being recorded. The switch circuit 119 switches as shown in the figure when the terminal 125 is at a high level, and switches in the opposite manner as shown in the figure during a period of a low level. This results in
During the post-recording period of the PCM signal, the noise signal is transmitted to the phase detection circuit 115 and the equivalent pulse removal circuit 11.
8 can be prevented from being input.

FIG. 6 is a block diagram illustrating another embodiment. Blocks that are the same as in FIG. 4 are designated by the same numbers.
The difference between FIG. 6 and FIG. 4 is that a switch circuit 119 is inserted between an equivalent pulse removal circuit 118 and a burst gate pulse generation circuit 120. Burst gate pulse generation circuit 1
20 is composed of a counter 129 and a logic circuit 130. The counter 129 is the equivalent pulse removal circuit 11
The output signal from VCO 116 is used as a clock signal, and signals _S1 and _S2 corresponding to the rising and falling edges of the burst gate pulse are output. Logic circuit 130 generates burst gate pulses from signals S ₁ and S ₂ . Figure 6 shows VCO1
16 and the phase detector 115 that controls it, the response speed of the so-called AFC circuit is slow and the terminal 117
This is an example in which the influence of noise signals generated in the above is small. In this case, the switch circuit 119
may be arranged to prevent the counter 129 of the burst gate circuit 120 from being reset by a noise signal.

In FIG. 6, the same effect can be obtained even if the switch circuit 119 is inserted between the burst gate circuit 120 and the phase detection circuit 123.

FIG. 7 is a block diagram illustrating another embodiment. Blocks that are the same as in FIG. 4 are designated by the same numbers.
The difference between Fig. 7 and Fig. 4 is that the phase detector 1
15, VCO 116, and phase detector 123.
Switch circuit 11 between each VCO 124
9,122 is inserted. Switch circuits 119 and 122 are input to terminal 125
It is controlled to close outside the PCM recording period by the PCM signal recording period signal.

FIG. 8 is a block diagram illustrating another embodiment. Blocks that are the same as in FIG. 4 are designated by the same numbers. 1
27 is a frequency detection circuit, and 128 is an addition circuit.

The difference between FIG. 8 and FIG. 4 is that the converter 11
0 is the output signal of the reference oscillation circuit 121. The VCO 116 is substantially controlled by the output signal of the frequency detection circuit 127 and the output reliability signal of the phase detection circuit 123. terminal 125
The switch circuit 119 controlled by the PCM recording period signal input to the adder circuit 127 and the VCO 11
It is inserted between 6 and 6.

In FIG. 8, the phase detection circuit 123 detects the phase difference between the reference oscillator 121 and the burst signal,
A so-called PLL circuit is configured to control the VCO 116 so that the phase difference between the two is constant. A frequency detection circuit 127 detects the oscillation frequency of the VCO 116 and prevents the above-mentioned PLL circuit from falsely locking.

The switch circuit 119 is controlled to be closed except during the PCM signal recording period.

FIG. 9 is a block diagram illustrating another embodiment. Blocks that are the same as in FIG. 8 are designated by the same numbers. The difference between FIG. 9 and FIG. 8 is that the frequency detection circuit 12
7, addition circuit 128, and phase detection circuit 123
This is because switch circuits 119 and 122 are inserted between the adder circuit 128 and the adder circuit 128, respectively. Switch circuits 119 and 122 are input to terminal 125
The PCM signal recording period signal is used to control it to close outside the PCM signal recording period.

FIG. 10 is a block diagram illustrating another embodiment. Blocks that are the same as in FIG. 8 are designated by the same numbers.
202 is a 1/3 frequency divider circuit, 203 is a gate circuit, 2
04 is a counter 205 is a logic circuit, 206 is a logic circuit, 207 is a 1/6 frequency divider circuit, 210-250 are transistors, 251-267 are resistors, 268-
270 is a capacitor, 271 to 275 are DC voltage sources, 301 is an input terminal of the frequency detection circuit 127,
302 is a synchronization signal input terminal, 303 is an input terminal for a PCM signal recording period signal, 304 is an output terminal of the frequency detection circuit 127, and 305 is a phase detector 123
306 is an input terminal for a PCM signal recording period signal, 307 is a burst gate pulse input terminal, 308 is a burst signal input terminal, and 309 is a reference signal input terminal. The reference oscillation circuit 121, phase detector 123, and VCO 116 constitute a well-known PLL circuit, and the output signal of the reference oscillation circuit 121 and the terminal 3
It operates to match the frequency and phase of the burst signal of 08. Transistors 218, 216, 217, 212, 213, 2 forming a phase detector
14 and 215 constitute a well-known so-called full-balanced phase detector. The transistor 218 is turned on during the burst signal period by the burst gate pulse of the terminal 307. Transistors 210, 211
is a well-known current mirror circuit. The transistors 230 and 231 operate as a switch circuit that is turned on during the burst period, and together with the capacitor 269 constitute a sample and hold circuit. Resistor 257 is a load resistance. Resistor 267 and capacitor 268 are what is called a loop filter. transistor 2
33 and 219 are controlled by a PCM signal recording period signal connected to the terminal 306 to be turned ON during the period in which the PCM signal is being recorded. Therefore, when the transistors 218 and 232 are turned off and a noise signal is input to the terminal 117, the phase detection circuit 123
Malfunctions can be prevented.

The above-mentioned pseudo lock frequency of the PLL circuit composed of the reference oscillation circuit 121, phase detection circuit 123, and VCO 116 is such that the burst signal frequency is NTSC.
_SC ±1/2 _H for the system and _SC ±1/4 _H for the PAL system.

Therefore, the oscillation frequency of VCO116 is usually
_378H ± _2H in NTSC format, _375H ±1H in PAL format
It is necessary to oscillate within the range of . The frequency detection circuit 127 is provided for this purpose. Frequency detection circuit 12
The operation of step 7 will be explained using FIGS. 11 and 12. Horizontal synchronization signal 10a input to terminal 302
generates a signal divided by a 1/6 frequency divider circuit, and the signal 1
0b opens the gate circuit 203 and terminal 301
VCO input via 1/3 frequency divider circuit 202
116 signals are supplied to the counter 204. 1/3
The frequency dividing circuit 202 is used to reduce the operating speed of the counter 204, and its frequency dividing ratio is not limited to 1/3. Counter 204 receives reset pulse 10c generated by logic circuit 206.
It is reset by Signal 10b and Signal 1
The timing of 0c is as shown in FIG. Therefore, the counter 204 starts counting by the output signal of the gate circuit 203. logic circuit 2
05 is the signal 10 according to the output signal of the counter 204.
, 10g. In Figure 12, the diagram shown by is for the NTSC system, and the diagram shown by is for the NTSC system.
This is the case with the PAL system. In the case of the NTSC system, 10 becomes a high level (abbreviated as 〓H〓) when the clock number of the counter 204 is 380 or more, and 10g becomes a high level (abbreviated as 〓H〓).
After 376, it becomes low level (abbreviated as 〓L〓).
In the PAL system, 10 becomes 〓H〓 after 376 and becomes 1
0g becomes 〓L〓 after 374. On the other hand, a signal 10d is connected to the base of the transistor 240, and is turned on during the period shown in FIG. The following explanation is for the NTSC system. In FIG. 11, when the oscillation frequency of the VCO 116 is higher than 380 _H , the signal 10 becomes "H" and the signal 10g becomes "L" during the period when the signal 10d is "H" as shown in FIG. Therefore, in FIG.
is turned on, and transistor 237 is turned off. Transistors 234, 236, and 235 are well-known current mirror circuits, and their explanation will be omitted. When the transistor 238 is turned on, the voltage at the terminal 304 is lowered, and the oscillation frequency of the VCO 116 is controlled to be lowered. The oscillation frequency of VCO116 is 376~
In the case of 380 _H , both signals 10g and 10 are 〓L〓
, and both transistors 237 and 238
It's off. The oscillation frequency of VCO116 is 376 _H
If it is lower, the signal 10 is 〓L〓 10g is 〓
becomes H〓, transistor 237 turns on, 238
turns off. When the transistor 237 is turned on, the transistor 235 is also turned on, and the voltage at the terminal 304 increases, controlling the oscillation frequency of the VCO 116 to be increased. Transistor 250 is connected to terminal 303.
It is controlled by the PCM signal recording period signal to turn ON during the period when the PCM signal is being recorded. Therefore, even if the transistor 240 is turned off and a noise signal is input to the terminal 17, the frequency detection circuit 127
Malfunctions can be prevented. In the embodiment of FIG.
While recording the PCM signal, transistor 2
Terminal 30 because 18, 232, 240 are OFF
5,304 becomes high impedance and VCO11
Since the control voltage 6 is held at a voltage other than the PCM signal recording period by the capacitor 269, the frequency of the reproduced chroma signal can be stabilized. Therefore, high quality images can be reproduced on the monitor screen without color fading.

FIG. 13 is a block diagram illustrating another embodiment. In FIG. 13, blocks that are the same as in FIG. 10 are designated by the same numbers. The difference between FIG. 13 and FIG. 10 is that a switch circuit 119 and a capacitor 278 are used instead of transistors 233, 219, and 250.
and transistor 277 are connected. The switch circuit 119 opens during the PCM recording period to prevent noise signals from being input to the equivalent pulse removal circuit 118. As a result, there is no input signal to the burst gate pulse generation circuit 120, and no burst gate pulse is generated, thereby preventing the phase detection circuit 123 from malfunctioning. transistor 277
is turned on during the dubbing period by the dubbing mode signal (corresponding to Arec in FIG. 2) inputted from the terminal 310. The frequency detection circuit 127 resets the counter 204 based on the horizontal synchronization signal input to the terminal 302 as described above. Therefore, during the period of recording the PCM signal, switch 11
9 is opened, the counter 204 is not reset during this period, and the transistor 237 or 238 may be turned on regardless of the frequency of the VCO 116. Transistor 277 prevents malfunction occurring in this case. Capacitor 278 is
A sufficiently large capacitance value is selected for the capacitor 270 so as to sufficiently smooth the malfunction current that occurs during each PCM signal recording period. In FIG. 13, the switch circuit 119 is not a particularly necessary element; for example, there is a well-known technique for devising the time constant of a sync separation circuit (not shown) to prevent a sync signal from being generated when a noise signal is input. . Therefore, in such a circuit configuration, the switch circuit 119 is not necessary.
It is important to substantially prevent noise signals from being input to the frequency detection circuit 127 and the burst gate circuit 120.

[Effects of the Invention] According to the present invention, it is possible to provide a recording/playback device that performs after-recording of a PCM signal in a helical scan VTR that records a video signal and a PCM audio signal in an overlapping manner. Also,
This has the effect of preventing color fading in monitor images, which was a problem when performing after-recording of PCM signals, and allowing high-quality images to be reproduced.

[Brief explanation of drawings]

FIG. 1 is a tape pattern diagram explaining overlap PCM, FIG. 2 is a block diagram of a signal processing circuit showing an embodiment of the present invention, FIG. 3 is a timing diagram explaining the operation of FIG. 2, and FIG. Block diagram of a chroma signal reproduction processing circuit showing an embodiment of the present invention, No. 5
The figure is a timing diagram explaining FIG. 4, FIG. 6, FIG. 7, FIG. 8, FIG. 9, and FIG. 10 are block diagrams showing other embodiments of the present invention, and FIGS. 11 and 12. is a timing diagram explaining the operation of FIG. 10, and FIG.
The figure is a block diagram of another embodiment of the invention. 53...Chroma signal reproduction processing circuit, 123...
Phase detection circuit, 121...Reference oscillation circuit, 124
... VCO, 116 ... VCO, 120 ... Burst gate pulse generation circuit, 114 ... Frequency division circuit,
115... Phase detection circuit, 119... Switch circuit, 122... Switch circuit, 127... Frequency detection circuit.

Claims (1)

[Scope of Claims] 1. When a magnetic tape on which video information including color information is sequentially recorded as a diagonal track is played back alternately by two rotating magnetic heads, the rotating magnetic head that is not in the playback state is used to record diagonal tracks. In a helical scan VTR that has an after-recording mode in which other information is recorded at a position where the track is extended, the chroma reproduction system includes an oscillation means that generates a conversion carrier for converting the frequency of the reproduced color information, and a reproduction unit. control means for controlling the phase of the conversion carrier by comparing the phase of the carrier frequency of the color signal with the output signal of the oscillation means, wherein one of the two rotating magnetic heads is in a reproducing state; A magnetic recording/reproducing apparatus characterized in that the phase control operation of the control means is stopped during a period when the other is in the recording state.