JPS61225992A - Recording and reproduction processing circuit - Google Patents

Abstract

PURPOSE:To prevent the effect of noise at processing a chrominance carrier signal while recording and reproduction by making the timing and time width of a burst gate pulse formed from a horizontal synchronizing signal coincident nearly with those of the chrominance carrier signal and a burst signal at recording and reproduction. CONSTITUTION:When the midpoint between the chrominance carrier signal and the burst gate pulse in a recording processing system and a reproduction processing system is made coincident, the time width of the burst gate pulse is made nearly equal to the time width of the burst signal under any condition. Thus, a burst signal amplifier circuit 8 in the recording processing system amplifies almost only the burst signal in the chrominance carrier signal B, a P.C 16 extracts almost only the burst signal from the chrominance carrier signal B and the effect of noise is reduced remarkably. Almost only the burst signal in a chrominance carrier signal F is attenuated by a burst signal attenuation circuit 31 also in the reproduction processing system, a P.C 35 extracts almost only the burst signal from the chrominance carrier signal and the effect of noise is reduced remarkably.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a magnetic recording and reproducing processing circuit for recording and reproducing color video signals, and in particular, a magnetic recording and reproducing processing circuit for extracting a burst signal from a carrier color signal during recording and reproducing. The present invention relates to a burst gate pulse generation circuit that generates burst gate pulses.

[Background of the invention]

Conventionally, in magnetic recording and reproducing devices (hereinafter referred to as VTRs) that record and reproduce color video signals, the luminance signal of this color video signal is converted to FM, the carrier color signal is converted to a low frequency signal, and then recorded. , the FM-modulated luminance signal is demodulated, and the carrier color signal, which has been converted to a low frequency band, is converted to a high frequency band to obtain the original color video signal.

FIG. 7(a) is a block diagram showing an example of a recording processing system in a conventional recording/reproducing processing circuit of such a VTR,
1 is an input terminal, 2 is an automatic gain control circuit, 3 is a low-pass filter, 4 is an FM modulation circuit, 5 is a high-pass filter, 6
is a band pass filter, 7 is an automatic clock control circuit, 8 is a burst signal amplification circuit, 9 is a frequency conversion circuit, 10 is a low pass filter, 11 is an addition circuit, 12 is a recording amplification circuit,
13 is a magnetic head, 14 is a synchronization signal separation circuit, 15 is a burst gate pulse generation circuit, 16 is a phase comparison circuit, 1
7 is a variable frequency oscillator, 18 is a phase comparison circuit, 19 is a variable frequency oscillator, 20 is a frequency dividing circuit, 22 is a frequency conversion circuit, and 23 is a band pass filter.

7) is a block diagram similarly showing the reproduction processing system, in which 24 is a preamplifier 1, 25 is a peaking circuit, and 26 is FMyt! J1 circuit, 27 is a low-pass filter, 28 is a frequency conversion circuit, 30 is an automatic chroma control circuit, 31 is a burst signal attenuation circuit, 32 is a comb filter, 33 is an adder circuit, 34 is an output terminal, 35 is a phase comparison circuit , 36 is a crystal oscillator, 37 is a frequency dividing circuit, and 38 is a band pass filter, and the same reference numerals are given to the parts corresponding to FIG. 7 (al).

First, the operation of the recording processing system shown in FIG. 7(a) will be explained.

Is the color video signal input from input terminal 1 on the automatic gain side? After the amplitude is controlled by a 1ll (hereinafter referred to as AGC) circuit 2, a low pass filter (hereinafter referred to as LPF) 3
and the luminance signal is separated. This luminance signal is
After being FM-modulated by the FM modulation circuit 4, the signal is supplied to the addition circuit 11 via a high-pass filter (hereinafter referred to as HPF) 5.

On the other hand, the carrier color signal is separated from the color video signal by BPF6, and an automatic chroma control circuit (hereinafter referred to as ACC circuit)
After the amplitude is controlled in step 7, only the burst signal is amplified by about 6 dB by the burst signal amplification circuit 8. This carrier color signal is added to the frequency conversion circuit 9, and a carrier signal fc from a band pass filter (hereinafter referred to as BPF) 23 is added to the frequency conversion circuit 9.
The frequency is converted by 40fH to the output of LPFIO.
A low frequency carrier color signal of (f is the horizontal scanning frequency) is obtained. This carrier color signal is sent to F by an adder circuit 11.
The M-modulated luminance signal is mixed with the recording amplifier circuit 12.
The information is recorded on a magnetic tape (not shown) via the magnetic head 13.

Carrier signal fc is created as follows.

Variable frequency oscillator (hereinafter abbreviated as VCO) 19° phase comparison circuit (hereinafter abbreviated as P and C) 181 Frequency divider circuit 20 is A
An FC loop is formed, and VCO 19 is synchronized signal separation circuit 1.
It oscillates at an oscillation frequency that is 160 times the frequency fH of the horizontal synchronizing signal obtained from 4. The output of this VCO 19 is input to the frequency dividing circuit 21, and is divided into 1/4 to give a frequency of 40 f
At the same time, the phase is rotated by 90 degrees for each horizontal scanning period.

On the other hand, the VCO 17, P, and C 16 form an APCJL/- loop and supply the frequency conversion circuit 22 with a signal f having a frequency of 3.58 MHz synchronized with the burst signal (3.58 MHz).

The frequency conversion circuit 22 receives 40f1 from the frequency dividing circuit 21.
A signal with a frequency of
is being created. Therefore, by supplying this carrier signal fc and the carrier color signal from the burst signal amplification circuit 8 to the frequency conversion circuit 9, the difference frequency component between them can be converted to L.
If selected by PFIO, a carrier color signal converted to a low frequency of 40 f m is obtained.

Here, the burst signal amplification circuit 8, P, and C16 obtain the horizontal synchronization signal from the synchronization signal separation circuit 14 by delaying it by the burst gate pulse generation circuit 15 so that it almost coincides in time with the timing of the burst signal. Controlled by pulses. In other words, the burst signal amplification circuit 8 amplifies only the Perth day code by 6 dB, and in the P and C16,
A signal f, which is phase-synchronized with the burst signal, is generated.

Next, the operation of the reproduction processing system shown in FIG. 7(b) will be explained. Note that here, the LPF 3. used in the recording processing system (FIG. 7(a)) is used. BPF6. Synchronous signal separation circuit 14.
The burst gate pulse generation circuit 15 and VCO 19 are also used as this reproduction processing circuit (in FIG. 7(b), these are given the same reference numerals as in FIG. 7(a)), for recording and reproduction in the VTR. The configuration of the processing circuit is simplified. Other circuits can also be used for both the recording processing system and the playback processing system, but switches are required to switch these between recording and playback.
The configuration can be simplified in consideration of the number of these switches.

In FIG. 7 (bl), No. 13 recorded on a magnetic tape (not shown) is reproduced by the magnetic head 13, and after being amplified by the preamplifier 24, the FM-modulated luminance signal has a frequency near the carrier frequency. Peaking circuit 25
is demodulated into the original luminance signal by the FM demodulator 26 and LPF 3.

On the other hand, the carrier color signal converted to a low frequency in the reproduced signal is extracted by the LPF 27, and is extracted by the frequency conversion circuit 28.
Since the carrier signal (, / is input to the zero frequency conversion circuit 28, which is applied to Attenuation circuit 31
Only the burst signal is reduced by GdB and returned to the original carrier color signal.

Further, in order to improve the S/N ratio, this carrier color signal passes through a comb filter 32, and further passes through a luminance signal and an adder circuit 33.
The original color video signal is reproduced at the output terminal 34.

As mentioned above, the frequency conversion circuit 28 has the function of converting the carrier color signal that has been converted to a low frequency to the original frequency, and at the same time, the frequency conversion circuit 28 has the function of converting the carrier color signal that has been converted to a low frequency to the original frequency. Here, a signal processing circuit that creates a carrier signal (,r) for correcting the time axis fluctuation of the carrier color signal will be explained. The burst signal and the output signal of the crystal oscillator 36 which oscillates at 3.58 MHz are controlled by the error voltage obtained by comparing the phases at P and C35, and the oscillation frequency is
Frequency 1 according to this error voltage centered around 160 f n
60fN+Δf'. The output signal of the VCO 19 is divided into 1/4 by the frequency dividing circuit 37 and inputted to the frequency conversion circuit 38. After the frequency is converted by the signal f3 from the crystal oscillator 36, the sum frequency component is extracted from the BPF 39. A carrier signal fc' to be applied to the frequency conversion circuit 28 is obtained.

Now, the carrier color signal reproduced from the magnetic head 13 and passed through the LPF 27 has time axis fluctuation, and its frequency is 40.
If fl(+Δf), then if the carrier signal added to the frequency conversion circuit 2nd day is fc'=4Of,+f+f, then the frequency of the carrier color signal output to BPF6 is f3, and the time axis fluctuation component Δf will be removed.Carrier signal fc′
is r,'=tOfo+Δf+f.

To achieve this, the oscillation frequency of VCO 19 must be 4 (40 f
, +Δr) (in addition, 4
Δf−Δf) This vCo19 is P.

At C35, the output f s (3
, 58 MHz) and the burst signal extracted from the carrier color signal from the comb filter 32 by the burst gate pulse from the burst gate pulse generation circuit 15.

Here, the burst signal attenuation circuit 31, P and C35 are as follows:
It is controlled by a burst gate pulse obtained by delaying the horizontal synchronizing signal from the synchronizing signal separation circuit 14 by the burst gate pulse generating circuit 15 so as to substantially coincide with the timing of the burst signal.

Next, burst gate pulse generation circuit 1 in FIG.
5 will be explained.

FIG. 8 is a timing chart showing the operation of the burst gate pulse generation circuit 15 in FIG. 7). The figure (71) is P from the comb filter 32 (Figure 7 (b)).
, C35, the figure shows the burst gate pulse output from the burst gate pulse generation circuit 15; Shows the signal extracted from the signal.

As shown in FIG. 8, if the period of the burst signal in the carrier color signal is l, the time width of the burst gate pulse signal is l.
' is this period! Therefore, noise is present before and after the burst signal in the signal extracted from the carrier color signal by this burst gate pulse.

This burst signal is phase-detected by the output f s (=3.58MHz) of the crystal oscillator 36 at P and C35, and the VCO 19 is controlled by the error signal, but during the burst gate period shown in FIG. The noise is l), and since an error signal corresponding to the noise is generated at the output of the C35, the VCO 19 is also controlled by noise other than the burst signal, and the time axis fluctuation cannot be suppressed sufficiently.

For this reason, the time width 2' of the burst gate pulse must be as equal as possible to the time width l of the burst signal BG. However, for the reason described below, the time axis β' of the burst gate pulse is the time width l of the burst signal BG. It has to be made larger than the axis l to some extent.

FIG. 9 is a timing chart showing the relationship between the burst gate pulse and the burst signal in the carrier color signal in the recording processing system shown in FIG. The blanking period is
Signal B represents a carrier color signal supplied to burst signal amplification circuit 8 and P, C1B, and signal C represents a burst gate pulse output from burst gate pulse generation circuit 15, respectively. Further, H3 is a horizontal synchronization signal, and in the following explanation, the falling edge (leading edge) of the horizontal synchronization signal H3 of the color video signal A is used as a time reference, and this color video signal A
burst signal B from the falling edge of horizontal synchronization signal H3.
Let the time at the middle point of the period G be τa sec.

In FIG. 7(a) and FIG. 9, color video signal A
is supplied to the BPF 6 and the carrier color signal B is separated, so that the carrier color signal B is delayed with respect to the color video signal A by a delay time τ3 at the BPF 6.

On the other hand, in order to separate the horizontal synchronization signal from the luminance signal and generate a burst gate pulse in the burst gate pulse generation circuit 15 based on this signal, the LPF 3° synchronization signal separation circuit 14 and the burst gate pulse generation circuit 15 each delay the horizontal synchronization signal. τVL+τ3 in time. A delay of τ9 occurs. Therefore, in the color video signal A, the middle point of the burst signal BG delayed by the time τO from the falling edge of the horizontal synchronizing signal HS is the color video signal A in the input signal B of the burst signal amplification circuit 8, P, and C16. horizontal synchronization signal H3
lags the falling edge of (at τ.4), and
The output signal C of the burst gate pulse generation circuit 15 is delayed by the same amount ((τ.+rVL+τ, 10τ). Therefore, the time difference Δ′l″R between these is as follows.

Δ′1”R=(τ. 10 τ7L+τ, +τ,) − (τ. 10 τ,) 2 τVL+τ8+τ, −τ3 ...+11 On the other hand, Figure 1θ shows the reproduction processing system shown in Figure 7(b). 2 is a timing chart showing the relationship between the burst gate pulse and burst No. 48 in the carrier color signal, in which the signal F is the reproduction signal of the magnetic head 13, and the signal F is the synchronization signal separation circuit 14.
The signal F corresponds to the horizontal blanking period of the luminance signal input to the burst signal attenuation circuit 31, and the carrier color signal input to the burst signal attenuation circuit 31 and P, C35 (note that the burst signal attenuation circuit 31
(The delay time of the comb filter 32 is negligible), and the signal G indicates the burst gate pulse output from the burst gate pulse generation circuit 15. Also, here, the leading edge of the horizontal synchronizing signal in the reproduced signal is used as a reference, and the time from this to the midpoint of the burst signal is τ. shall be. Furthermore, the waveform obtained by demodulating this reproduced signal is shown by a broken line.

The luminance signal in the reproduced signal is delayed by τ□ in the peaking circuit 25, passes through the FMujLili device 26, and then passes through the LPF.
3 and delayed by τYL. From this luminance signal, τ1. A burst gate pulse G with a delay of τ
is obtained. The burst signal attenuation circuit 31 also includes an L
0 frequency conversion circuit 28 to which a carrier color signal delayed by rc at PF27 and τ3 at BPF29 is supplied. The delay time of the ACC circuit 30 can be ignored. A similar delay occurs in the carrier color signals supplied to P and C35. For this reason, the midpoint of the burst signal input to the burst signal attenuation circuit 31, P, and C35 lags the falling edge of the horizontal synchronizing signal of the reproduced signal by (τ.+τ6.+τ), and , the midpoint position of the burst signal of the reproduced signal is the signal G
As shown, after passing through the peaking circuit 25 to the burst gate pulse generation circuit 15, the falling edge of the horizontal synchronizing signal of the reproduced signal is (τPK + τVL + τ. + τ
, +τ,).

By the way, the relationship between the position of the burst gate pulse and the position of the burst signal is designed so that the midpoint of the burst signal BG and the midpoint of the burst gate pulse will be lost once in the reproduction processing circuit, which has relatively many noise components. . From this, the middle point of the burst gate pulse G is set at (τPml+τVL
+τ. +τ.

+τ, ), and the following condition may be satisfied between this delay and the midpoint of the burst signal BG of the signal F.

τ0+τcp+τII■τ□+τYL+τ. +τ, +τ
.

Therefore, τ, praise τCde+ τ−1 τVL−τ□−τ,
・ ・ ・ By setting the delay time τ of the burst gate pulse generation circuit 15 in this way, the burst signal BG and the burst gate pulse G are set in the burst signal attenuation circuit 31 and P, C 35 as shown in (2). It is possible to defeat the midpoint of the game.

By the way, in this way, the burst gate pulse generation circuit 1
When the delay time τ of LPF 3.5 is set, in the recording processing system of FIG. 7(a), LPF 3. Delay time due to synchronization signal separation circuit 14 and burst gate pulse generation circuit 15 and B
The difference ΔT between the delay time due to PF6 and the equation (1) above
From the above formula (2), R is ΔTR−(rVL+τ, −τ
, )+(τCP+τ.

Therefore, in the recording processing system, as shown in FIG. 9, the midpoint of the burst signal C is the burst in the carrier color signal B. It lags behind the midpoint of the signal BG by (TCP-τ□).

Therefore, in the reproduction processing system, for example,
As disclosed in Japanese Patent No. 13484, when attempting to extract only the burst signal BG from the carrier color signal F, that is, when the time width l' of the burst gate pulse G is made equal to the time width l of the burst signal BG, the recording process In the system, there is a time lag between the burst signal BG of the carrier color signal B and the burst gate pulse C by the time (τeP - τ■), and this burst signal BG is extracted by missing the period (τCP - τ□). That will happen. This is not desirable, and for this reason, in the reproduction processing system, the burst gate pulse G is extended by a small time width (τ, P−τ□) before and after the burst toy No. 8 BG under the carrier color signal. The time width l' is the time width of this burst signal BG! It's bigger than that.

In this way, in the recording signal processing system and the reproduction signal processing system,
LPF3. B['F6. It is necessary to make the time width l' of the burst gate pulse wider than the time width 1 of burst number 48. As a result, noise components before and after the burst signal are included during recording and playback, making it impossible to maintain sufficient synchronization with the human-powered burst signal during recording, and when playing back, the time axis of the carrier color signal There was a problem in that the correction could not be made sufficiently.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a recording/reproducing processing circuit which eliminates the problems of the prior art described above and is capable of preventing the influence of noise when processing carrier color signals during recording and reproduction.

[Summary of the invention]

In order to achieve this object, the present invention makes the delay time of the horizontal synchronizing signal in the burst gate pulse generation circuit different during recording and during reproduction, and the timing and time of the burst gate pulse formed from the horizontal synchronizing signal. width,
The feature is that the burst signal of the carrier color signal is made to almost match the burst signal during recording and during reproduction.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a recording/reproducing processing circuit according to the present invention. Figure (a) shows the recording processing system,
40. 41 is a burst gate pulse generation circuit, 42 is a switch circuit, and in FIG.
Figure (b) shows a regeneration processing system, in which the same reference numerals are given to the parts corresponding to the seventh opening) and Figure 1 (a), and redundant explanation will be omitted.

In FIG. 1(a), the switch circuit 42 is closed to the R side, and the burst gate pulse generation circuit 40 is used. Here, the delay time τYL of LPF3 regarding the horizontal synchronization signal
+Delay time τ of the synchronization signal separation circuit 14.

and the delay time τ of the burst gate pulse generation circuit 40
. The delay time τ, ′ of the burst gate pulse generation circuit 40 is set so that the sum (rVL+τ, +τ, ′) of the burst gate pulse generation circuit 40 is equal to the delay time τ of the BPF 6. As a result, as shown in FIG. 2 (which corresponds to FIG. 9),
The midpoint of the burst signal BG in the carrier color signal B input to the burst signal amplification circuit 8 and P, C 16 can be matched with the midpoint of the burst gate pulse C output from the burst gate pulse generation circuit 40.

In addition, in the first opening), the switch circuit 42 is closed to the P side, and the burst gate pulse generation circuit 41 is used. Here, the peaking circuit 25 regarding the horizontal synchronization signal
delay time τpH, delay time τ94 of LPF3. The sum of the delay time τ of the synchronization signal separation circuit 14 and the delay time τ and # of the burst gate pulse generation circuit 41 (τI+τVL
+τ, +τ, #) and the sum (τcP+τ3) of the delay time τCP of the LPF 27 and the delay time τ of the BPF 6, the burst gate pulse generation circuit 41
Set the delay time τ, #. As a result, Figure 3 (
This corresponds to FIG. 1O), as shown in FIG. The midpoint of the gate pulse G can be made coincident with the midpoint of the gate pulse G.

Therefore, if it is possible to match the midpoints of the carrier color signal and the burst gate pulse in the recording processing system and the reproduction processing system as described above, the time width of the burst gate pulse j! 1 (FIGS. 2 and 3) can be made approximately equal to the time width l of the burst signal, and the time width of the burst gate pulse can be made sufficiently shorter than in the prior art described above. That is, It'>1'>
It becomes. Therefore, in the recording processing system shown in FIG. 1(a), the burst signal amplification circuit 8
It is possible to amplify almost only the burst signal BG in the P
, C16 from the carrier color signal B to almost the burst signal BG.
The effect of noise on the recording process of the carrier color signal is greatly reduced.

Also, in the reproduction processing system shown in the first section, the burst signal attenuation circuit 31 can attenuate almost only the burst signal BG in the carrier color signal F, and P and C35 extract almost only the burst signal from the carrier color signal. This greatly reduces the influence of noise during reproduction processing of the carrier color signal.

In FIG. 1, the burst gate pulse generation means is composed of the burst gate pulse generation circuits 40 and 41 and the switch circuit 42, but another specific example is shown in FIG.
In the same figure, 43, 44, 45 are input terminals, 46 to 5
2 is a flip-flop circuit, 53 is a gate pulse generation circuit, 54 is a switching circuit, 55 is a reset pulse generation circuit,
56.57 is an AND gate, sg: 5B is a Nant gate, 59.60.61 is an inverter, and 62 is an output terminal.

In this specific example, by counting the reference pulses,
The pulse delay time and pulse width are set, and the count number is changed between recording and reproduction to generate a burst gate pulse whose timing matches the burst signal.

In the figure, a switching signal SW that is "L" during recording and "H" during playback is input to the input terminal 43.

The above reference pulse P0 is input to the input terminal 44.

Here, the output signal of the VCO 19 in FIG. 1 is assumed to be the reference pulse Pa. Therefore, the frequency of this reference pulse Pa is 16 fN (2.5 MHz).The horizontal synchronizing signal H5 from the synchronizing signal separation circuit 14 of FIG. 1 is input to the input terminal 45. D-type flip-flop circuit (
46 to 52 (hereinafter referred to as FF) operate on the rising edge of the input pulse, FF46.47 operates as a 4 frequency divider circuit, and FF
1a and 49.50 respectively constitute a frequency divider circuit.

Next, the recording operation of this specific example will be explained using the timing chart of FIG.

At this time, the switching signal SW from the input terminal 43 is “L”.
", and is supplied directly and inverted by the inverter 59 to the switching circuit 54. As a result, in the switching circuit 54, the Q output of the FF 46 passes through the Nantes gate 57, and the FF
The Q output of 47 is set to pass through a Nantes gate 58.

On the other hand, the horizontal synchronizing signal HS of negative polarity from the input terminal 45 is inverted by the inverter 61 and sent to the gate pulse generating circuit 53.
supplied to This gate pulse generating circuit 53 is set at the rising edge (leading edge) of the inputted horizontal synchronizing signal H3, and generates an "H" gate pulse G1. This gate pulse G1 turns on the AND gate 56, and the reference pulse Pa from the input terminal 44 turns on the AND gate 56.
The trigger pulse G2 is supplied to the T terminal of the FF 46, 47 via the trigger pulse G2. The Q output of FF47 is supplied to the D terminal of FF46, and the Q output of FF46 is supplied to the D terminal of FF47, so that the Q output of FF46 has a duty ratio of 50%, which is obtained by dividing the reference pulse P0 by 4. Further, the Q output of the FF 47 becomes a pulse delayed by 174 cycles (that is, one cycle of the reference pulse P0) than the Q output of the FF 46.

The Q output of FF46 is connected to the Nant gate 58' of the switching circuit 54.
is supplied to the T terminal of FF51 as a trigger pulse, and is also inverted by the inverter 60 and output to the FF5.
It is also supplied to the T terminal of No.2.

On the other hand, the Q output of FF46 is output from the Nant gate 58 of the switching circuit 54 as a trigger pulse, FF1a, 49.5
0 T terminal. Also, the D terminal of FF4B has an F
The Q output of F50 is output to the D terminal of FF49, and the Q output of FF48 is output to the D terminal of FF49.
The Q output of FF49 is supplied to the D terminal of FF50. In the initial state, the reset pulse G3 from the reset pulse generation circuit 55 causes F F
1a, 49.50 are reset, so their Q outputs are “H”. At the first rising edge of the Q output of FF47, the Q output of FF48 rises, and the
At the next rising edge of the Q output of FF 47, the Q output of FF 49 rises, and at the next rising edge of the Q output of FF 47, the Q output of FF 5Q rises and the Q output falls. Then, for each rising edge of the Q output of FF47, FF1a,
The Q output falls in the order of 49.50. Therefore, F.F.
The Q output of FF 48 is a H'' pulse with a width of 3 cycles of the Q output of FF 47, and the Q output of FF 49 is a pulse with a width of 1 cycle of the Q output of FF 47.

The Q output of FF4B is connected to the D terminal of FF52, and the Q output of FF4B is also connected to the D terminal of FF52.
The Q outputs of 9 are respectively supplied to the D terminals of FF51.

Therefore, when the Q output of FF49 rises, the F
At the rising edge of the Q output of F46, the Q output of FF51 becomes “
Inverted from “L” to “H”, 3 cycles 1 of Q output of FF47
When the Q output of 1tFF49 falls, its direct fi(7)
At the rising edge of the Q output of FF46, the Q output of FF51 is inverted from "H" to "L".

From the above, the Q output of FF51 rises at the rising edge of the 7th pulse of the reference pulse P0 from the leading edge of the horizontal synchronization signal H3 (referred to as the 7th pulse of the reference pulse PO, the same applies hereinafter), and the Q output of the FF51 rises, It will fall at the rising edge of the 199th = 7+4x3).

On the other hand, the Q output of FF48 is the first rising edge of the Q output of FF47 (the second rising edge of the reference pulse P0).
When the FF rises at
52's Q output is inverted from "L" to "Hl", and when the Q output of FF4B falls three cycles after the Q output of FF47 (the 14th (-2+4X3) rising edge of the reference pulse P0), the At the falling edge of the Q output of FF46 (the rising edge of the 177th -14+3 of reference pulse P0), the Q output of FF52 is inverted from "H'" to "L".Therefore, the Q output of FF52 is inverted from "H'" to "L". Rising at the 5th rising edge of P0, the 17th rising edge of the reference pulse P0
It will fall at the 7th rising edge.

The Q outputs of the FFs 51 and 52 are supplied to the AND gate 57, and by its logical operation, the reference pulse P0 is output to the output terminal 62.
A burst gate pulse G4 is obtained which rises at the 7th rising edge of the reference pulse P0 and rises at the 177th rising edge of the reference pulse P0. The time width of this burst gate pulse G4 is equal to 10 periods (-17-7) of the reference pulse Po.

In addition, the Q output of FF50 is inverted from H' to ``L'',
When the Q output is inverted from L'' to H', at that point the reset pulse generation circuit 55 generates the reset pulse G3,
As a result, the FFs 46 to 50 and the gate pulse generating circuit 53 are reset to the initial state, and wait until the next horizontal synchronizing signal Is is supplied from the input terminal 45.

In this way, each time the horizontal synchronization signal H3 is supplied,
A burst gate pulse G4 is obtained at the output terminal 62.

In FIG. 5, the burst gate pulse G4 is shown to partially overlap with the horizontal synchronizing signal (S), but in reality, due to delays in circuit blocks such as FFs 46 to 52, the burst gate pulse The pulse G4 is shown as shown in the figure because it is based on the reference pulse P0, which is delayed by a desired time from the horizontal synchronizing signal H3 and does not overlap in time.The same applies to FIG.

Next, the operation during reproduction will be explained using the timing chart of FIG.

In this case, the switching signal SW from the input terminal 43 is 1H.
”, the Q output of FF 47 is supplied to the T terminal of FF 51, and the Q output of FF 47 is inverted by the inverter 60 and supplied to the T terminal of FF 52.Furthermore, FF1a, 49. The Q output of the FF 46 is supplied to the T terminal of the FF 46.The other components are the same as those during recording.

Therefore, the rising edge of the Q output of FFd6 is
Since the Q output of "H" is delayed by 1) 4 cycles (one cycle of the reference pulse P0), the Q output of FF48 and FF49 is also delayed by one cycle of the reference pulse P0 from the time of optical recording, respectively. . Further, the Q output of the FF 47 also lags behind the Q output of the FF 46 by 174 cycles, that is, one cycle of the reference pulse P0.

From this, the Q output of H1 of FF51.52 is also delayed by one cycle of the reference pulse P0 compared to the time of recording, and the same is true for the burst gate pulse G4 obtained at the output terminal 62. In other words, this no-east gate pulse G4 rises at the 8th rising edge of the reference pulse P0, and is also 1
It will fall at the 88th rising edge.

As shown below, the burst gate pulse G4 during reproduction is set to the reference pulse P with the leading edge of the horizontal synchronization signal H3 as a reference, rather than the burst gate pulse G4 during recording.
o can be delayed by one period, and the times can be made equal. At this time, as shown in Figure 1 (b
If the difference (τeP - τ□) between the delay time τC2 of the LPF 27 and the delay time τ□ of the peaking circuit 25 at 1 is equal to one cycle of the reference pulse P0, almost one loss occurs during the burst signal period during recording and playback. A burst gate pulse will be obtained.

In the above specific example, by appropriately setting the division ratio of the reference pulse Pa, an arbitrary delay time difference (rep-τ
□) It goes without saying that it is possible to obtain a burst gate pulse that substantially matches the period of the burst signal during both recording and reproduction.

Further, the reference pulse Pa is not limited to only the output signal of the VCO 19.

(Effect of the invention〕 As explained above, according to the present invention, during recording.

At the time of reproduction, it is possible to use a burst gate pulse that is almost completely lost during the burst signal period of the carrier color signal, and it is possible to sufficiently suppress the influence of noise on the recording and reproduction processing of the carrier color signal. During recording, it is possible to process the carrier color signal in synchronization with the burst signal, and during playback, the time axis of the carrier color signal can be sufficiently corrected, thus solving the problems of the prior art described above. Therefore, it is possible to provide a recording/reproducing processing circuit with excellent functions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a recording/reproducing processing circuit according to the present invention, and FIG. 1(a) shows the recording processing system,
Figure 2 (b) shows the regeneration processing system, and Figure 2 shows the reproduction processing system shown in Figure 1 (
Fig. 3 is a timing chart of signals of each part in Fig. 1 (bl), Fig. 4 is a timing chart of signals of each part in Fig. A block diagram showing a specific example of
FIG. 5 is a timing chart showing the operation of this burst gate pulse generating means during recording, FIG. 6 is a timing chart showing the same operation during playback, and FIG. 7 is a block diagram showing an example of a conventional recording/playback processing circuit. 8 shows the relationship between the burst signal of the carrier color signal and the burst gate pulse in FIG. 7 (bl). Timing chart FIG. 9 is a timing chart showing the positional relationship of signals of each part in FIG. 7(a).
FIG. 0 is a timing chart showing the positional relationship of signals of each part in the 7th test. DESCRIPTION OF SYMBOLS 1... Color video signal input terminal, 4... FM modulation circuit, 9... Frequency conversion circuit, 13... Magnetic head, 14... Periodic signal separation circuit, 26... FM demodulation circuit , 28... Frequency conversion circuit, 40.41... Burst gate pulse generation circuit, 42... Switch circuit. ”;'1.:b”L 1”L” 2nd figure←τ-2r, -2. r − 13th i = Z hall is τi→ Sai5kaku T 6 Roa e E% '1'q prisoner ← T, "T" rt middle 7;'? "F-111"-74
Figure 0

Claims (1)

[Claims] During recording, the luminance signal of the color video signal is FM modulated, the carrier color signal is converted to a low frequency and recorded, and during playback, the FM
In a recording and reproducing processing circuit that performs FM demodulation of the modulated luminance signal and converts the carrier color signal that has been converted to a low frequency to the original frequency to obtain the color video signal, the delaying the horizontal synchronizing signal separated from the luminance signal of the color video signal by a first delay time to generate a first burst gate pulse whose timing and time axis substantially coincide with the burst signal in the carrier color signal; A horizontal synchronizing signal separated from the luminance signal that has been FM demodulated during reproduction is delayed by a second delay time to produce a second signal whose timing and time width almost match the burst signal in the carrier chrominance signal which is converted to the original frequency. The apparatus is characterized in that it is configured to include means for generating two burst gate pulses, and to process the respective carrier color signals during recording and reproduction based on the first and second burst gate pulses. Recording/playback processing circuit.