JPH01251719A - Surface treatment - Google Patents

Abstract

PURPOSE:To improve breakdown strength by setting a temperature of a substrate to be treated having irregularities or steps on the surface thereof to a liquefying temperature of an inert gas under partial pressure of the inert gas, and by subjecting the substrate to be treated to a dry etching process while covering the surface thereof with the inert gas to chamber the pointed edges thereon. CONSTITUTION:A sample having irregularities 31 on the surface of a single crystal silicon film, a polycrystalline silicon film, etc., worn due to RIE, etc., is placed within a vacuum container. Then, an inert gas is introduced to both an etching gas and an etching species to subject the sample to a dry etching process while maintaining the temperature of the sample at a temperature of liquefying the inert gas. As a result, the recessed portions are covered deep and the projected portions are covered thin by a liquid 32. This allows projected portions to be selectively etched, thereby contributing to reducing the irregularities and thus to flattening.

Description

Detailed Description of the Invention (Objective of the Invention) (Industrial Field of Application) The present invention relates to a surface treatment method in a semiconductor manufacturing process, and in particular to a surface treatment method for rounding the angle of unevenness or steps, or flattening an uneven surface. Regarding processing method.

(Prior Art) In recent years, so-called trench capacitor technology, in which a trench is dug in the surface of a semiconductor substrate and a capacitor is formed in the trench, has been attracting attention as a method of increasing the capacitance of a capacitor in a MOS dynamic memory.

With this technology, the capacitor capacity can be increased without increasing the area occupied by the device, allowing for miniaturization.

Extremely effective for high integration.

However, reactive ion etching (RI)
E) etc., the radius of curvature of the top and bottom corners of the groove is generally extremely small. When such grooves are thermally oxidized, thermal oxidation is a reaction in which the volume expands, so stress concentrates at steep corners and oxidation does not progress as much as at flat areas.
The obtained gate oxide film has a thin film thickness at an angle. When the oxide film is thin, the electric field strength increases, so when a capacitor is formed and operated, dielectric breakdown tends to occur at the corners, leakage current increases, and performance deteriorates, among other problems.

As a means to solve the above problems, high temperature thermal oxidation, so-called sacrificial oxidation, is often used. This method performs thermal oxidation at a high temperature where the stress is sufficiently low, and the supply of oxidizing agent is higher at the upper corners of the groove than at the flat areas, and less at the lower corners, so oxidation decreases faster at the upper corners. It progresses slowly at the corner of
The corners are said to be rounded. However, high-temperature processing causes problems such as contaminants adhering to the surface diffusing into the substrate.

Sharp corners are a problem in many other device manufacturing processes. For example, a stacked capacitor is a capacitor made by stacking an electrode such as a polycrystalline silicon thin film on top of another element or element isolation region, oxidizing its surface, and then forming another electrode. In the lower electrode processed by RIE, etc., the radius of curvature at the upper corner is small, and if this is oxidized as is, the oxide film thickness at the corner will become thinner, similar to a trench capacitor, and the dielectric strength will decrease.
Leakage current increases.

Furthermore, in Ag wiring, wiring defects caused by stress, called stress migration, have become a serious problem. This is because the coefficient of thermal expansion of Ap is about 50 times that of the passivation film (SiO2), and after the passivation film is deposited, when the temperature drops from the deposition temperature to room temperature, a large tensile stress acts on 1, causing defects such as disconnection. It is something. If you look at the defective wiring, you will often find that the cracks are growing from the corners. That is, tensile stress tends to concentrate at the corners, and the smaller the radius of curvature, the more likely the stress will be concentrated and defects will occur.

Furthermore, when a contact hole is formed in the insulating film 82 on the substrate 81 by anisotropic etching such as RIE, as shown in FIG.
The side walls of contact hole 83 become vertical as shown in FIG.

For this reason, when filling the wiring material 84 with sorrel, ivy, etc., the inside of the contact hole 83 may not be completely filled, resulting in a cavity 85, as shown in FIG. 8(b). This is because the solid angle inside the contact hole 83 is small.
This is because there are fewer deposits to reach. Therefore, in order to facilitate embedding, it is necessary to widen the opening. Therefore, conventionally, the upper part of the insulating film 82 is etched wider than the mask 86 as shown in FIG. 8(e) by isotropic etching such as down-flow type plasma etching, and then as shown in FIG. 8(d). The insulating film 82 is completely etched by anisotropic etching such as RIE. However, since such a contact hole requires a complicated formation process and has sharp corners, there is a problem in that it is susceptible to defects such as disconnection due to electric field concentration.

Furthermore, in the trench capacitor and star-soaked capacitor described above, the electrode is oxidized to form a gate oxide film, but the flatness of the electrode surface becomes a problem at this time. First, in a trench capacitor, when a trench groove is formed by RIH, minute surface roughness may be observed on the sidewall. The cause of this is not clear, but it is thought that ion advance bombardment etc. contribute. In a stacked capacitor, since a polycrystalline Si thin film is used for the electrode, many crystal planes and grain boundaries appear on the surface. If the electrode surface has such irregularities, there is a risk that the density of surface states will increase at the interface between the gate oxide film and the electrode, leading to an increase in leakage current.

Furthermore, recently, multilayer wiring has been increasingly used to increase the degree of integration. At this time, the upper layer wiring is formed after covering the lower layer wiring with an insulating film, but since the insulating film has unevenness reflecting the underlying layer, it is necessary to flatten the insulating film before forming the upper layer wiring. Various methods have been considered for planarization, one of which is an etching back method in which a thick insulating film is formed and planarized by etching. However, simply etching does not make the surface flat, so a method is usually used in which a resist is applied to flatten the surface and the resist and insulating film are etched at the same time. Therefore, there is a problem that the number of steps increases and it takes a lot of time.

(Problem to be Solved by the Invention) Conventionally, when a stepped portion such as a trench groove, contact hole, or wiring is formed by anisotropic etching such as RIE, the radius of curvature of the corner portion becomes extremely small, and this steep The rough corners were a factor in degrading the performance of the device. Furthermore, when a trench is formed by RIE during the manufacture of a trench capacitor, minute irregularities occur on the inner wall, causing leakage current. This also applies to the surface of the Po1y Si thin film that is the electrode of the stud capacitor. Further, when forming multilayer wiring, the lower wiring is coated with an insulating film and then the insulating film is flattened, but it is necessary to apply a dry cyst and then perform etching, which is a complicated process.

The present invention has been made in consideration of the above circumstances, and its purpose is to easily round the corners of unevenness and steps, and to easily flatten the uneven surface. Surface treatment suitable for post-processing for forming grooves, contact holes, wiring, etc. The gist of the present invention is to perform dry etching while covering the surface of the substrate to be treated with a liquid that is inert to the etching species. The purpose of this method is to round off steep corners of stepped portions formed on the surface of a substrate, or to flatten the surface of a substrate to be processed that has minute irregularities or steps.

That is, in the present invention, after placing a substrate to be processed having irregularities or steps on its surface in a vacuum container, an etching gas and a gas inert to the etching species generated from the etching gas are simultaneously introduced into the container. The temperature of the substrate to be processed is maintained at a temperature at which an inert gas is liquefied by the pressure inside the vacuum container, and dry etching is performed while covering the surface of the substrate with a liquid that is inert to the etching species. This is a surface treatment method.

Through this process, sharp corners of stepped parts such as trenches dug in a single crystal silicon substrate, electrodes in a polycrystalline silicon thin film, wiring in a metal thin film, or contact holes opened in an insulating film can be rounded. This method flattens the surface of single crystal silicon, the surface of a polycrystalline silicon thin film, or the surface of an insulating film covering a wiring layer, which has been roughened by a dry etching process or the like, such as minute irregularities or steps.

(Function) According to the present invention, when performing dry etching, the liquid inert to the etching species coats the surface of the concave corners more thickly than the flat parts, and the convex corners coats the surface thinner than the flat parts. Since this liquid suppresses etching, etching is slower at concave corners than at flat corners and faster at convex corners, resulting in sharp corners being rounded. When a capacitor is fabricated by forming an insulating film such as a gate oxide film on the groove of a Si substrate with rounded corners or on the surface of a thin polycrystalline silicon film, the thickness of the insulating film is uniform, so it is Electric field concentration occurring at the corners is also alleviated, and properties such as dielectric breakdown voltage are improved.

Furthermore, when metal wiring is covered with an insulating film, stress is generated due to a difference in coefficient of thermal expansion between the insulating film and the wiring, but in the past, this stress was concentrated at the corners and caused wire breakage. However, in the above method, when the corners are rounded, stress concentration is alleviated, so wiring defects such as wire breakage do not occur.

Further, when forming a contact hole by opening an insulating film, sharp corners caused by anisotropic etching such as RIE can be rounded, thereby reducing disconnection defects. Furthermore, R
When an inert liquid is formed on the surface as described above during IE, the sidewall becomes tapered, so a contact hole that can be easily filled with wiring material can be formed by one etching.

Further, according to the present invention, when performing dry etching, the concave portions on the surface are thickly covered with a liquid inert to the etching species, whereas the convex portions are hardly covered. is selectively etched, and as a result, the unevenness gradually disappears and the surface becomes flat.

After flattening the surface of a single-crystal silicon or polycrystalline silicon thin film using the above method, an insulating film such as a gate oxide film is formed to fabricate a capacitor, resulting in low leakage current due to the low density of surface states. A capacitor is obtained. In addition, in multilayer wiring, after covering the lower wiring layer with an insulating film, another wiring layer is formed on the insulating film, but the surface of the insulating film is usually uneven, reflecting the underlying layer, and the upper wiring layer is coated with an insulating film. These irregularities must be flattened before forming the layer. By using the above method, these unevenness can be flattened, making it easier to form multilayer wiring.

(Embodiments) First, before describing embodiments, the basic principle of the present invention will be explained with reference to FIGS. 1 to 3.

Figures 1(a) and 2(a) show grooves in single crystal silicon formed by anisotropic etching such as RIE, wiring or stepped portions in polycrystalline silicon, metal, and metal silicide thin films, etc. Indicates a sharp corner. FIG. 1(a) shows a convex corner 11, and FIG. 2(a) shows a concave corner 21. Such a corner 11
, 21 on the surface is placed in a vacuum container,
When a gas inert to the etching gas and the etching species is introduced and the sample temperature is maintained at a temperature at which the inert gas becomes a liquid, if the liquid and the substrate surface are well wetted, the corners of the unevenness will be As shown in FIG. 2(b) and FIG. 2(b), it is covered with liquid 12.22.

In other words, when wetting is poor, the liquid gathers and forms droplets due to the cohesive force of liquid molecules, but when the adhesion between the liquid and the surface is large and wetting is good, the liquid spreads over the surface, and at the corners, the surface tension is reduced. Therefore, it is thicker in concave areas and thinner in convex areas. If dry etching is performed in this state, the thicker the liquid formed on the surface, the fewer etching molecules will reach the sample surface, and the removal of etching products will be suppressed, resulting in slower etching. Therefore, etching progresses more slowly on concave corners that are thickly coated with liquid than on flat areas, and faster on convex corners that are thinly coated, as shown in Figure 1 (C).
, concave as shown in Figure 2(C).

The convex corners 11.21 are rounded together.

Next, FIG. 3(a) shows unevenness 31 on the surface of a monocrystalline silicon or polycrystalline silicon thin film that has been etched and roughened by RIE or the like, or on the surface of an insulating film where a wiring layer has been overturned and a step has been created. . After placing a sample having a surface with such an uneven surface 31 in a vacuum container, a gas inert to the etching gas and etching species is introduced, and the sample temperature is maintained at a temperature at which the inert gas turns into a liquid. However, when dry etching is performed, the concave portions are covered thickly and the convex portions are thinly covered by the liquid 32, as shown in FIG. 3(b), based on the same principle as explained above.

For this reason, the convex portions are selectively etched as shown in Fig. 3 (C
), the unevenness becomes smaller, and the surface is finally flattened as shown in (d) of the same figure.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a schematic diagram showing a dry etching apparatus used in the embodiment method of the present invention. In the figure, 41 is a vacuum container, and inside this container 41 is a parallel flat plate 78t! lI! 42
a, 42 b are stored. High frequency power from a high frequency power source 44 is applied to the lower electrode 42b side on which the substrate 43 to be processed is mounted, and the reaction gas is introduced into the gas inlet 45b,
Reactive ion etching can be performed by supplying from 45c. Further, one end of a discharge tube 47 coupled to a microwave power source 46 is connected to the gas inlet 45a, and radicals generated by discharge can be introduced into the container 41 for etching.

The gas introduced into the container 41 is discharged from the gas outlet 48. Further, numeral 49 in the figure is a cooling device, which is capable of lowering the temperature of the substrate to be processed to -150°C.

Next, a method for manufacturing a trench capacitor will be described as a first embodiment of the present invention. FIG. 5 shows a schematic diagram of the manufacturing process.

First, as shown in FIG. 5(a), an oxide film 52 with a thickness of 6000 layers is formed on a silicon substrate 51, and this oxide film 52
After processing by RIE, RIE was further performed using the oxide film 52 as a mask to form a film with a width of 1 μm.

A groove 53 with a depth of 3 μm was formed. Note that the apparatus shown in FIG. 4 above was used for RIE. Thereafter, the wafer was treated with a hydrofluoric acid/ammonium fluoride buffer solution to remove the natural oxide film on the inner wall of the groove 53 and the mask oxidation 852.

Next, using the apparatus shown in FIG.
1F3 from gas inlet 35c 50atl1cm'/
400 V of microwave was applied to the discharge tube under conditions of a pressure of 5 Torr in the vacuum vessel 41 and a substrate temperature of -140° C. to etch the surface of the substrate for about 500 minutes.

As a result, both the upper and lower corners of the groove 53 were rounded, as shown in FIG. 5(b). The radius of curvature is 500 at the upper corner,
There were 1,000 people in the bottom corner. Further, the minute surface roughness and streaks observed on the inner wall immediately after RIE disappeared, and the inner wall became smooth.

Next, as shown in FIG. 5(c), As is applied to the inner wall of the groove 53.
Diffusion, concentration 5 x 102°c [3, depth 2000
A human n-type diffusion layer 54 was formed. Furthermore, Figure 5 (1)
), the surface of this n-type diffusion layer 54 is thermally oxidized,
After forming a gate oxide film 55 having a thickness of 150, phosphorus-doped polycrystalline silicon 56 was buried in the groove 53 to form an electrode.

The dielectric breakdown voltage of the gate oxide film was investigated using the trench capacitor formed through the above steps. As a result, 90% showed a dielectric breakdown voltage of 8 MY/ell1 or higher, which is the intrinsic breakdown voltage. However, when a capacitor was formed by dry etching using the cF47CCIF described above, the intrinsic breakdown voltage was only 30%.

That is, the above-mentioned surface treatment rounded the upper and lower corners and smoothed the inner wall surface, improving the dielectric breakdown voltage of the gate oxide film.

Next, a method for manufacturing an Ag alloy wiring will be described as a second embodiment of the present invention. FIG. 6 shows a sectional view of the manufacturing process.

First, as shown in FIG. 6(a), a silicon oxide film 62 is formed on a single crystal silicon 61, an Afi alloy film 63 with a thickness of 8000 is deposited by sputtering, and a 1 μm pattern is further formed on it. A resist mask 64 was formed. Next, the sample was placed on the apparatus shown in FIG. 4, and 75 SCCM of CN2 was supplied from the gas inlet 45a.
RIE was performed by introducing 25 SCCM of B C11 3, and the AfI alloy film 63 was selectively etched to form wiring as shown in FIG. 6(b). Then add oxygen to 110
05CC was introduced and the resist mask 64 was removed.

Next, Ar gas was introduced from the gas inlet 45a and discharged, thereby removing the oxide film on the surface of the Aρ alloy film 63. After that, introduce C(IFI 503CC)I and reduce the pressure inside the container by 503CC.
Torr and lowered the sample temperature to -100°C.
! F3 was liquefied on the sample surface. Subsequently, in addition to C(lF3), CD 2508CCM was introduced, and the heg alloy film 63
etched. As a result, the corners of the wiring were rounded as shown in FIG. 6(C). Furthermore, a passivation film (SiO2) 65 was deposited as shown in FIG. 6(d).

The occurrence of notches in the A, 17 wiring formed in the above steps was examined using an optical microscope. As a result, it was found that the notch occurrence rate was reduced to about 1710 by rounding the corners.

In other words, 1. Tensile stress caused by the difference in thermal expansion coefficient between the upper and lower oxide films of the AfI alloy wiring and the A1 alloy concentrates at the corners of the wiring and causes notch failure, but by rounding the corners, the stress is dispersed and the notch is formed. We were able to reduce wiring defects such as defects.

Next, an example of forming multilayer wiring as a third embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 7(a), a single crystal silicon substrate 7
After an insulating film 72 made of silicon oxide or the like is deposited on the substrate 1, a wiring layer 73 made of phosphorus-doped polycrystalline silicon, molybdenum silicide, tungsten, or the like is deposited. Next, Fig. 7 (b
), the wiring layer 73 is patterned by RIE, and then patterned with BPSG (boron,
The wiring layer 73 was covered with a phosphorus-doped silicon glass film 74.

Next, the sample was placed on the apparatus shown in FIG. 4, and CF 450SCCM was introduced from the gas inlet 35a.

CCΩ2F 250SCCM was introduced to maintain the pressure inside the vessel at 5 Torr. Furthermore, when the sample temperature was lowered to -100° C., CCR2F2 liquefied as shown in FIG. 7(d), and the concave portion was thickly covered with liquid 75 of CCfI2F2. In this state, the discharge tube 47 is discharged, and the generated F atoms are guided into the vacuum container and B P S Gll! Etched i74. As a result, the unevenness gradually decreases as shown in Fig. 7(e), and finally, as shown in Fig. 7(r) (B
The surface of the PSG film 74 was flattened.

Thus, according to the method of this embodiment, an uneven insulating film can be planarized in a single process.

Therefore, compared to the conventional method of applying a resist and etching back, the process is greatly simplified and there is an advantage that multi-layer wiring can be easily formed.

Note that the present invention is not limited to the embodiments described above. As the etching gas, gases used in normal dry etching can be used, and may be appropriately selected depending on the material to be etched. Similarly, the inert gas may be appropriately selected depending on the etching gas used, such as CF4. CCΩF,, CCΩ2F2. C.C.
Ω3F.

C2F6. C2F5 CN, C2F4 Cl12゜CC
(Ia, SFb, etc. can be used. In addition, the dry etching equipment used in the method of the present invention includes plasma etching, reactive ion etching, reactive ion beam etching, downflow type plasma etching, photoexcitation etching, etc. Can be used.

In addition, various modifications and applications can be made without departing from the gist of the present invention.

[Effects of the Invention] According to the present invention, steep corners of grooves in a single crystal silicon substrate, electrodes with a polycrystalline silicon film thickness, metal wiring, contact holes, etc. By performing dry etching while covering the surface with liquid, corners can be rounded to improve dielectric breakdown voltage and reduce wiring defects such as disconnections.

Further, according to the present invention, the surface of a thin polycrystalline silicon film, the surface of a single crystal silicon substrate that has been roughened through a dry etching process, etc., has minute irregularities, or the surface of an insulating film covering a wiring layer, etc. It is possible to flatten the surface with steps, reduce capacitor leakage current, and facilitate the formation of multilayer wiring.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views for explaining the present invention in detail, FIG. 4 is a schematic configuration diagram showing a dry etching apparatus used in an embodiment of the present invention, and FIG. 5 is a diagram showing the formation of a trench capacitor. 6 is a sectional view showing the process of forming an AΩ alloy interconnect, FIG. 7 is a sectional view showing the process of forming a multilayer interconnect, and FIG. 8 is for explaining the problems of the conventional method. FIG. 2 is a cross-sectional view showing the process of forming a contact hole. 11.21...Corner, 12,22.32...Liquid,
31... Uneven surface, 41... Vacuum container, 42a. 42b... Parallel plate electrode, 43... Substrate to be processed, 4
4...High frequency power supply, 45a, 45b...Gas inlet, 46...Microwave power supply, 47...Discharge tube,
48...Gas exhaust port, 49...Sample stand. Applicant's representative Patent attorney Takehiko Suzue (b) (b) (c) (c) Figure 1 Figure 2 (a) (b) (c) Figure 3 Figure 4 (c) (d) Figure 5

Claims (4)

[Claims] (1) A substrate to be processed with unevenness or steps formed on the surface is placed in a vacuum container, and an etching gas and a gas inert to the etching gas are introduced into the container to inert the substrate to be processed. A surface treatment method characterized by etching the surface of a substrate to be processed while keeping the temperature in a range where the inert gas liquefies under the partial pressure of the gas and covering the surface of the substrate with an inert liquid. (2) A semiconductor substrate with trench grooves formed on its surface is placed in a vacuum container, and an etching gas and an inert gas to the etching gas are introduced into the container. The corner portion of the trench groove is rounded by etching the surface of the semiconductor substrate while covering the surface of the semiconductor substrate with an inert liquid while maintaining the temperature in a range where the inert gas liquefies under pressure. Surface treatment method. (3) A substrate to be processed with a wiring pattern formed on its surface is placed in a vacuum container, an etching gas and a gas inert to the etching gas are introduced into the container, and the substrate to be processed is placed in an inert gas. The corners of the wiring pattern are rounded by etching the surface of the substrate to be processed while covering the surface of the substrate with an inert liquid while maintaining the temperature in a range where the inert gas liquefies under a partial pressure of Characteristic surface treatment method. (4) A substrate to be processed having an uneven surface is placed in a vacuum container, an etching gas and a gas inert to the etching gas are introduced into the container, and the substrate to be processed is placed under a partial pressure of the inert gas. The uneven surface is planarized by etching the surface of the substrate to be processed while covering the surface of the substrate with the inert liquid while maintaining the temperature in a range where the inert gas liquefies. Characteristic surface treatment method.