JPS61232636A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form flat insulating films having high reliability by making a first deposition process, in which the insulating film is shaped, a resist applying process, in which a resist film is formed onto the insulating film, a flattening process, in which the projecting film of the insulating film is removed together with a resist film and the surface is flattened, and a second deposition process, in which the insulating film is deposited, to be contained. CONSTITUTION:A PSG insulating film 3 is formed through a normal pressure CVD method, the viscosity of polymethyl methacrylate is adjusted, and a resist layer 4 having a flat surface is shaped through wet-on-wet coating by spin coating. The resist layer 4 and the projecting sections of the PSG insulating film 3 are removed through etching by reactive ion etching using tetrafluoromethane to shape the PSG insulating film 3 having a flat surface. The surface layer of the PSG insulating layer is etched slightly to remove a surface contamination layer, a defect layer, etc., and a PSG insulating film 5 is deposited through the normal CVD method. A contact hole 6 is bored to the flat PSG insulating film formed, and a second wiring pattern 7 is shaped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an interlayer insulating film.

[Prior Art and Its Problems] With the progress of semiconductor technology, the integration of semiconductor devices including very large scale integrated circuits (VLSI) has been increasing. BACKGROUND ART High integration of semiconductor devices is achieved through miniaturization of elements, so techniques for forming fine and highly accurate patterns are attracting attention.

Generally speaking I! I! In LsT, the irregularity of the wiring increases the amount of space on the wiring surface, and multilayer wiring technology is essential to alleviate this problem. In multi-layer wiring technology, electrical insulation is applied to predetermined areas between each element area formed in the substrate and the first layer wiring pattern, and between wiring patterns to provide electrical insulation.・The formation of an insulating film that electrically connects the patterns of different layers through the holes to contact 1 with the 'T' hole plays an important role, which contributes to the miniaturization and yield improvement of semiconductor devices with multilayer wiring. To improve,
As will be described later, flattening technology for the surface of the insulating film and contact 1
-The formation technology is changing, especially important point 1-.

That is, in order to achieve complete insulation, it is necessary to cover the level difference in the underlayer and form it thick enough to prevent conduction due to pinballs. However, the thicker the culm, the more difficult it becomes to form contact holes (through holes).
Advanced contact forming technology becomes necessary.

In addition, in order to miniaturize the wiring pattern formed in the L layer and improve the yield, it is necessary to use a photomask in the photolithography process for pattern formation, from the viewpoint of film formation for the wiring layer. There is a strong demand for flattening of the insulating layer also from the aspect of pattern transferability.

Therefore, a planarization method using a reflow method and a method using an organic material such as polyimide resin as an insulating film have been proposed.

In the reflow method, for example, a phosphosilicate glass (PSG) film is formed and then heated and melted to flatten the surface.This method requires high-temperature treatment. In a device having an impurity diffusion layer, the impurities in the impurity diffusion layer are diffused again due to heat and the junction depth becomes deeper. Therefore, in an ultra LSI device with a channel length of 2 μm or less, a short channel is required. Problems arise with effectiveness. In addition, in the case of a device including an aluminum wiring layer, there are problems such as an interfacial reaction between the aluminum in the wiring layer and the silicon substrate, which causes hillocks and breakdown of the bond, and therefore the reflow method cannot be applied.

Therefore, after forming an insulating film made of an inorganic material such as a silicon dioxide film, the uneven surface is flattened with a resist, dry etching is performed under etching conditions such that the resist and the insulating film have the same etching rate, and the insulating film is etched. A method of flattening the convex portion of the film by edge-backing it together with Regime 1- is attracting attention.

However, when attempting to flatten the surface by applying a resist, it was necessary to form a single layer of resist I which is quite thick.

By the way, the thicker the resist layer I is coated, the longer the resist layer that must be removed in the etching process has a thickness of <4, so the time required for etching becomes longer. There have been problems such as contamination and deterioration of film quality due to pinholes, resulting in a drop in breakdown voltage.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a flat and highly reliable insulating film.

[Means for Solving the Problems] Therefore, the present invention provides a JFT deposition process for forming an insulating film with a flat surface on an uneven substrate surface by chemical vapor deposition (CVD). This process is divided into two processes: planarization using an etch-back method and a film thickness control process. a flattening step of removing the convex portions of the insulating film together with the resist film by dry etching to flatten the surface; and a second deposition step of depositing the insulating film again. I'm here.

Preferably, the resist coating process is repeated twice, and after the flattening process and prior to the second deposition process, a surface cleaning process using a wet etching method is performed.

[Operation] That is, after an insulating film is formed by CVD on a surface including steps due to the presence of a wiring layer pattern, etc., a high viscosity resist is first applied to the insulating layer, and then a low viscosity resist is applied. By this method, a resist layer with a minimum thickness and a flat surface is formed. By this second regeneration 411 method, conventionally 1.5 to 2.0 μmff
The resistor layer required once is significantly reduced by 1 to 1.2 μ7n.

Then, the convex portions of the insulating film are removed together with the resist layer by anisotropic dry etching such as reactive ion etching under conditions such that the etching rate of the first layer of the regimen and that of the insulating film are the same, and the etching rate of the insulating film before etching is removed. To obtain a flat insulating film surface that maintains the flat surface shape as it is. At this time, since the thickness of Regime 1 to layer is kept to a minimum, (1) the etching time is short, and etching can be performed with good workability without deteriorating the film quality of the insulating film.

After that, a surface cleaning treatment is performed to remove substances generated or attached to the surface due to etching pressure, etc.
Furthermore, the insulating film is grown again using the CVD method or the like until it reaches a desired thickness.

In this way, a highly reliable insulating film with good film quality and 1:1 flatness is formed, with the amount of etchback being minimized.

Note that this method is particularly effective when etching back an insulating film formed using the atmospheric pressure CVD method.

In other words, when attempting to planarize using the conventional edge back method, the insulating film must be formed thicker by the amount of edge back. The more <11 is multiplied, the larger the step becomes. Therefore, it is necessary to apply the same amount thicker to Regime 1, and the amount of etchback increases. Therefore, in the method of the present invention, the insulating film deposition step is divided into two steps. In the first step, a relatively thin insulating film is formed for the sole purpose of forming a flat surface, and in the second step,
Since the film thickness is adjusted, the amount of etchback can be significantly reduced and deterioration in film quality can be prevented.

[Example] Hereinafter, a method for forming a wiring layer according to an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(f) are diagrams showing the process of forming a wiring layer.

First, as shown in FIG. 1(a), on a silicon substrate 1 on which a predetermined element rt region (not shown) is formed, an aluminum film containing 3% silicon is sputtered using a normal sputtering method.
After forming a cum layer (AQ-8i 3%) to a film thickness of 0.9 times and 1 m, a first wiring pattern 2 is formed by a lithography process.

Next, as shown in FIG. 1(b), a PSG insulating film 3 having a thickness of 1.2 μm is formed by atmospheric pressure CVD. The substrate humidity at this time is 400°C.

Then, adjust the viscosity of polymethyl methacrylate-1 to (PMMA) to be 4 to 5 CP, apply it to a thickness of about 0.9 μm by spin coating, and apply it to a thickness of about 0.9 μm between the first wiring patterns. Fill in the bone. Next, the viscosity of polymethyl methacrylate (PMMA) was adjusted to about 40 CP, and the viscosity of polymethyl methacrylate (PMMA) was similarly adjusted to about 0.2 CP by spin coating.
The layer 4 is coated to a thickness of 1.0 mm to form a layer 4 on the resist 1 having a flat surface, as shown in FIG. 1(C).

After this, layer 4 and P of resist 1 are etched by reactive ion etching using Te1 to Rafluoromethane (CF4).
Etching is performed under conditions such that the etching rate of the SG insulating film 3 is approximately equal, and the resist layer 4 and the PS insulating film 3 are etched.
By removing the convex portion of the G insulating film 3, the structure shown in FIG. 1(d) is obtained.
As shown in FIG. 2, a PSG insulating film 3 with a flat surface is formed.

At this time, the etching conditions were Te 1 to Rafluoromethane 50 (SCCM) and Oxygen 10 (SCCM).
), the etching pressure was 40 Pa, the power was 350 W, and the ion energy was set to 150 eV. In this way, in this step, by adding oxygen, C, F, CF2. COF2
Oxygen plasma is used to prevent such polymers from adhering to the substrate surface, and the ion energy is suppressed to about 1500V to prevent deterioration of the PSG insulating film. By the way, Figure 2 shows the oxygen content in the tetrafluoromethane atmosphere (horizontal axis) and etching rate (vertical axis).
Indicates the relationship between A is a curve showing the etching rate of the PSG insulating film, and b is a curve showing the etching rate of polymethyl methacrylate.

Furthermore, this silicon substrate 1 is treated with salt 1ti(Hcll)+
After immersing in a mixture of hydrogen peroxide (H2O2) to remove etching products, carbon, fluorine, and mixtures thereof, PSG was immersed in dilute hydrofluoric acid for approximately 100-200 A.
By lightly etching the surface layer of the insulating film, surface contamination layers, defective layers, etc. are removed.

Thereafter, a PS'G insulating film 5 of approximately 1 μm is deposited by atmospheric pressure CVD as shown in FIG. 1(e). At this time, the substrate temperature is 400°C.

For the flat PSG insulating film formed in this way,
Drill a contact hole 6 in the usual manner (see Fig. 1).
As shown in f), a second wiring pattern 7 is formed.

The PSG insulating film formed in this way is flat, has good film quality, and is highly reliable, so it does not cause breaks in the second wiring pattern or insulation defects. , a highly reliable semiconductor device can be obtained.

In the examples, polymethyl methacrylate was used as the regimen, but it is not necessarily limited to this, and any organic resist may also be used.

Although normal pressure CVD was used to form the insulating film, other methods such as low pressure CVD and plasma CVD may also be used, especially when forming the insulating film after planarization etching. It is desirable to form a denser film by low pressure CVD or the like.

Furthermore, it goes without saying that the insulating film can also be applied to a PSG insulating film, a silicon oxide film (SiO2), a silicon nitride film (Si3N, etc.).

[Effects] As described above, according to the present invention, there is a step of flattening the deposited T culm of the insulating film by an edge-back method after the deposition, and a step of flattening the deposited T culm of the insulating film by applying 1(f product) on the flat insulating film. In addition to dividing the film thickness into two steps, the process from Regime 1 through the etch-back method to the coating process is sequentially overcoated using a highly viscous resist to achieve the minimum film thickness that does not enlarge the step shape. Since the surface of the first insulating film stacked with Jl is flattened by layer 1 to the minimum film thickness by overcoating, the amount of edgeback is significantly reduced and the film quality is improved. By forming a flat first insulating film without causing deterioration and further forming a second insulating film of a desired thickness on top of this, a flat and highly reliable insulating film can be formed extremely efficiently. Formation becomes possible.

[Brief explanation of the drawing]

1(a) to 1(f) are process explanatory diagrams showing a method for forming a wiring layer according to an embodiment of the present invention, and FIG. 2 shows an etching rate (tetra FIG. 3 is a diagram showing the relationship between the addition of oxygen to a fluoromethane atmosphere and the etching rate. 1... Silicon substrate, 2... First wiring pattern,
3...PSG insulation, 4...resist layer, 5...
PSG insulating film, 6... contact hole, 7... second wiring pattern. Figure 1 (CI) Figure 1 (b) Figure 1 (C) Figure 1 (d) rryi, 7.13 Figure 1 (e) Figure 2! Multi 1200'-waten (A/m1n) 2 4 6 8 T.

Claims (4)

[Claims] (1) The step of forming an insulating film on the surface of a substrate having steps includes a first deposition step of forming an insulating film by chemical vapor deposition (CVD), and a resist with a flat surface on the insulating film. a resist coating step to form a layer; a flattening step to flatten the surface by removing the convex portions of the insulating film together with the resist layer by dry etching; and further depositing the insulating layer until a desired thickness is achieved. A method for manufacturing a semiconductor device, comprising a second deposition step. (2) The method of manufacturing a semiconductor device according to claim (1), wherein the resist coating step includes a step of overcoating using resists having higher viscosity in sequence. (3) The semiconductor according to claim 1 or 2, further comprising a surface cleaning step by wet treatment after the planarization step and prior to the second deposition step. Method of manufacturing the device. (4) The method for manufacturing a semiconductor device according to any one of claims (1) to (3), wherein the first deposition step is a step using an atmospheric pressure CVD method.