JPH0336727A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent breakdown strength of a PE-PSG film from deteriorating and shape failure of a through-hole formed on this PE-PSG film from being generated by eliminating a lamination layer which is accumulated on the surface in the case of etch-back process of a spin-on glass film by etching and by forming a phosphor silicate glass film on the surface by plasma CVD growth. CONSTITUTION:A phosphor silicate glass film PE-PSG film 3 is formed on the surface of a semiconductor substrate 1 where an Al wiring layer 2 is formed by plasma CVD growth. Then, a spin-on glass film(SOG) is coated, thus forming an SOG film 3 by plasma CVD growth. Then, the spin-on glass(SOG) is coated, thus forming an SOG film 4 with nearly a flat surface. Then, the SOG film 4 is etched back by reactive ion etching for flattening the surface. At this time. the PE-PSG film 3 on the Al wiring layer 2 is also etched under the condition where the SOG film 4 is nearly equal to the PE-PSG film 3, thus exposing the upper surface of the Al wiring layer 2. At this time, an accumulated layer 7 on the surface by etching back is eliminated by reactive ion etching. Finally, the PE-PSG film 6 is formed by the same conditions.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the process of forming a glabella insulating film, etc. with a flat surface on a wiring pattern, etc. in a method of manufacturing a semiconductor device, a spin-on glass film (hereinafter abbreviated as SOG film) is proposed. When a silicate glass film (hereinafter abbreviated as PH-PSG film) is formed by plasma-enhanced CVD growth after etching back and flattening the PE-PSG film, breakdown voltage deterioration of the PE-PSG film and this PIl! - Forming an insulating film on the surface of a semiconductor substrate on which a convex pattern is formed, with the aim of providing a method for manufacturing a semiconductor device that can prevent defects in the shape of through holes formed in a PSG film. a step of forming a spin-on glass film on the surface of the insulating film, and etching back the spin-on glass film to planarize it;
- Etching and removing the deposited layer deposited on the surface during the etch-back process of the spin-on glass film described above [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a wiring layer. This invention relates to improvements in the planarization process.

As the wiring layers of ultra-large integrated circuit devices become finer and multilayered, the importance of planarization processes such as SOG film etch-back methods for flattening the surface of semiconductor substrates is increasing.

In the multilayer planarization process, a phosphorus silicate glass film (hereinafter abbreviated as PSG film) is formed on the surface of this SOG film, which can be grown at a low temperature, and the high wave power output, distance between electrodes, etc. can be changed. PE-PSG films formed by plasma CVD, which can control stress, have become widely used, but a contamination layer is formed on the surface of the SOG film in the etch-back process of this SOG film, and this contamination layer is A problem has occurred in which PE-PSGlli deteriorates, which is thought to be due to

Under the above circumstances, there is a need for a method of manufacturing a semiconductor device that can prevent deterioration of a PH-PSG film during the planarization process of a semiconductor substrate.

[Conventional technology]

A conventional method for manufacturing a semiconductor device will be explained step by step with reference to FIG.

First, as shown in FIG. 2 (ω), on the surface of the semiconductor substrate 11,
An aluminum wiring layer 12 (hereinafter abbreviated as Al wiring layer) is formed by patterning an aluminum layer formed by sputtering.

Next, as shown in FIG. 2 (b), A1. A PH-PSG film 13 is formed by plasma CVD growth on the surface of the semiconductor substrate 11 on which the wiring layer 12 is formed.

Then, as shown in FIG. 2(C), SOG is applied to form an SOC film 14 with a substantially flat surface.

Next, etchback is performed by active ion etching under the following conditions to flatten the surface as shown in FIG. 2(d).

At this time, the PH on the Af wiring layer 12 is adjusted under the condition that the etching rate of 4E-PSG@L3 on the SOG film 1 is almost equal.
- The PSG film 13 is also etched, and A1. This process is continued until the upper surface of the wiring layer 12 is exposed.

Finally, as shown in FIG. 2(e), a PE-PSG film 16 is grown by plasma CVD as in the step of FIG. 2(b).
Form a layer approximately 5,000 thick.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above,
A SOG film is formed to flatten the Al wiring layer, and after etching back the SOG film, File-PSG is formed on the surface.
However, when etching back this SOG film, a carbon or fluorine-based deposited layer is generated, which may cause deterioration of the withstand voltage of the PE-PSG film formed on the surface, or the growth conditions of the PH-PSG film, Even though the rIi length rate and phosphorus concentration were kept constant, the etching rate of the grown PH-PSG film increased abnormally at the bottom of the film.
There is a problem in that when a through hole is formed in a film, the shape of the through hole is defective.

Due to the above situation, PE-psc formed on this surface
The object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent deterioration of the breakdown voltage of the film and defects in the shape of through holes formed in this PH-PSG film.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming an insulating film on the surface of a semiconductor substrate on which a convex pattern is formed, forming a spin-on glass film on the surface of the insulating film, and etching the spin-on glass film into an etch bank. a step of flattening the
M is deposited on the surface during the etch bank process of the spin-on glass film [action] That is, in the present invention, it is deposited on the surface of the semiconductor substrate on which a convex pattern such as the A1 wiring layer is formed! ! An I edge film is formed, an SOG film is formed on the surface of this insulating film, and the SOG film is etched back to planarize the surface.

Furthermore, the deposited layer formed on this surface is removed by etching, and a PE-PSG film is formed on the surface by plasma CVD growth using thermal CVD growth. If a PR-PSG film is formed by plasma CVD growth after removing the deposited layer in this way, defects in the shape of through holes due to breakdown voltage deterioration of the PSG film or abnormal increase in etching rate will not occur, and in addition, PE-PSG by plasma CVD growth
If a film is formed, stress control can be performed well.

These abnormalities and defects occur because the carbon or fluorine-based deposited layer formed on the surface of the SOG film by etchback is activated in the plasma state of PSG plasma CVD growth and is transferred to the growing PR-PSG film. This is thought to be because they are taken in as impurities, resulting in poor film quality of the PE-PSG film at the growth interface.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained in order of steps with reference to FIG.

First, as shown in FIG. 1(a), an aluminum layer with a thickness of approximately lμ is formed on the surface of a semiconductor substrate 1 by sputtering, and the aluminum layer is buttered to form an AA wiring layer 2.
form.

Note that an insulating film is formed in advance on the surface of the substrate on which the wiring layer 2 is to be formed.

Next, as shown in FIG.
The SG film 3 is formed by plasma CVD growth under the following conditions.

Gas type and flow rate Silane (SiH4) ------------
305ecta nitrous oxide (NtO) -800sec
m-phosphine (PH3) (12) --------
= 900 sccm Reaction chamber pressure - 3 Torr High frequency power supply frequency - 13,56 MHz High frequency power supply output density - 1 - 2 W/cf
fl susceptor temperature -400''C Then, as shown in FIG. 1C, SOG is applied to form an SOG film 4 with a thickness of approximately 5000 mm and a substantially flat surface.

Next, the SOG film 4 is etched back by active ion etching under the following conditions to flatten the surface as shown in FIG. 1(a).

Gas type and flow rate Diflon C-318 (C, P,) 705
cca carbon tetrafluoride (CFa) --- 800
sec■Reaction chamber pressure 0.2 Tor
rHigh frequency power supply frequency -=-13,56MH2 High frequency power supply output density I W/cd At this time, under the condition that the SOG film 4 and the PH-PSG film 3 have approximately the same etching speed, /l PE-PSG film 3 on the wiring N2 Also etching ＼Af! , until the upper surface of the wiring N2 is exposed.

The deposited layer 7 deposited on the surface by this etchback is shown in Figure 1 (
As shown in e), it is removed using oxygen (0□) gas or by active ion etching.

The etching conditions are as follows.

Gas flow rate ・---500sec Reaction chamber pressure 0.03 Torr High frequency power supply frequency 13.56 MHz High frequency power supply output density I W/d Etching time
At the end of 100 seconds, the first
A R-PSGSbO2 film having a thickness of about 5,000 layers is formed under the same conditions as in the process shown in FIG. 3(b).

Incidentally, a through hole is formed in the PE-PSGSbO2 psc film 5 by etching, and an upper layer A1 wiring layer is formed.

In this way, after the etch-back process of the SOG film 4, the SO
PE-PSGSb is formed in the step of FIG. 2(f) by etching away the deposited layer formed on the surface of the G film 4.
This Pl! is prevented from coming into contact with the O2 deposit layer.
- It is possible to prevent PSGSbO2 pressure defects and through-hole shape defects from occurring.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, SOG
After the film etch-back process, the deposited layer formed on the surface is removed by etching, so it is possible to prevent the PH-PSG film formed after the SOG film etch-back from having poor breakdown voltage or poor through-hole shape. It is possible to provide a method for manufacturing a semiconductor device that can be expected to significantly improve reliability.

[Brief explanation of drawings]

FIG. 1 is a side cross-sectional view showing an embodiment of the present invention in order of steps, and FIG. 2 is a side cross-sectional view showing a conventional method for manufacturing a semiconductor device in order of steps. In the figure, 1 is a semiconductor substrate, 2 is an Af wiring layer, 3 is a PH-PSG film, 4 is an SOG film, and 6 is a PIE-PSG film. Suimei IZ with water! , Ru-thing (Meji child) 1st order in n order: Showing news side Rokugo I + 21 (Part 1)' σ) = 2 Sea * Direction = Shiiteri 1L
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Claims (1)

[Claims] A step of forming an insulating film (3) on the surface of the semiconductor substrate (1) on which the convex pattern (2) is formed, and forming a spin-on glass film (4) on the surface of the insulating film (3). and etching back and planarizing the spin-on glass film (4); etching away the deposited layer deposited on the surface during the etch-back process of the spin-on glass film (4); A phosphorus silicate glass film (6
) A method for manufacturing a semiconductor device, comprising the step of forming a