JPH01251664A - Field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the capacitance between gate and source, and the capacitance between gate and drain, without fining gate length, and enable the title transistor to be applied in a high frequency region, by forming a low carrier concentration region with a shallow depth from a surface, in a region of an active layer just under the gate, and in the vicinity thereof. CONSTITUTION:In an active layer 2 just under a gate, a low concentration region 5, where carrier concentration of the active layer 2 is decreased, is formed. The depth of the low concentration region 5 is desirable to be nearly equal to the thickness of a surface depletion layer at the time of gate zero bias. Since the low concentration region 5 of carrier is formed only in the active layer 2 just under the gate electrode 6, and in its vicinity, capacitance between gate and source, and capacitance between gate and drain can be reduced without fining the gate length. Further, since the depth of the low concentration region 5 is made equal to the depth of the depletion layer at the time of gate zero bias, the region is made as a complete depleted state at an operating point when the gate bias is applied, so that mutual conductance is never sacrificed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor used in a high frequency band.

[Conventional technology]

Conventionally, a field effect transistor used in a high frequency band is formed by forming an active layer (n-type active layer) 2 on the main surface of a semiconductor substrate 1 and covering the surface with an insulating film 3, as shown in FIG. A gate electrode 6 is formed through the opened window 4, and a drain electrode 7 and a source electrode 8 are formed on both sides of the gate electrode 6.

In this case, the carrier concentration of the active layer 2 is uniform not only directly under the gate and in its vicinity, but also over the entire channel region between the drain and source. Furthermore, a structure in which the concentration is low in a region shallow from the surface of the active layer 2 has been proposed, but even in this case, the concentration is uniform in the channel region between the drain and the source.

[Problem to be solved by the invention]

In the conventional field effect transistor described above, the carrier concentration is uniform throughout the channel region, so the gate and
Source-to-source capacitance and gate-drain capacitance increase,
Difficult to use for high frequencies. In order to reduce this capacitance, it is necessary to shorten the gate length, which requires microfabrication, which leads to a decrease in manufacturing yield.

In this case, as described above, it is possible to reduce the capacitance by lowering the concentration in the shallow region from the surface of the active layer 2, but this will greatly expand the surface depletion layer around the gate and cause the source to narrow due to channel narrowing. This causes an increase in resistance and drain resistance, resulting in deterioration of characteristics.

An object of the present invention is to provide a field effect transistor in which each capacitance between the gate and source and between the gate and drain can be reduced without sacrificing characteristics or manufacturing yield.

[Means to solve the problem]

The field effect transistor of the present invention has a gate, a drain,
A low carrier concentration region is formed shallowly from the surface directly under and in the vicinity of the gate of the active layer forming the source.

In this case, the low concentration region is preferably formed to a depth approximately equal to the thickness of the surface depletion layer at zero gate bias.

[Function] In the above configuration, the gate length can be increased without making the gate length minute due to the low concentration region directly under the gate and in its vicinity.
The source-to-source and gate-drain capacitances can be reduced, and the expansion of the depletion layer is prevented, thereby suppressing increases in source resistance and drain resistance.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, on the main surface of which an n-type active layer 2 is formed by ion implantation technology or various epitaxial techniques. Then, an insulating film 3 is formed on the surface of the substrate,
A gate electrode 6 is formed through a window 4 formed in this insulating film 3, and a drain electrode 7 and a source electrode 8 are formed on both sides of the gate electrode 6.
are formed respectively. Further, a low concentration region 5 in which the carrier concentration of active N2 is lowered is formed in the region directly below the gate of the active layer 2.

The low concentration region 5 is formed into an n-type region by, for example, implanting p-type compensation ions into the active layer 2 at the time when the window 4 is opened in the insulating film 3. Note that this low concentration region 5 is preferably formed to a depth approximately equal to the thickness of the surface depletion layer at zero gate bias.

According to this configuration, since the low concentration region 5 of carriers is formed only directly under and in the vicinity of the gate electrode 6, the active N2 can be formed between the gate and the source and between the gate and the drain without making the gate length minute. It becomes possible to reduce the capacity of. Furthermore, since the depth of this low concentration region 5 is made equal to the depth of the surface depletion layer at zero gate bias,
At a certain operating point with gate bias applied, the region is fully depleted and the transconductance (
gm) will not be sacrificed. Furthermore, the low concentration region 5
Since this is only directly under and in the vicinity of the gate, it is possible to prevent the surface depletion layer from expanding significantly, and to prevent increases in source resistance and drain resistance due to channel narrowing.

This allows the transistor to be used in a high frequency band without deteriorating its characteristics, and prevents a decrease in manufacturing yield.

FIG. 2 is a sectional view of another embodiment of the present invention, and the same parts as in FIG. 1 are given the same reference numerals.

In this embodiment, a recess (concave portion) 9 is formed in the substrate surface of the gate electrode 6, and the source/drain current is adjusted by this. In this example as well, a low carrier concentration region 5 is formed directly under and in the vicinity of the gate electrode of the active layer 2 to reduce the capacitance between the gate and source and between the gate and drain.

[Effects of the Invention] As explained above, in the present invention, a low carrier concentration region is formed shallowly from the surface directly under the gate of the active layer and in its vicinity. It is possible to reduce the capacitance between the source and the gate and drain, and also prevent the expansion of the depletion layer, suppressing the increase in source resistance and drain resistance, enabling use in high frequency bands and preventing deterioration of characteristics. Moreover, it has the effect of improving manufacturing yield.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a sectional view of another embodiment of the invention, and FIG. 3 is a sectional view of a conventional structure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Active layer, 3... Insulating film, 4... Window, 5... Low carrier concentration region, 6...
Gate electrode, 7...Drain electrode, 8...Source electrode, 9...Recess. Figure 1 Figure 3

Claims (1)

[Claims] 1. In a field effect transistor in which a gate, drain, and source are formed on an active layer formed on a semiconductor substrate, a low carrier concentration region is formed shallowly from the surface of the active layer directly under the gate and in the vicinity thereof. Characteristics of field effect transistors.