JPH01251151A - Bus extension adaptor - Google Patents

Abstract

PURPOSE:To reduce the load of a basic system bus by decreasing the output frequency of memory read requests to the basic system bus from a channel device connected to an extension system bus. CONSTITUTION:A channel device 17 under the control of a bus extension adaptor 19 carries out its original memory reading job by the instruction of a channel control block CCB by using a basic system bus 15 in a low priority order under the control of a microcomputer 23 of the adaptor 19. This read data is stored in a memory data buffer 20. Then a memory read request MR0 is sent from the device 17 instructed for a memory reading job via the CCB. Thus the read data is taken out of the buffer 20 and sent back to the requester device 17. In this case, it is inhibited to send the request MR0 to the bus 15 as a memory read request MR1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bus expansion adapter used for expanding a system bus.

(Prior Art) Systems have been known in which a system bus is expanded using a bus expansion adapter. In this type of system, the channel devices connected to the system bus of the expansion part, that is, the expansion system bus under the bus expansion adapter, and the channel devices connected to the original system bus (basic system bus) are generally Considering the objective (
(from the software perspective), memory requests output from channel devices connected to the expansion system bus to the expansion system bus are transmitted to the basic system bus by the bus expansion adapter. Therefore, the channel device connected to the expansion system bus can perform human output control between the main memory and the external storage device as if it were connected to the basic system bus.

(Problem to be Solved by the Invention) When the system bus is expanded using a bus expansion adapter as described above, channel devices connected to the expanded system bus are treated in the same way as channel devices connected to the basic system bus. As a result, memory requests from the expansion system bus occur frequently, resulting in a heavy load on the system bus, resulting in wait times occurring everywhere, resulting in a reduction in system throughput.

Therefore, the present invention enables normal input/output control of this type of channel device without transmitting memory read requests from channel devices connected to the expansion system bus to the basic system bus, thereby reducing the load on the basic system bus. The problem to be solved is to be able to reduce the

[Configuration of the Invention (Means for Solving the Problems) This invention decodes a channel control block specified by an input/output start command issued from a CPU, and uses the decoding result to determine the channel control block connected to the expansion system bus. If it is determined that memory read from the device is specified, the basic system bus gap (free time period)
Use this to first issue a memory read request that should naturally be issued from the channel device for which the memory read is specified, store the read data in the memory data buffer, and then respond to the memory read request from the channel device. The read data in the buffer is output to the request source via the extended system bus, while the memory read request from the channel device is prohibited from being output to the basic system bus. It is something.

(Function) According to the above configuration, it is possible to significantly reduce the frequency at which memory read requests from channel devices connected to the expansion system bus are output to the basic system bus, thereby reducing the load on the basic system bus. becomes.

(Embodiment) FIG. 1 is a block diagram of a bus expansion adapter according to an embodiment of the present invention, and FIG. 2 is a block diagram of an information processing system to which the bus expansion adapter of FIG. 1 is applied.

In the system shown in FIG. 2, 11 is a CPU that controls the entire system, and 12 is a main memory in which various programs, data, etc. are stored. 13. 14 is a channel device that is activated in response to an input/output start command (start I/O command, SIO command) from the CPU II and performs input/output control between the main memory 12 and various input/output devices such as a magnetic disk device; l5; is CPU IL main memory l2 and channel device 13. This is the basic system bus for connecting 14 etc. l6 is an expanded system bus (extended system bus) of the basic system bus l5, 17. 18 is a channel device connected to the expansion system bus 16, and 19 is a bus expansion adapter for connecting the expansion system bus 16 to the basic system bus 15 to expand the system bus. This bus expansion adapter 19 is provided with a memory data buffer 20. This memory data buffer 20
The bus expansion adapter 19 issues a memory read request prior to a memory read request from a channel device connected to the expansion system bus 16 under the bus expansion adapter 19 (hereinafter referred to as a channel device under the expansion system bus 16). This is used to temporarily store memory data read from the main memory 12 by issuing the .

Now, the CPU II shown in Figure 2 is the basic system bus 1.
5 or the expansion system bus 16, an input/output start command is output to the basic system bus 15. This input/output start command includes a channel identifier for specifying the channel device to be activated, an activation signal PR for the channel device specified by this identifier,
C that describes the input/output operations to be performed by the same channel device
Contains the storage start address (CCB storage address) in the main memory 12 of the CB (channel control block).

The start signal PR and CCB storage address in the input/output start command on the basic system bus 15 are stored in the RP register 21.
After being led to and held in a read data register (RDR) 22, it is led to a microcomputer 23 provided in a bus expansion adapter 9 and an expansion system bus 16. Further, the channel identifier in the input/output start command on the basic system bus 15 is guided to and held in an address register (not shown) provided in the bus expansion adapter 19, and then guided to the microcomputer 23 and the expansion system bus 16. .

The microcomputer 23 is activated by the activation signal PR in the input/output start command from the main memory 12, and determines whether the channel device indicated by the channel identifier in the command is a channel device under the bus expansion adapter 19, i.e. It is determined whether the command is a start command (input/output start command) for a channel device under the bus expansion adapter 19. If the activation command is for a channel device under the bus expansion adapter 19, for example, the channel device 17, the microcomputer 23 uses the CCB storage address from the register 22 to send it to the main memory 12 via the basic system bus 15.
and read the corresponding CCB.

The microcomputer 23 has a built-in CCB decoder 24 for decoding the CCB, and the main memory 1
The CCB read from CCB 2 is decoded by the CCB decoder 24. The microcomputer 23 includes an address register 25 that holds a memory address (buffer memory address) BMA for reading memory from the main memory 12 to the memory data buffer 20, and a transfer destination channel for data read to the memory data buffer 20. I that holds the channel identifier BDID indicating the device
It is connected to each input of the D register 26. If the microcomputer 23 determines as a result of the decoding by the CCB decoder 24 that a memory read operation of the channel device (channel device 17 in this case) under the bus expansion adapter 19 is specified, the microcomputer 23 determines that the memory read operation is specified by the CCB. The start address of the current memory read operation is set in the address register 25, and the channel identifier of the channel device (channel device 17) for which the memory read operation is specified is set to the BD.
It is set in the ID register 26 as an ID.

Memory address BMA (
Here, the memory start address) and the channel identifier BDID indicated by the ID register 26 are led to the 0-side input of a selector (hereinafter referred to as SEL) 27 provided in the bus expansion adapter 19, as shown in FIG. This 5
One side of the EL27 includes a memory address MAO for reading memory from the channel device under the bus expansion adapter 19, and an address register 28 and a 1D register 29 for holding the channel identifier 5IDO (source ID0) of the same channel device. Each output (connected data of) is derived. 5EL27 selects the content of the 0 side input or the 1 side input according to the state of the selection control terminal S.

The output of ID register 2B (BD ID) is sent to comparator 30.
It is also guided by the input. The B input of this comparator 30 has I
The output (SIDO) of D register 29 is derived. The comparator 30 becomes logic “1” only when the input contents of both A and 8 are equal.
Outputs the signal. The output of the comparator 30 is sent to the inverter 31
The level of the signal is inverted by the inverter 31. The output of this Inno Kuichi 31 is an AND gate (
A) 32, and the output of the MR register 33 holding the memory read request MRO from the channel device under the bus expansion adapter 19 is guided to the other input of the AND gate 32. The AND gate 32 operates only when the output of the inverter 31 and the output of the MR register 33 are both 1'', that is, the channel identifier BDID indicated by the ID register 26 and the channel identifier 5IDO indicated by the ID register 29 do not match, and the MR Only when the memory read request MRO indicated by the register 33 is "1" (true), in other words, among the channel devices under the bus expansion adapter 19, a request from a channel device with a channel identifier different from the channel identifier indicated by the BDID. Outputs a logic “1” signal only when a memory read request is made.AND gate 32
The output of is led to the selection control terminal S of 5EL27.

From the above, when the memory read request MRO is not issued from the channel device under the bus expansion adapter 19, the output of the AND gate 32 becomes "0" regardless of the comparison result of the comparator 30, and the output of the address register 25 becomes "0". The indicated memory address BMA (memory start address here), the channel identifier BDI indicated by the ID register 2B
D is selectively output from the 5EL27. On the other hand, when a memory read request MRO is issued from a channel device under the bus expansion adapter 19, if the comparison result of the comparator 30 indicates a match, the memory address BMAO, ID indicated by the address register 28 is sent. If the channel identifier 5IDO indicated by the register 29 indicates a mismatch, the memory address BMA indicated by the address register 25 and the channel identifier BDID indicated by the ID register 26 are set to 5E.
It is selectively outputted from L27.

The memory address (BMA or MAO) of the selected output data from the 5EL 27 is led to the input of the address register 34, and is held in the register 34 as the memory address MAI for accessing the main memory 12. Also, the channel identifier (BDID or 5IDO) of the selected output data from the 5EL27 is stored in the ID register 35.
The same register 35 is input as the channel identifier 5IDI indicating the channel device from which the main memory 12 is accessed.
is maintained. Further, the output of the AND gate 32 is held in the MR register 36 as a memory read request MRI from the channel device under the bus expansion adapter 19.

Now, the microcomputer 23 has a CC
When the address register 25 and register 2B are set according to the B decoding result, the basic system bus 1
A memory read request MR2 to the main memory 12 is sent to the main memory 12 on the main memory 12. This request MR2 is set to have the lowest priority regarding bus acquisition on the basic system bus 15. Therefore, the memory read request MR2 is valid only when the basic system bus 15 is free, and the main memory 1
Accepted by 2. When this request MR2 is accepted, the memory address M A indicated by the address register 34 is
1 and the channel identifier 5I indicated by the ID register 35.
DI is output onto the basic system bus 15.

This is a memory read request MR from the MR register 36.
The same applies even if I is accepted.

When the main memory 12 (memory controller, not shown) receives the memory read request MR2, the main memory 12 (memory controller, not shown) receives the read data (here, 4 bytes) corresponding to the memory address MAI and the data indicating the transfer destination channel device. Channel identifier DID (matches channel identifier 5IDI)
Together with I, the memory response MP2 is output onto the basic system bus 15. The read data on the basic system bus 15 is led to a read data register 22 provided in the bus expansion adapter 19 and held there, and then led to a memory data buffer 20. Also, basic system bus 1
Memory response MP2 on 5 is bus expansion adapter 1
After being led to the MP register 37 provided in the memory data buffer 20 and held therein, the data is led to the write control unit 38 for managing writing to the memory data buffer 20.

The write control unit 38 writes the read data from the read data register 22 to the address in the memory data buffer 20 indicated by the write pointer WP (initial value 0) at the timing of the memory response MP2 from the MP register 37, and Count up. This signal for counting up the write pointer WP is also used as an interrupt signal 39 to the microcomputer 23. The microcomputer 23 has a light control section 38
Memory address BMA of address register 25 is +4 (for 4-byte read) in response to interrupt signal 39 from
After that, the next memory read request MR2 is output.

As a result, when this request MR2 is accepted, BMA incremented by +4 is used as the memory address MAI, and the next 4 bytes are read from the main memory 12 and written to the next address in the memory data buffer 20. The above operations are repeated until the memory read for the transfer data length specified by the CCB is completed.

Now, the input/output start command (start signal PR inside) is sent from the CPU II onto the basic system bus 15.

CCB storage address, channel identifier) are stored on the expansion system bus ■ via the bus expansion adapter 19 as described above.
It also leads to 6. If the channel device connected to the expansion system bus 6 is the device to be activated indicated by the input/output start command (channel identifier inside) on the expansion system bus 1G, it performs the well-known (7) CCB read. , performs the letter input/output control operation specified by this CCB. Therefore, when a memory read operation is specified by the CCB as described above, the corresponding channel device under the bus expansion adapter 19 (channel device 17 in this case) stores the memory address MAO and channel identifier on the expansion system bus 16. A memory read request MRO is output together with 5IDO.

MAO output from the channel device (channel device 17) under the bus expansion adapter 19 onto the expansion system bus 16
, S I DO, MROl;t, bus expansion adapter 19
each address register 28. ID register 29
．． It is held in the MR register 33. The memory read request MRO held in the MR register 33 is guided manually to one of the AND gates 32, and the AND gate (A
) 40. This and gate 40
The output of the comparator 30 is led to the other input of the comparator 30. The AND gate 40 determines whether the memory read request MRO from the MR register 33 and the match comparison result from the comparator 30 are “
A signal of logic "1" is output only in the case of a memory read request from a channel device to which the read data read in advance into the memory data buffer 20 is transferred. In this embodiment in which the memory read request MRO is issued from the channel device 17, the memory read request MRO and the match comparison result of the comparator 30 are both "1", so a logic "L" signal is output from the AND gate 40. Output. If the match comparison result of the comparator 30 is "1", the output of the AND gate 32 becomes "0"', and the memory read request MRO from the MR register 33 is basically sent as the memory read request MRI from the MR register 36. Output on the system bus 15 is prohibited. Also, the address register 28. Memory address MAO and channel identifier 5IDO from ID register 29 are MAL, 5
Selecting from the 5EL 27 as an IDI and outputting it to the basic system bus 15 is prohibited.

The output of the AND gate 40 is a flip-flop, e.g.
- Flip-flop (hereinafter referred to as F/F) 41
Guided by the power of three people, it is memorized by F/F 41.

Therefore, when a logic "1" signal is output from the AND gate 40, the F/F 41 enters the set state, and the read data read in advance into the memory data buffer 20 is transferred from the destination channel device (channel device 17) to the memory read. It is indicated that a request MRO has been issued.

The bus expansion adapter 19 is provided with a read control section 42 for managing reading from the memory data buffer 20, as shown in FIG. This lead control section 42
A read pointer RP (initial value O) used for read management is guided to the A input of the comparator 43. This comparator 43
The write pointer W from the write control unit 38 is input to the B input of
P is guided. Comparator 43 compares the input contents of both A and 8, and in the case of A-B (that is, when read pointer RP is equal to write pointer WP), memory data buffer 2
Outputs a logic "1" signal indicating that 0 is empty.

The output of the comparator 43 is guided to the input of an inverter 44, and its level is inverted by the inverter 44.

The output of this inverter 44 is guided to one input of an AND gate (A) 45, and the Q output of the F/F 41 is guided to the other input of the AND gate 45. and gate 45
is the output of inverter 44 and the Q of F/F 41
Only when both outputs are "1", that is, only when the memory data buffer 20 is not empty and the request is a memory read request from the channel device (channel device 17) to which the read data pre-read into the memory data buffer 20 is to be transferred. , outputs a logic “1°” signal.

Now, the bus expansion adapter 19 has an MR
An MP register 46 is provided that holds a memory response MPI returned together with read data read from the main memory 12 in response to a memory read request MR+ from the register 36. The output of this MP register 46 is guided by the power of an inverter 47, and its level is inverted by the same inverter 47.

The output of this inverter 47 is led to one input of an AND gate (A) 48, and the other input is connected to an AND gate 45.
The output of is derived. AND gate 48 is inverter 47
The output of MRI is “1”, that is, (memory read request
If the output of the AND gate 45 is “1” in the absence of memory response MPI (corresponding to
A signal 49 is output.

A logic “1” signal 49 from the AND gate 48 is guided to the read control section 42. In response to this signal 49, the read control unit 42 reads the pre-read data (4) from the address in the memory data buffer 20 indicated by the read pointer RP.
byte) and counts up the read pointer RP. The data read from the memory data buffer 20 by the read control unit 42 is sent to the selector (SEL).
Guided by 50's 0 side human power. The output of the read data register 22 is led to the 1-side input of the selector 50, and the memory response MPI from the MP register 46 is led to the selection control terminal S. In the case of MPI (-S)-0 as in this example, the selector 50 selectively outputs the read data from the memory data buffer 20 guided by the 0-side manual input. Selected output data of this selector 50 is guided onto the expansion system bus 16.

The logic '12 signal 49 from the AND gate 48 is also led to one of the OR gates (OR) 51.

The other input of this OR gate 51 is connected to the MP register 46.
A memory response MPI from is derived.

The OR gate 51 receives the signal 49 or the memory response M
If either PI is "1" (that is, when reading from the memory data buffer 20 or from a channel device under the bus expansion adapter 19 that is not the data transfer destination of the memory data buffer 20, the memory response MP
When I is returned), a memory response MP of logic "1" indicating that the read data output from the selector 50 to the bus expansion adapter 19 is valid is output to the expansion system bus 16.

The memory response MPI from the MP register 46 is also guided to the selection control terminal S of the selector (SEL) 52. The channel identifier BDID from the ID register 26 is introduced to the 0 side input of the selector 52, and the output of the ID register 53 provided in the bus expansion adapter 19 is introduced to the 1 side input. This ID register 53 is a bus expansion adapter 19 that is not the transfer destination of data in the memory data buffer 20.
(by reading from the lower channel device) memory response M
It is used to hold the channel identifier DIDI (indicating the destination channel device) returned with the PI. In the case of MPI (-'5)-0 as in this example, the selector 52 converts the channel identifier BDID from the ID register 26 led to the 0 side input into the destination channel device ( Here, it is selectively output as a channel identifier DID indicating the channel device 17). Selected output data of this selector 52 is guided onto the expansion system bus 16.

If the channel identifier DID output from the selector 52 to the expansion system bus 16 matches the channel identifier of the channel device connected to the expansion system bus 16, the channel device connects to the expansion system bus 1 from the selector 50.
6 (memory read data) is taken in at the timing of the memory response MP output from the OR gate 51 to the expansion system node 16.

The logic “1” signal 49 from the AND gate 48 is F/
It is also led to the J input of F41. This allows F/
F41 is reset. When the next memory read request MRO is issued from the channel device (channel device 17 in this case) to which the data in the memory data buffer 20 is to be transferred, the F/F 41 resets again and transfers the previous memory data. Data is retrieved from the sofa 20. If the data retrieval from the memory data buffer 20 progresses and the read pointer RP matches the write pointer WP (that is, the memory data buffer 20 becomes empty), the comparator 43
The output becomes logic "1". As a result, and gate 4
The outputs of 5 and 48 become logic "0" regardless of the Q output of F/F 41, and when data is taken out from the memory data buffer 20 (the operation of writing read data from the main memory 12 to the memory data buffer 20 is performed). (until the write pointer WP advances).

As described above, in this embodiment, the memory read that should originally be executed by the channel device under the bus expansion adapter 19 (in this case, the channel device 17) in accordance with instructions from the CCB is controlled by the microcomputer 23 in the bus expansion adapter 19. The basic system bus 15 is used for execution with low priority, and the read data is transferred to the memory data buffer 20.
I try to store it in . Then, when a memory read request MRQ is issued for the original memory read from the channel device (channel device 17) to which memory read has been instructed by the CCB, the read data stored in the memory data buffer 20 is retrieved. It is returned to the requesting channel device (channel device 17).

At this time, since the memory read request MRO is prohibited from being sent as an MHI to the basic system bus 15, the load on the basic system bus 15 is reduced.

By the way, in this embodiment, during the period when data is prefetched to the memory data controller 20 under the control of the microcomputer 23, a channel device under the large expansion adapter 19, for example, a channel device 18 is activated. An input/output start command may be issued from the CPU II input. In this case, the microcomputer 23 ignores the above input/output start command.

In such a state, if a memory read request MRO is output from the channel device 18 (in this case, the comparator 30
The result of the matching comparison is "0" indicating no match. Comparator 3
If the output of 0 is "Oo", the memory read request MRO from the channel device 18 is output on the basic system bus 15 as a valid MRI.

Also memory address MAO from channel device 18.

Channel identifier 5IDO is selected by 5EL 27 and output on basic system node 15 as MAI, 5IDI. As a result, memory reading similar to the conventional method is performed. When the output of the comparator 30 is “0”, F/
The Q output of F 41 also becomes "0", and the signal 49 from the AND gate 48 also becomes "0". When the signal 49 is "0", data extraction from the memory data buffer 20 is prohibited.

A request MRI corresponding to the memory read request MRO from the channel device 18 is output to the basic system node 15,
When the same request MHI is accepted by the main memory 12,
A corresponding memory read is performed. As a result, the read data from the main memory 12 is transferred via the basic system bus 15 with the memory response MPI of logic "1" and the channel identifier DIDI (indicating the channel device 18)
The read data is returned to the large expansion adapter 19, and the read data is held in the register 22, the memory response MPI is held in the MP register 46, and the channel identifier DIDI is held in the ID register 53. For MPI-1, register 2
The read data held in the ID register 53 (from the main memory 12) is selectively output from the selector 50 to the expansion system I/O system 16, and the DIDI held in the ID register 53 is transferred to the destination channel device (of the output data from the selector 50). Here, it is selectively output from the selector 52 to the expansion system bus 16 as a channel identifier DID indicating the channel device 18). Further, a valid memory response MP is output from the OR gate 51 in response to MPI -1.

Now, when the channel device 17 performs a memory read of the amount of transfer specified by the CCB under the control of the microcomputer 23 in the bus expansion adapter 19, the channel device 17 transfers the termination information having its own channel identifier as 5IDO to the expansion system bus lG. Output on top. This termination information includes a termination request (transfer end signal) TRI of logic "1". The termination information from the channel device 17 is sent to the bus expansion adapter 1.
Guided by 9, channel knowledge and sashiko (SIDO) in the same information
is held in the ID register 29, and the termination request TRI is held in the TR register 54.

Termination request T held in TR register 54
R is guided to one input of an AND gate (A) 55.

The output of the comparator 30 is led to the other input of the AND gate 55. The AND gate 55 operates when the output of the comparator 30 and the termination request TR from the TR register 54 are both "1", that is, when the memory data buffer 20
In the case of a termination request from a channel device to which internal data is to be transferred, a signal of logic "1°" is output.The output of this AND gate 55 is led to the microcomputer 23 as an interrupt signal for notifying the end of transfer.Microcomputer 23 is the logic “1” from the AND gate 55
In response to the output signal of the light control section 38. A write pointer WP and a read pointer RP are sent to the read control unit 42.
A clear signal 5G for clearing is output, and the memory data buffer 20 is released to a newly activated channel device. Also, TRI from the TR register 54 is
It is output onto the basic system bus 15 via the TR register 57 as a termination request TR2 for I.

[Effects of the Invention] As described in detail above, according to the present invention, a memory read request that should naturally be issued from a channel device under an extended system bus for which memory read is specified by a CCB is handled by a gap in the basic system bus ( The bus expansion adapter itself issues read data onto the basic system bus using the idle time (vacant time) and stores the read data in a memory data buffer, and then transmits the read data in the buffer in response to a memory read request from the channel device. Since the request source is accessed via the expansion system bus, memory read requests from channel devices connected to the expansion system bus do not have to be transmitted to the basic system bus, and input/output of this type of channel device can be performed. Control can be performed normally, the load on the basic system bus is reduced, and system throughput is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bus expansion adapter according to an embodiment of the present invention, and FIG. 2 is a block diagram of an information processing system to which the bus expansion adapter of FIG. 1 is applied. ■1... CPU, 12... Main memory, 13. 1
4. 17゜18... Channel device, 15... Basic system bus, 1B... Expansion system bus, 19...
・Bus expansion adapter, 20...Memory data buffer, 23...Microcomputer, 24...CCB
Decoder, 27.52...Selector (S E L)
, 30.43... Comparator, 38... Light control unit,
41...Flip-flop, 42...Read control section. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) In a bus expansion adapter for expanding a basic system bus to which a CPU, main memory, channel devices, etc. are connected, and for connecting an expansion system bus to which channel devices, etc. are connected, to the basic system bus, the CPU
If the channel control block indicated by the input/output start command issued from issuing a memory read request to the main memory using the basic system bus to issue a second memory read request corresponding to a first memory read request from a channel device connected to the expansion system bus and designated as a memory read destination; a memory data buffer for temporarily storing read data read from the main memory to the basic system bus in response to the second memory read request from the memory read request means; transfer control means for transferring the memory data stored in the memory to the channel device via the expansion system bus in response to the first memory read request from the channel device designated as the memory read destination; and memory read request output control means for prohibiting the first memory read request from the channel device that is connected to the base system bus from being sent to the basic system bus. (2) A detection means is provided for detecting a transfer end signal indicating the end of transfer from the channel device controlled by the transfer control means, and the memory data buffer is released in accordance with the detection result of the detection means. The bus expansion adapter according to claim 1, characterized in that the bus expansion adapter is configured as follows. (3) After the memory read request issuing means detects that a memory read operation of the channel device connected to the expansion system bus is specified, the above-mentioned memory read request issuing means does not perform the above-mentioned operation until the detection means detects the transfer end signal. A second method characterized by ignoring subsequent input/output start commands from the CPU.
A bus expansion adapter according to the claims.