JPH01250162A - Memory writing system - Google Patents

Abstract

PURPOSE:To avoid the erroneous breakage of data stored in a memory by preparing a write protecting circuit and setting a write enable memory address as a reference address via a CPU prior to a memory writing action. CONSTITUTION:A write protecting circuit 5 is provided on an address bus of a DMA control circuit 2 and a CPU 1 sets a write enable memory address as a reference address prior to a memory writing action. Thus the data stored in a memory serving as a receiver of the DMA transfer even in case the CPU makes a mistake to set a transfer destination address at start of the DMA transfer. Then the reliability of a computer system is improved. Furthermore the cost is never increased in particular owing to such a simple constitution where the data on the address bus is compared with the reference data and the working of the circuit 2 is inhibited based on the discordance between both data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory write method using a DMAυ1ty11 circuit.

(Prior art) Conventionally, in this type of memory write method, the DMA idle
After setting the write destination memory address in the t11 circuit, the CPU performs a series of processes to activate the + control circuit for the DM8, and thereafter f) Based on the address data sequentially generated from the MA control circuit, Data was written to the memory without involving the CPU.

(Problem to be Solved by the Invention) However, in such a memory write method, once the DM A tdl control circuit is activated,
Since data is written to memory without the CPU being involved, if the CPLJ accidentally sets a write-prohibited memory address in the DMA control circuit, for example, a read-only area in the memory may There was a problem in that it was destroyed during data transfer.

The purpose of this invention is to prevent destruction of read-only areas in the memory, etc., without the involvement of the CPU, even if the write destination memory address is incorrectly set in the DMA ill 111 circuit. The purpose is to provide a memory write method.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention sets a memory address to be a write destination in a DMA control circuit, and then
In a memory write method in which the CPU performs a series of processes to start up the DMA control circuit, and then data lines to the memory are executed without CPU involvement based on address data sequentially generated from the DMA control circuit. , A write protect circuit is provided on the address bus of the DMA control circuit to stop the operation of the DMA control circuit when the address data does not match a preset reference address, and the write protect circuit is provided with a CP.
U is characterized by setting a writable memory address as a reference address prior to memory writing.

(Function) According to this configuration, the write is connected to the protection circuit.
The PU sets the writable memory address as the reference address before writing the memory, so if the write destination memory address is set incorrectly in the DMA control circuit, the write protection circuit will prevent the D
The operation of the MA control circuit is stopped.

(Embodiment) FIG. 1 is a block diagram showing the hardware configuration of a computer system to which the method of the present invention is applied.

As shown in the figure, this computer system is
PU1. DMA control circuit 2. It is composed of an input/output circuit 3, a memory 4, and a write protect circuit 5.

The CPU 1 is mainly composed of a microprocessor, and is configured to implement various control functions using built-in ROM and RAM.

The DMA control circuit 2 is well known as a DMAC-LSI, etc., and is capable of programming the transfer destination address under control from the CPU 1, and after being activated by the CPU 1, the DMA control circuit 2 is configured to control the DREQ signal, DACK signal, etc. While exchanging signals with the input/output circuit 3, DMA transfer from the input/output circuit 3 to the memory 4 is performed.

Further, during this DMA transfer, transfer destination addresses are sequentially sent onto the address bus.

The write protect circuit 5 is provided on the address bus of the DMA control circuit 2, and when the address data sent onto the address bus does not match the reference address set in the write protect circuit 5, the DMA control circuit At the same time, an interrupt signal NMI is sent to the CPU 1 to notify the CPU 1 of an error in setting the write destination address. Further, the reference address in the write protect circuit 5 is CP
The reference address can be programmed arbitrarily under control from U1.

Next, in the above configuration, from the input/output circuit 3 to the memory 4
The operation when performing DMA transfer to is explained below.

When a series of programs including DMA transfer is to be executed in the CPU 1, a writable address of the memory 4 is set in the write protect circuit 5 as an initial process.

Needless to say, this writable address must be set as accurately as possible.

Following this initial processing, routine processing begins,
When the DMA transfer processing part arrives, as is well known, the CPU 1 sets the transfer address in the memory 4 in the form of a transfer start address, the number of transfer bytes, etc. in the DMA control circuit 2, and then the DMA control circuit 2 Activate against.

Then, DM A! The II Ia circuit 2 sequentially sends the transfer destination address onto the address bus, and at the same time, the signal DRE is sent between the DMA control circuit 2 and the input/output circuit 3.
Q and DACK are exchanged, and as a result, DMA transfer from the input/output circuit 3 to the memory 4 is performed.

On the other hand, if the CPU 1 incorrectly sets the transfer destination address in the DMA control circuit 2, the write protect circuit 5 will issue a stop command when the address is sent onto the address bus. signal is DMA
The signal is sent to the control circuit 2, thereby stopping the DMA transfer operation, and at the same time, an interrupt signal INMI is sent to the CPU 1. Based on this, the CPU 1 performs a predetermined process to prevent a setting error in the transfer destination address. It will be recognized and necessary measures will be taken.

Therefore, as long as the memory address settings for the write protect circuit 5 executed in the initial processing are correct, even if D
Even if an error occurs in setting the MA transfer address, the data stored in the memory 4 at the address will not be destroyed by mistake.

[Effect of the invention] As is clear from the above explanation, according to this invention, the DMA
Even if you make a mistake in the transfer destination address setting process when starting a transfer, the data in the memory that is the transfer destination will not be accidentally destroyed, and the reliability of this computer system can be improved. Moreover, the configuration for this purpose simply compares the data on the address bus with reference data and prohibits the DMA IDl TE1 circuit based on the mismatch between the two, so there is no particular increase in cost. Moreover, it can be applied to conventional systems as is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a computer system to which the method of the present invention is applied. 1...CPU 2...DMA control circuit 3...I/O circuit 4...Memory 5...Write protection circuit

Claims (1)

[Claims] (1) After setting the write destination memory address in the DMA control circuit, the CPU performs a series of processes to start up the DMA control circuit, and thereafter the CPU participates based on address data sequentially generated from the DMA control circuit. In the memory write method, the operation of the DMA control circuit is performed when the address data does not match a preset reference address on the address bus of the DMA control circuit. A write protect circuit is provided to stop the CP.
U is a memory write method characterized by setting a writable memory address as a reference address prior to memory write.