JP3402414B2 - Watchdog timer circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer circuit for detecting an abnormal operation of a CPU. 2. Description of the Related Art Conventionally, a CPU system provided with an abnormality detecting function using a monomulti (monostable multivibrator) outputs a pulse at regular intervals by an OUT (out) command of the CPU and activates the monomulti. are doing. The output of this mono multi is connected to the reset terminal of CPU or NMI.
(Non-maskable interrupt) The RC integration circuit composed of a resistor and a capacitor, because if a CPU malfunctions, a pulse due to an OUT command or the like is not output and a mono-multi cannot be started. After the elapse of the time constant tw, a pulse was applied to the NMI terminal of the CPU as shown in FIG. However, in the prior art, when the CPU is to execute an instruction one step at a time, READY to the CPU is extended by an access cycle by a WAIT signal, that is, the CPU is waited. In the (WAIT) state, a pulse by an OUT command or the like cannot be output at regular intervals, the mono-multi cannot be started, and the CPU detects an operation abnormality and makes an incorrect judgment. In view of the above, an object of the present invention is to operate the mono-multi normally even when the CPU is in the wait state, and to prevent erroneous operation abnormality detection. [0004] To solve the above-mentioned problems,
Therefore, the present invention uses the rising edge of the reset signal or the CPU
Monos activated by the pulse output by the out command
The output of the table multivibrator is reset by the CPU.
Terminal or non-maskable interrupt terminal NMI
Detects abnormal operation of CPU by inputting
Yes, WA to stop READY for the CPU
A RC integration circuit whose operation is stopped by the IT signal
In the watchdog timer circuit, the CPU
Always in READY state for memory or I / O, etc.
If it is working, the monostable multivibrator
The output of the CPU is output without interruption, and the CPU
Operates without receiving an interrupt such as NMI.
When U enters wait state due to WAIT signal
Is the trigger pulse signal output from the CPU.
The monostable multi-vibration without force
Data cannot be kicked again, the integration operation ends, and the WAIT
Signal through an open collector output gate circuit.
RC time constant input terminal of monostable multivibrator
The RC integration circuit at that time
Will be reset and will be maintained during the wait period.
It was made. According to the above means, when the CPU is in a wait state such as when executing a step, the mono-multi integration operation is stopped, and the CPU can prevent erroneous operation abnormality detection. An embodiment of the present invention will be described below with reference to FIG. First, the CPU 1 is at the center of the system, and memories, I / O, and the like are connected to the periphery through a bus. Reference numeral 2 denotes a mono-multi function of a watchdog timer circuit, which is kicked by a trigger pulse signal 6 having a constant period outputted from the CPU 1 by an OUT command or the like. The output of Mono Multi 2 is
A period signal of the time constant tw of the RC integration circuit composed of the resistor 3 and the capacitor 4 is output, and is input to the NMI of the CPU 1 by interruption. In this case, the output of the mono-multi 2 is set before the end of the time constant tw, that is, before the end of the integration operation.
When the trigger pulse signal 6 is input from 1, the output of the mono-multi 2 is reset from that point and the integration operation is started again. As described above, when the CPU 1 is constantly operating in a READY state with respect to peripheral memories or I / Os, the output of the mono multi 2 is output without interruption, and an interrupt such as an NMI is issued to the CPU 1. Not enter
Works fine. Next, when the CPU 1 is put into the wait state by the WAIT signal 7, the trigger pulse signal 6 output from the CPU 1 is not output, so that the mono-multi 2 cannot be kicked again and the integration operation ends.
The CPU 1 receives an interrupt such as an NMI and performs an incorrect operation. However, the WAIT signal 7 is transmitted to the R of the mono-multi 2 through the gate circuit 5 having an open collector output.
By inserting it into the C time constant input terminal 8, the RC integrator is reset at that time, and this state is maintained during the wait period. This state corresponds to the period b shown in FIG. As described above, according to the present invention, C
Even when PU1 waits during step execution or the like,
An interrupt such as an NMI is received, so that incorrect operation abnormality detection can be prevented, and the watchdog timer circuit can always operate normally.

[Brief description of the drawings] FIG. 1 illustrates a circuit according to the present invention. FIG. 2 illustrates the operation of a watchdog timer circuit. FIG. 3 is a diagram illustrating a conventional circuit. [Explanation of symbols] 1 CPU 2 mono multi 3 Resistance 4 Capacitor 5 Open collector output gate circuit 6 Trigger pulse signal 7 WAIT signal 8 RC time constant input terminal tw mono multi output period a Watchdog error detection period b Mono-multi output suspension period

Claims (1)

(57) [Claims] [Claim 1] Rising of reset signal or CPU
It is started by the pulse output by the out command of (1).
Output of the monostable multivibrator (2)
Reset terminal of CPU (1) or non-maskable input
CPU (1) by inputting to the interrupt terminal NMI
The CPU (1) detects an abnormal operation of the CPU (1).
Operate by WAIT signal to stop READY
Watchdog timer with RC integration circuit that stops
In the circuit, the CPU (1) is connected to a peripheral memory or an I / O or the like.
However, if it is always operating in the READY state,
The output of the no-stable multivibrator (2) is interrupted
Output to the CPU (1) with NMI
The CPU (1) operates without receiving an interrupt such as an interrupt.
When the CPU (1) enters the
Trigger pulse signal (6) is not output,
Press the monostable multivibrator (2) again.
The integration operation ends without being locked, and the WAIT signal (7)
Through an open collector output gate circuit (5)
RC time constant of monostable multivibrator (2)
By inserting it into the input terminal (8),
The RC integration circuit is reset and held during the wait period.
Watchdog character characterized by continuing
Ima circuit.