JP2737724B2 - NMI communication device between processors and system bus controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an edge-triggered NM.
I (Non-Maskable Interrupt)
NMI between microprocessors with terminals
The present invention relates to a communication device and a system bus controller, and more particularly to an inter-processor NMI communication device and a system bus controller that exchange commands between microprocessors and collect fault information using an NMI.

[0002]

2. Description of the Related Art As a runaway monitoring mechanism of a processor using an NMI, an "abnormal processing state control system" disclosed in Japanese Patent Application Laid-Open No. Sho 60-176147 and Japanese Patent Application Laid-Open No. 63-1231 are disclosed.
No. 38, “Microcomputer runaway detection circuit”, JP-A-4-69746, “Memory dump method”, JP-A-4-88448, “Program area protection device”, and the like. There is.

On the other hand, in the inter-processor communication in a tightly-coupled multiprocessor type information processing apparatus constituted by a microprocessor having an NMI terminal, the NMI
Is not used, and an interrupt level one step lower than the error interrupt is generally used. This is because NMI cannot perform masking by software. That is, in ordinary software, an interrupt handler that processes an interrupt from a processor is executed during execution of a system call that issues an interrupt to a processor, in consideration of contention for receiving an interprocessor communication from another processor during an interprocessor communication. For exclusive control of
This is because a method of masking an interrupt between processors is adopted.

On the other hand, NMI is generally used to notify the runout of a watchdog timer used for monitoring the runaway of a conventional single processor (see, for example, Japanese Patent Application Laid-Open No. 61-271545). This is because NMI is most effective for stopping the runaway of the processor. In other words, with a normal maskable interrupt, it is impossible to stop the runaway in the case where the software runs away while masking the interrupt. After a runaway stop,
The processor is used for collecting fault information such as a memory dump. In the case of an inexpensive control processor that does not need to collect fault information, there is a method of inputting a run-out signal of a watchdog timer as a reset signal of the processor and restarting the processor.

[0005]

In the above-described conventional inter-processor communication interrupt, in the event of an abnormality, for example, when another processor detects a runaway of another processor and wants to forcibly stop the runaway processor, it is necessary to perform debugging. Sometimes when you want to stop software runaway, you may not be able to do so despite the fact that you want to communicate between processors with the highest priority processing (with a priority higher than error processing). There was a point.

Also, in the conventional watchdog timer interrupt, since the side that detects an error is a non-intelligent device, the processor that receives the NMI stops its own runaway and collects fault information such as a memory dump. There was a problem that it was necessary to do it. But,
In the case of a multiprocessor, in many cases, it is better to collect failure information and recover an error with another normal processor without using the runaway processor. This is especially true in the case of a failure of the processor itself.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to generate an NMI in inter-processor communication and stop any MPU if one MPU can detect an abnormality in any software runaway. An object of the present invention is to provide an inter-processor NMI communication device and a system bus controller capable of extracting an MPU state at that time.

[0008]

According to the present invention, an inter-processor N is provided.
The MI communication apparatus has an M having an edge triggered NMI terminal.
In an information processing apparatus in which one or more PUs and a shared memory accessible from all the MPUs are connected via a system bus, one of the MPUs includes an interrupt code and data indicating an interrupt notification destination MPU. , An inter-processor interrupt generation port for generating an interrupt transaction on the system bus by writing the same, an interrupt factor register set or reset by receiving an interrupt transaction addressed to the own MPU from the system bus, and an interrupt factor register Is set when the NMI factor is set in
A signal is input to the NMI terminal of the interrupt notification destination MPU to generate an NMI, and NM of the interrupt factor register is generated.
An NMI flip-flop that is not reset even if the I factor is reset, and that the interrupt notification destination MPU resets the NMI flip-flop by writing dummy data to stop driving the NMI signal. An NMI flip-preset port enabling reception of an NMI, an MPU control table provided on the shared memory, and a command table written in the MPU control table in the MPU that issues the interrupt transaction, designated by the command table. NMI addressed to MPU
NMI generating means for writing data indicating an interrupt code of
At the interrupt notification destination MPU, M
Fault information collecting means for saving PU fault information, inter-processor NMI processing means for executing the corresponding command processing by referring to the command in the command table, and checking the interrupt factor register, and setting the NMI factor. And a polling means for transferring control to the inter-processor NMI processing means and continuing to check if it has not been set.

Further, the system bus controller of the present invention is an information processing system comprising at least one MPU having an NMI terminal for edge trigger and a shared memory accessible from all the MPUs via a system bus. An MPU for generating an interrupt transaction on the system bus by one of the MPUs writing an interrupt code and data designating an interrupt notification destination MPU;
An interrupt factor register that is set or reset by receiving an interrupt transaction addressed to the system bus from the system bus;
When the cause is set, an NMI signal is set and input to the NMI terminal of the interrupt notification destination MPU to generate an NMI, and the NMI flip-flop which is not reset even if the NMI cause of the interrupt cause register is reset; An NMI flip-flop preset port that resets the NMI flip-flop by writing dummy data by the notification destination MPU to stop driving the NMI signal, and enables the interrupt notification destination MPU to receive the next NMI.

[0010]

Next, the present invention will be described in detail with reference to the drawings.

[0011]

FIG. 2 is a block diagram showing a configuration of an information processing apparatus to which an inter-processor NMI communication apparatus according to one embodiment of the present invention is applied. This information processing apparatus includes a microprocessor (hereinafter referred to as M) having an NMI terminal for an edge trigger.
A PU 1), a system bus controller (hereinafter abbreviated as SBC) 2 for connecting the system bus 4 to the MPU 1, a local memory 3 accessible from the MPU 1, a system bus 4, and a shared memory 5. , The main part is constituted.

The MPU 1 has a coprocessor 10 built therein. Each MPU has its own MPU number. In the case of the present embodiment, the maximum number of MPUs 1 is 16, so the MPU numbers are numbers from 0 to 15. In the present embodiment, the MPU 1 is M4 R4.
000 is assumed. In the R4000, the address translation table (TLB) 11 is built in the R4000, so that when a failure occurs, dumping of the contents of the TLB 11 is often effective. The R4000 has 32 general-purpose registers and 32 coprocessor registers, which are also effective as information when a failure occurs. However, at least one register must be destroyed in order to save the general-purpose register. In this case, kl (r2
6) The register is destroyed.

The local memory 3 is provided for each MPU 1 and is controlled by the SBC 2 so that access is permitted only from the MPU 1. By doing this,
The data of the corresponding MPU 1 can be protected from a malfunction of another MPU 1 and an input / output device (not shown), and the data of the corresponding MPU 1 can be protected even if a failure of the system bus 4 or the shared memory 5 occurs.

A control program 30 including an NMI issuing unit 31, a failure information collecting unit 32, a polling unit 33, and an inter-processor NMI processing unit 34 is loaded on the local memory 3.

The local memory 3 has a ROM (Re
ad Only Memory) and RAM (Rand)
om Access Memory) section. RA
The M section is composed of a volatile RAM and a non-volatile RAM (nvR
AM). Normally, the control program 30 that is executed first when the power is turned on includes a ROM unit or a RAM.
Stored in the department. The advantage of the nvRAM is that it does not disappear even if the power is turned off when the program is loaded. Part of the control program 30 may be stored in the nvRAM. The application is a work area of the control program 30. In this case, once loaded, the data is not erased even if the power is turned off, so that it can be used in the same manner as a ROM, and the control program 30 can be rewritten, so that the control program 30 can be easily upgraded. .

On the shared memory 5, an MPU control table 50 is secured.

FIG. 1 is a circuit block diagram showing a more detailed configuration of SBC2. The SBC 2 has a local bus 6 for separating an address bus and a data bus, and includes a buffer 201, a decoder 202, an interrupt factor register 203, an NMI flip-flop 204, and an NMI flip-flop 204.
Flip-flop preset port 207, inter-processor interrupt generation port 208, address control unit 209
It is comprised including. Note that in FIG.
Is an INT (interrupt) signal, 206 is an NMI signal, 21
0 indicates an NMI reset signal.

The interrupt factor register 203 stores its own MPU
It is set or reset by receiving the interrupt transaction data addressed to 1 from the system bus 4 via the buffer 201 and the decoder 202.

The NMI flip prop 204 is set when the NMI factor is set in the interrupt factor register 203, and sends the NMI signal 206 to the MPU of the interrupt notification destination.
The NMI is input to the NMI terminal No. 1 to generate an NMI. In addition,
The NMI flip prop 204 is not reset even if the NMI factor of the interrupt factor register 203 is reset.

NMI flip preset port 2
In step 07, the MPU 1 of the interrupt notification destination resets the NMI flip-flop 204 by writing the dummy data to stop driving the NMI signal 206, and the MPU 1 of the interrupt notification destination can receive the next NMI.

Inter-processor interrupt generation port 208
Causes one of the MPUs 1 to write an interrupt transaction data including an interrupt code and an interrupt notification destination MPU designation field to generate an interrupt transaction on the system bus 4.

The address control unit 209 monitors the address output from the MPU 1 and selects the local memory 3, the system bus 4, the inter-processor interrupt generation port 208 or the NMI flip preset port 207 according to the address.

FIG. 3 shows an inter-processor interrupt port 20.
8 is a diagram showing the format of the interrupt transaction data which is the format of the interrupt transaction output on the address of the system bus 4 at the same time as the data to be written by the MPU 1 to 8, and which is also the format to be taken into the buffer 201. Bits 0 to 15 are an interrupt destination notification destination MPU designation field including bits indicating which MPU 1 is an interrupt. The interrupt code has 7 bits of bits 16 to 22, and values 0 to 63 are defined as a normal interrupt, and values 64 to 79 are defined as an NMI between processors. When the interrupt operation bit OP is 1, the interrupt factor is set, and when the interrupt operation bit OP is 2, the interrupt factor is reset. Note that bits 24 to 3
1 is an RFU (Reservefor Future)
Use).

When the MPU 1 writes the interrupt transaction data to the inter-processor interrupt generation port 208, the SBC 2 outputs the data on the address of the system bus 4 to generate an interrupt transaction. MPU1 can also generate an interrupt transaction addressed to its own MPU1. This interrupt transaction is sent from the system bus 4 to the SB
It is notified to the interrupt notification destination MPU1 via C2. In the case of this embodiment, the SBC 2 fetches the address of the system bus 4 into the buffer 201 and constantly monitors it,
Recognizes that the interrupt transaction is destined for the own MPU 1, the decoder 202 decodes the interrupt code of bits 16 to 22 and holds it in the interrupt factor register 203. At this time, when the interrupt operation bit OP is 1, the interrupt factor is set and 1 is held, and when it is 0, the interrupt factor is reset and 0 is held.

The normal interrupt factor between processors is NMI
However, it is a normal interrupt, but some of the interrupt codes are defined as NMI factors. When the bit of this NMI factor becomes 1, the NMI flip-prop 204 is set and the NMI signal 206 is driven. MPU1 N
Input to MI terminal. When the normal interrupt bit of the interrupt factor register 203 is set, the INT signal 20
5 is driven and an interrupt is notified to the MPU 1.

The reset of the interrupt factor register 203 is performed with respect to the inter-processor interrupt generation port 208.
This can be performed by writing the interrupt code to be reset to the own MPU 1 and the interrupt transaction data including the interrupt operation bit OP having the value 0. Also, the reset of the NMI flip prop 204 is performed by NM
This can be performed only by writing dummy data to the I flip-flop preset port 207.

The NMI is, as the name implies, an interrupt that cannot be masked. However, since NMI processing cannot be performed by software if NMIs occur continuously, a very common MPU uses the NMI terminal as an edge trigger and once the NMI signal becomes active, the next By not resetting the NMI signal until the NMI processing can be accepted by the software, the occurrence of the next NMI can be prevented. Also in the present invention, the reason why the NMI signal 203 is output via the NMI flip-flop 204 instead of directly outputting the interrupt factor register 203 is that N
The reset of the MI signal 206 is performed by the interrupt factor register 20.
3 is performed separately from the reset so that the occurrence of the next NMI can be masked.

FIG. 4 shows an MPU placed in the shared memory 5.
FIG. 4 is a diagram showing the contents of a control table 50. The MPU control table 50 includes MPU control blocks for the number of MPUs 1. Each MPU control block is composed of an execution status and command tables for the number of MPUs 1 that issue NMIs.

As shown in FIG. 5, the execution status in the MPU control block indicates the current state of the MPU 1. −
1 (dead state) indicates that the MPU 1 has detected a fatal error and has stopped accessing the system bus 4. 0 (none state) indicates that there is no MPU1 corresponding to the MPU control block. 1 (id
The “le state” indicates that the MPU 1 is in a state of polling and waiting for an NMI from another MPU 1. That is, it indicates that the polling unit 33 is being executed. 2 (busy state) indicates that MPU 1
NMI processing means 34 by means of NMI from processor 1
Is being executed. idle state and bus
In the case of the y state, since the level of the NMI terminal is in the interrupt state, the next NMI is suppressed. The difference between the run state and the busy state is that the NMI signal 2
06 is not driven, so that the next NMI can be accepted.

FIG. 6 is a diagram showing in detail the contents of the command table in the MPU control block. The command table includes flags, ST, CMD, MPU #, REG #,
Upper 32-bit data, lower 32-bit data, a transfer address (nvRAM offset), and a transfer length (byte number) are stored. The command table is MPU1
There are the squares of the number. This is because the number of NMIs issued from one MPU 1 to another MPU 1 is the square of the number of MPUs 1 and a command table is provided for each one. MPU 1 that issues NMI
After setting the command structure (see FIG. 24) in the command table corresponding to the MPU number of the own MPU1 in the MPU control block of the MPU1 to which the NMI is issued,
Issue The MPU # in the command table is
It must match the MPU number of the MPU 1 that has always received the NMI. Note that when MPU # is 0xff (the first two digits 0x indicate that the last two digits are hexadecimal numbers; the same applies hereinafter), it is an interrupt for all MPUs 1.

As shown in FIG. 7, the flag in the command table is 1 to indicate that an NMI request is being made, and 0 indicates that there is no NMI request. The MPU 1 that issues the NMI always sets 1 here and issues the NMI. After that, NMI
Is waiting until the MPU 1 that has received the NMI flag resets it to 0 and ends the NMI process.

FIG. 8 is a flowchart showing the processing of the failure information collecting means 32 executed by the MPU 1 having received the NMI. Referring to FIG. 8, the processing of the failure information collecting means 32 includes a general-purpose register saving step S201, a coprocessor register saving step S202, and a TLB dumping step S203.

FIG. 9 is a flowchart showing the processing of the polling means 33 executed by the MPU 1 having received the NMI.
Referring to FIG. 9, the processing of polling means 33
It consists of a register read step S301 in C and an inter-processor NMI occurrence determination step S302.

FIGS. 10 to 16 show NM between processors.
5 is a flowchart showing the processing of the I processing means 34. In this embodiment, since the interrupt codes 64 to 79 are NMI factors, the correspondence between the interrupt codes and the MPU numbers of the issuers is defined as shown in FIG. Therefore, only by reading the interrupt factor register 203 and recognizing the interrupt code, it is possible to recognize which MPU 1 is the NMI. The NMI between the MPUs 1
Even if there is only one level, the MPU 1 that has received the NMI can recognize the MPU number of the NMI issuer from the position of the command table if it can search the command table in its own MPU control block. It is.

Referring to FIG. 10, the NMI between processors
The main processing of the processing means 34 includes an NMI bit reset step S401, an MPU control block read step S402, and an initialize command determination step S4.
03 and register read command determination step S404
And register write command determination step S405;
nvRAM read command determination step S406, n
vRAM write command determination step S407 and ST
It comprises an unauthorized command setting step S408 and an execution status idle setting step S409.

Referring to FIG. 11, the NMI between processors
The initialization command processing of the processing means 34 includes a register save area initialization step S410, a TLB initialization step S411, a TLB dump area initialization step S412, and an ST normal end setting step S413.

Referring to FIG. 12, the NMI between processors
The register read command processing of the processing means 34 includes a register save area information upper / lower data area setting step S414 and an ST normal end setting step S415.

Referring to FIGS. 13 and 14, the register write command processing of the inter-processor NMI processing means 34 includes a REG # determination step S416, an upper / lower data register save area setting step S417, and
T normal end setting step S418 and CRC (Cyc
Like Redundancy Check) bit determination step S419 and CRC bit setting step S419
420, a COUNT bit determination step S421,
COUNT register 0 write step S422, TL
BCLR bit determination step S423, TLB and TLB dump area initialization step S424, SCF
CLR bit determination step S425, control program area initialization step S426, ST normal end setting step S429, EXEC bit determination step S4
30, and the coprocessor register return step S431
, NMI reset step S432, general-purpose register etc. return step S433, and eret (excepti
(on return) instruction execution step S434.

Referring to FIG. 15, the NMI between processors
The processing of the nvRAM read command by the processing means 34 includes a step S435 for transferring data from the local memory and a step ST435.
It comprises a normal end setting step S436.

Referring to FIG. 16, the NMI between processors
The nvRAM write command processing of the processing means 34 includes a step S437 for transferring data to the local memory and a step ST438 for setting the normal end of the ST.

FIG. 18 is a diagram showing the types of CMD in the command table. In this embodiment, five types of commands are defined as CMD. 0x0f is a command indicating initialization, the register saved in the local memory 3 by the fault information collecting means 32, the TLB
And a command for initializing all the TLB dump areas. 0x12 is a command indicating a register read, and among the registers saved in the local memory 3 by the fault information collecting means 32, the RE in the command table
The contents of the register of the register number indicated by G # are stored in the upper 32 bits of data and lower 32 bits in the command table.
This is a command to copy to bit data. 0x13
Is a command indicating register write, which is the reverse of 0x12, and stores the contents of the upper 32 bits data and lower 32 bits data in the command table in the fault information collecting means 3.
2 is a command for copying to the save area of the register number indicated by REG # in the command table in the area saved in the local memory 3 in the local memory 3. 0x02
Is a command to transfer from the offset address in the local memory 3 indicated by the transfer address in the command table by the number of bytes indicated by the transfer length (number of bytes) into the shared memory 5 indicated by the lower 32-bit data. . 0x03 is the reverse of 0x02, and from the shared memory 5 indicated by the lower 32 bits of data in the command table,
This is a command for transferring the number of bytes indicated by the transfer length (number of bytes) to the offset address in the local memory 3 indicated by the transfer address. These commands load the control program 30 into the local memory 3,
Alternatively, it is effective for dumping the contents of the local memory 3.

FIG. 19 shows REG # in the command table.
It is a figure which shows the content of. Bits 0 to 4 indicate a register number of 0 to 31, and bits 5 to 7 are R400 when the value is 0.
A 0 register indicates a cp0 (system control) register when the value is 4, and a cp1 (floating point) register when the value is 5. The register list is as shown in FIG.

FIG. 21 shows the NMI processing means 3 between processors.
FIG. 4 is a diagram for explaining the contents of ST stored in the command table. 0x00 indicates that the command ended normally, 0x07 indicates that the command ended abnormally,
x0A indicates that an undefined command has been issued.

FIG. 22 is a flowchart showing the main processing of the NMI issuing means 31. It is often convenient to summarize the procedure for issuing the NMI as a subroutine when using it in software. FIG. 23 is a flowchart showing the processing of the subroutine (NMI issuing subroutine). FIG. 24 schematically shows a method of calling the NMI generating means 31.

Referring to FIG. 22, NMI issuing means 31
Main processing of the command structure creation step S101
, Shared memory address setting step S102, N
It comprises an MI issuing subroutine call step S103.

Referring to FIG. 23, the processing of the NMI issuing subroutine includes an MPU # normality determination step S104,
Execution status none / dead determination step S10
5, ST invalid MPU number setting step S106,
Execution status busy determination step S107 and ST
Busy set step S108, flag reset step S109, command structure copy step S11
0, ST0xff set step S111, NMI
Generation step S112, ST0xff change determination step S113, 10 ms elapsed determination step S114,
Flag 0 setting step S115 and execution status de
ad setting step S116, ST0x30 setting step S117, command table copying step S1
18

FIG. 25 is a diagram for explaining the contents of the ST stored in the command table by the NMI issuing means 31. 0
x10 indicates a busy state, 0x20 indicates an invalid MPU number, and 0x30 indicates a timeout.

FIG. 26 is a diagram for explaining writing to the register 0. In the inter-processor NMI communication device of the present embodiment, writing to the register of register number 0 (hereinafter referred to as register 0) has a special meaning. Normally in R4000, register 0 is called a zero register,
This is a special register that can read 0 when read and is ignored even if it is written. However, writing to the register 0 of the partner MPU 1 through the inter-processor NMI is performed as shown in FIG.
There is a meaning as shown in

That is, by writing data in which the EXEC bit of bit 31 of the upper 32 bits of data is set to 1, after restoring all the saved registers to the other MPU 1, the address indicated by the Error EPC register is restored. You can tell it to start. The ErrorEPC register is a register that holds a program counter when an NMI occurs. More specifically, by returning the contents of the coprocessor 10 from the register save area of the local memory 3 and then restoring the general-purpose registers, and further executing the eret instruction so that the NMI can be accepted, the ErrorE is executed.
The contents of the PC register are loaded into the program counter from which the instruction is executed.

By using this function, a certain MPU 1 can stop the partner MPU 1 by the NMI between the processors and freely obtain the value of the register at that time, and simultaneously copy the partner MPU 1 to the original program. It is also possible to return. This feature is very useful for multiprocessor debugging. That is, the MPU 1 that has executed the break instruction issues an NMI to all the MPUs 1 to cause the other MPUs 1 to stop executing instructions, execute the debug monitor itself, and read registers from the debug monitor to the other MPUs 1. By writing / writing, the execution state of another MPU 1 can be known,
After that, NMI is issued by a command from the debug monitor.
It is possible to realize a function of restarting from an instruction before occurrence.

In this embodiment, the CRC function of the control program 30 in the nvRAM is realized by writing to the register 0. This corresponds to nvRA of the local memory 3.
In the case where the control program 30 is stored on M, in order to determine whether or not the control program 30 is normally loaded, the last two bytes of the control program 30 are stored in the 2 bytes.
By embedding an RC code and causing each MPU 1 to perform a CRC, it can be used to determine whether it is necessary to load the control program 30 or not. The CRC result can be obtained by reading the register 0 and checking the CRC bit of the upper 32 bits of data.

Only writing to register 0 is performed by own MPU 1
Can be issued to This is the reason why the present invention is established even when only one MPU 1 exists. this is,
Stores own MPU number in MPU # of command structure and returns N
This can be realized by calling the MI issuing unit 31. For example, REG # in the command structure is set to 0, and the MPU
# Is set to its own MPU #, and the upper 32 bits are set to the data in which both the CRC bit and the EXEC bit shown in FIG.
Is called, an NMI is generated in itself immediately after step S112 in the NMI issuing subroutine of FIG. Since the NMI cannot be masked, the NMI issuing means 31 itself is interrupted halfway. Thereafter, the NMI executes the fault information collecting means 32, the polling means 33, and the inter-processor NMI processing means 34. Since the CRC bit is 1, the CRC bit is set in steps S419 and S420 in the inter-processor NMI processing means 34.
A check is performed, and thereafter, since the EXEC bit is 1, the inter-processor NMI processing means 34 is terminated in steps S431, S432, S433, and S434, the state is returned to the state before the interrupted NMI, and the processing from step S113 is performed. Resume. Since the normal end is set in ST in step S429 in the NMI issuing unit 31, the NMI issuing unit 31 proceeds to step S11.
8 and the process ends.

Only writing to register 0 is performed for all M
Simultaneous writing to PU1 is possible. For example, the COUNT register can be initialized by writing to the register 0. The COUNT register is a register in which each MPU 1 counts up every clock, and is a register that can be used by the R4000 as an interval timer. Since this value takes various values at the time of resetting, a method of initializing all at once is required. In this case as well, writing to register 0 is performed for all MPs.
By simultaneously performing the operations on U1, it is possible to initialize the COUNT register to 0 all at once.

Further, by writing to register 0, T
It is also possible to clear the LB area and the control program area on the nvRAM.

Reading the register 0
The 2-bit data is used to read the CRC bit on the nvRAM, and the lower 32 bit data is used to read the revision of the control program 30.

Next, the operation of the thus-configured inter-processor NMI communication device of this embodiment will be described.

The NMI issuing means 31 creates a command structure on the shared memory 5 (step S101), sets the shared memory address where the command structure is stored in the r4 register (step S102), and executes an NMI issuing subroutine. Call (step S103). Then, r4
With the register as an argument, the head address of the command structure on the shared memory 5 is passed to the NMI issuing subroutine.

In the NMI issuing subroutine, the NMI issuing means 31 first sets MPU # in the command structure to 0-1.
It is checked whether it is between 5 or 0xff (step S104). If the value is any other value, the illegal MPU number (0x20) is set to ST in the command structure (step S106), and the process returns. If the MPU # in the command structure is between 0 and 15 or 0xff, the NMI issuing unit 31 checks the execution status of the corresponding MPU control block in the shared memory 5 (step S105), and Is dead or none, invalid M
The PU number (0x20) is set to ST in the command structure (step S106), and the process returns. If the execution status is busy (step S10
7), the NMI issuing unit 31 sets busy (0x10) to ST in the command structure (step S10).
8) Return. If the execution status is idle or run, an NMI can be issued.
The issuing unit 31 is configured to execute the MPU in the corresponding command table.
# Own MP in the MPU control block of MPU1 indicated by #
The flag in the command table corresponding to U # is reset to 1 (step S109), and the contents of the command structure are copied to the command table (step S11).
0). If the MPU # is 0xff, the flags of the command tables for all the MPUs 1 with MPU numbers 0 to 15 are set to 1, and the contents of the command structure are copied.

Next, the NMI issuing means 31 sets ST in the command table to 0xff (step S11).
1), an NMI is generated for the MPU 1 (step S112). Specifically, the MPU 1 writes the interrupt transaction data to the inter-processor interrupt generation port 208. Inter-processor interrupt generation port 2
08 is transferred via the system bus 4 to the interrupt notification destination MPU 1
Is taken into the buffer 201 of the SBC2 connected to
The data is decoded by the decoder 202 and set in the interrupt factor register 203. As a result, the NMI flip-flop 204 is set, the NMI signal 206 is driven, and an NMI is generated in the MPU 1.

In the MPU 1 that has received the NMI, the failure information collecting means 32 first saves the contents of the general-purpose registers except the k1 register in the local memory 3 (step S20).
1) Subsequently, the contents of the coprocessor register are saved in the local memory 3 using the general-purpose register (step S).
202), dump the contents of the TLB to the local memory 3 using the general-purpose register and the coprocessor register (step S203). Thereafter, the failure information collecting means 32
Initializes the contents of the coprocessor 10 and transfers control to the polling means 33.

The polling means 33 reads the interrupt cause register 203 of the SBC 2 (step S30).
1) Checking continues until an inter-processor NMI with an interrupt operation bit OP of 1 and an interrupt code of 64 to 79 occurs (step S302). If an inter-processor NMI has occurred, the inter-processor NMI
The control is transferred to the processing means 34.

The inter-processor NMI processing means 34 first resets the NMI interrupt code in the corresponding MPU 1 in the interrupt factor register 203 (step S40).
1), the MPU control block of MPU1 corresponding to the interrupt code is read (step S402). Next, the inter-processor NMI processing means 34 is
The command is recognized by reading the CMD in the command table written in (steps S403 to S407).

If the CMD is initialized (0x0f) in step S403, the inter-processor NMI processing means 34 initializes the NMI register save area (step S410). That is, all the general-purpose registers are set to 0, and the status register of the coprocessor register is initialized. Next, the inter-processor NMI processing means 34
Initializes the TLB 11 (step S411),
The B dump area is initialized (Step S412). Subsequently, the inter-processor NMI processing unit 34 sets the normal end (0x00) to ST in the command table (step S413), changes the execution status to idle (step S409), and ends the processing.

If the CMD is a register read (0x12) in step S404, the inter-processor NMI processing means 34 stores information in the register save area corresponding to REG # in the upper / lower 32-bit data area in the command table. (Step S414). However, if the register number is 0, as shown in FIG. 26, the CRC bit is set in the upper 32-bit data area, and the revision of the control program 30 is set in the lower 32-bit data area. As for the read-only registers (Random, Count, PRid),
It is read directly from the coprocessor 10 and set. Subsequently, the inter-processor NMI processing unit 34 sets the normal end (0x00) to ST in the command table (step S415), changes the execution status to idle (step S409), and ends the processing.

When the CMD is a register write (0x13), the inter-processor NMI processing means 34 outputs REG #
Is 0 (step S416), the control is transferred to step S419. If REG # is other than 0, N between processors
The MI processing means 34 sets the upper 32-bit data in the command table in the register save area corresponding to REG # in the register save area 37, and
The lower 32-bit data in the control block is set in the register save area (step S417). Subsequently, the inter-processor NMI processing unit 34 sets normal end (0x00) to ST in the command table (step S418), changes the execution status to idle (step S409), and ends the processing. Step S4
In step 19, it is checked whether or not the CRC bit is set. If the CRC bit is set, the inter-processor NMI processing means 34 performs a CRC for the byte length in the command table from the transfer address in the command table and returns the result. The CRC bit is set (step S420). Next, the inter-processor NMI processing means 34 checks whether or not the COUNT bit is set (step S421), and if it is not set, writes 0 data directly to the COUNT register (step S42).
2). Subsequently, the inter-processor NMI processing means 34
It is checked whether the LBCLR bit is set (step S423).
The B11 and the TLB dump area are initialized (step S424).

Next, the inter-processor NMI processing means 34
Checks whether the SCFCLR bit is set (step S425), and if so, initializes the control program area and invalidates the nvRAM (step S426). Next, between processors N
The MI processing means 34 sets normal termination (0x00) to ST in the command table (step S429),
It is checked whether or not the XEC bit has been set (step S433), and if not, the process ends. If the EXEC bit is set, the inter-processor NMI processing means 34 sets the Random, Count, PRid, Cache
All registers other than Err, EPC, and Status are restored from the register save area (step S431).
The MI is reset (step S432), the general-purpose registers other than kl, the EPC, and the status are restored (step S433), and the eret instruction is executed (step S43).
4), end the process.

In step S406, CMD is set to nvRAM
In the case of the read (0x02), the inter-processor NMI processing means 34 converts the data of the byte length from the local memory address indicated by the transfer address in the command table to the memory address indicated by the lower 32 bit data in the command table. The transfer is performed (step S435), the normal end (0x00) is set in the ST in the command table (step S436), and the process ends.

In step S407, CMD is set to nvRAM
In the case of a write (0x03), the inter-processor NMI processing means 34 transfers the data of the byte length from the memory address indicated by the lower data in the command table to the local memory address indicated by the transfer address in the command table. The transfer is performed (step S437), the normal end (0x00) is set in the ST in the command table (step S438), and the process ends.

If an exception is detected during command processing and the command processing cannot be continued, the inter-processor NMI processing means 34 sets an abnormal end code to ST and ends the processing.

When the CMD is other than the above five types,
The inter-processor NMI processing means 34 sets an invalid command in the ST of the MPU control block (step S40).
8) The flag of the command table is reset to 0, and the control is returned to the polling means 33.

After generating the NMI in step S112, the NMI issuing unit 31 of the NMI issuing source waits for ST in the command table to change to a value other than 0xff (step S113). If ST does not change from 0xff (step S114) and the execution status does not change to busy, the flag in the command table is cleared to 0 (step S114).
115), change the execution status of the MPU control block to de
It is rewritten to ad (step S116), a timeout (0x30) is set to ST in the command table (step S117), and the process ends. Step S1
If the ST in the command table changes from 0xff in step 13, the NMI issuing unit 31 copies the contents from the command table to the command structure (step S1).
18), end the process.

As described above, by using the communication function between NMI processors, the function of stopping software runaway and collecting registers at that time, the start / stop function of all MPUs at the time of debugging of the multiprocessor, the function of each MPU, Various functions such as a simultaneous setting function of the interval counter can be realized thereon.

[0073]

As described above, according to the present invention, the inter-processor interrupt generation port, the interrupt factor register, the NM
The provision of the I flip prop, the NMI flip preset port, the MPU control table, the NMI issuing means, the fault information collecting means, the inter-processor NMI processing means and the polling means has the following effects.

(1) Since an NMI interrupt can be generated in inter-processor communication, if one MPU can detect an abnormality in any software runaway, all MPUs are stopped by the NMI issuing means by the NMI issuing means. NM
The MPU that has received I can cause the MPU state at that time to be saved by the fault information collection unit and be transferred to the polling unit. After that, the MPU that detected the abnormality
However, when the NMI issuing unit issues an instruction using a command structure again, the information saved by the failure information collecting unit can be extracted from the MPU executing the polling unit.

(2) In the debugger of the multiprocessor system, when one processor executes a break instruction and enters the debugger, all MPUs are stopped by the NMI issuing means by the NMI issuing means, and the fault information collecting means stops the MPU. It is possible to save the register and shift to the polling means. Previously, the MPU could not be stopped when interrupts were disabled, such as during exception handling. After that, by specifying the rewritten register in the command structure and calling the NMI issuing means, it is possible to refer to and change the register states of all the MPUs from one MPU. Also, MPU #
Is specified as 0xff, REG # is specified as 0,
By passing the command structure in which the EXEC bit of the upper 32 bits data is set to 1 to the NMI issuing means, all MP
It is possible to instruct U to resume execution.

(3) In the command structure, 0xff is specified as MPU #, 0 is specified as REG #, data in which the COUNT bit and EXEC bit of the upper 32 bits are set to 1 is specified, and the NMI issuing means is specified. , It is possible to simultaneously set the timer counter existing for each MPU that has received the NMI by the inter-processor NMI processing means.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an SBC used in an inter-processor NMI communication device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an NMI communication device between processors according to the embodiment;

FIG. 3 shows an MPU in an inter-processor interrupt port in FIG.
FIG. 4 is a diagram showing the format of interrupt transaction data which is the format of an interrupt transaction output on the address of the system bus at the same time as the data to be written, and which is also the format taken into the buffer.

FIG. 4 is a diagram showing contents of an MPU control table placed in a shared memory in FIG. 2;

FIG. 5 is a diagram illustrating an execution status in FIG.

FIG. 6 is a diagram showing details of a command table in FIG. 4;

FIG. 7 is a diagram illustrating flags in a command table in FIG. 6;

FIG. 8 is a flowchart showing a process of a fault information collecting unit in FIG. 2;

FIG. 9 is a flowchart showing the processing of the polling means in FIG. 2;

FIG. 10 is a flowchart showing main processing of an inter-processor NMI processing means in FIG. 2;

FIG. 11 is a flowchart showing an initialization command process of the inter-processor NMI processing means in FIG. 2;

FIG. 12 is a flowchart showing a register read command process of an inter-processor NMI processing means in FIG. 2;

13 is a flowchart showing the first half of the register write command processing of the inter-processor NMI processing means in FIG. 2;

14 is a flowchart showing the latter half of the register write command processing of the inter-processor NMI processing means in FIG. 2;

FIG. 15 shows nv of the inter-processor NMI processing means in FIG. 2;
It is a flowchart which shows RAM read command processing.

FIG. 16 shows nv of the inter-processor NMI processing means in FIG. 2;
It is a flowchart which shows a RAM write command process.

FIG. 17 is a diagram showing the correspondence between the number of the MPU issuing the NMI and the interrupt code to be used in the inter-processor NMI communication device of the embodiment.

18 is a diagram illustrating types of commands stored in CMD in the command table in FIG.

19 is a diagram showing types of registers stored in REG # in the command table in FIG.

20 is a diagram showing a register list defined by REG # in FIG. 19;

21 is a diagram for explaining the contents of ST stored by the inter-processor NMI processing means in FIG. 2;

FIG. 22 is a flowchart showing a main process of an NMI issuing unit in FIG. 2;

FIG. 23 is a flowchart showing processing of an NMI issuing subroutine called in FIG. 22;

FIG. 24 is a diagram illustrating the contents of a command structure stored in the command table of FIG. 6;

FIG. 25 is a diagram for explaining the contents of an ST stored by the NMI issuing unit in FIG. 2;

FIG. 26 is a diagram illustrating writing to a register 0 in the inter-processor NMI communication device of the present embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microprocessor (MPU) 2 System bus controller (SBC) 3 Local memory 4 System bus 5 Shared memory 6 Local bus 10 Coprocessor 11 Address conversion table (TLB) 30 Control program 31 NMI issuing means 32 Fault information collecting means 33 Polling means 34 NMI processing means between processors 50 MPU control table 201 Buffer 202 Decoder 203 Interrupt cause register 204 NMI flip-flop 205 INT signal 206 NMI signal 207 NMI flip-preset port 208 Inter-processor interrupt occurrence port 209 Address control unit 210 NMI reset signal

Claims (5)

(57) [Claims] An MP having an edge triggered NMI terminal.
U, and an information processing apparatus in which a shared memory accessible from all the MPUs is connected via a system bus, wherein one of the MPUs has an interrupt code and an interrupt notification destination M
An inter-processor interrupt generation port that generates an interrupt transaction on the system bus by writing data designating a PU; and an interrupt factor register that is set or reset by receiving an interrupt transaction addressed to its own MPU from the system bus When an NMI factor is set in this interrupt factor register, the NMI signal is set and the interrupt notification destination MPU
To generate an NMI, resetting the NMI flip-flop by writing dummy data by the interrupt notification destination MPU, The driving of the NMI signal is stopped by the
A PU having an NMI flip preset port enabling the PU to receive the next NMI, an MPU control table provided on the shared memory, and a command table written in the MPU control table in the MPU issuing the interrupt transaction. NMI generating means for writing data indicating an NMI interrupt code addressed to the MPU specified by the table to the inter-processor interrupt generation port.
Fault information collecting means for saving PU fault information, inter-processor NMI processing means for executing the corresponding command processing with reference to the command in the command table, and checking the interrupt factor register, and setting the NMI factor. And a polling means for transferring control to said inter-processor NMI processing means and continuing to check if it has not been set. 2. The inter-processor NMI communication device according to claim 1, wherein the MPU includes a local memory dedicated to each MPU. 3. The inter-processor NMI communication device according to claim 1, wherein the MPU control table includes MPU control blocks for the number of MPUs, and each MPU control block includes a command table for the number of MPUs. 4. The NMI generating means writes data in which the EXEC bit of bit 31 of the upper 32 bits data is set to 1 to the register of register number 0 of the MPU, so that the other MPU 1 2. The inter-processor NMI communication device according to claim 1, wherein after returning all the saved registers, an instruction is given to start from the address indicated by the ErrorEPC register. 5. An MP having an NMI terminal for an edge trigger.
U, and an information processing apparatus in which a shared memory accessible from all the MPUs is connected via a system bus, wherein one of the MPUs has an interrupt code and an interrupt notification destination M
An inter-processor interrupt generation port that generates an interrupt transaction on the system bus by writing data designating a PU; and an interrupt factor register that is set or reset by receiving an interrupt transaction addressed to its own MPU from the system bus When an NMI factor is set in this interrupt factor register, the NMI signal is set and the interrupt notification destination MPU
To generate an NMI, resetting the NMI flip-flop by writing dummy data by the interrupt notification destination MPU, The driving of the NMI signal is stopped by the
A system bus controller having an NMI flip-flop preset port that enables the PU to accept the next NMI.