JPH01250078A - Testing method for integrated circuit element - Google Patents

Abstract

PURPOSE:To shorten a test time by performing only data processing continuously, then performing decision processing continuously, and eliminating the handling time of the integrated circuit element equivalently. CONSTITUTION:The application of a test signal to an (n-1)th integrated circuit element DUT to be measured is finished at time tn(0), the (n-1)th element DUT is detached from a contact part, and a waiting position where a decision result is expected is reached. An (n)th element DUT is inserted into the contact part at Cn time. Then a wait state is maintained until the decision result of the (n-1)th element DUT is obtained, i.e. for an Xn time. It is decided whether or not the (n-1)th element DUT is normal according to the decision result at time tn(2). Similarly, the test signal is applied from a testing device to the (n)th element DUT and the testing device performed data processing for a Dn time. Consequently, the handling time of the element DUT is eliminated equivalently and the test time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for testing integrated circuit devices during their manufacture.

Prior Art FIG. 2 shows a conventional integrated circuit device. An integrated circuit device to be measured (hereinafter referred to as DUT) (2) is inserted into a contact portion 4 of a handling device 3 using some kind of transport means 2, and is electrically connected to a test device 8 by a connecting wire 5. The controller 6 of the handling device 3 confirms that this connection has been completed, and transmits a test start signal from the interface 7 to the test device 8 to start the test.

The test device 8 generates an electrical signal from the test signal generator 10 under the control of the controller 9, and outputs the electrical signal to D via the connection line 2.
Supply to UTI. Then, the reading unit 11 reads the result.
The read data is given to the data processing unit 12, which determines whether the predetermined test items are good or bad. Below, similar tests are repeated for multiple test items, and one DUT is tested.
Complete the test for I. This test completion signal and pass/fail determination signal are given to the controller 6 of the handling device 3 via the interface 7. Based on this signal, the controller 6 takes out the tested DUTl from the contact section 4 and classifies it according to the results of the pass/fail determination. Thereafter, the controller 6 controls the transport means 2 to insert the next DUTI into the contact portion 4, electrically connects it to the test device 8, and issues a test start signal.

Incidentally, such a test is conducted according to the time diagram shown in FIG. In FIG. 3, n-1, n.

n+1 indicates the test time of the DUTI, Cn+1°Cn is the time for inserting the DUTI into the contact part 4 of the handling device 3 within the test time (so-called handling time), D n -1 (n), D n (1 )～(n)
, D n + 1 (1) to (n) are test items (1)
Application of test signal at ~(n) and data processing time, Mn -1(n), Mn(1) ~(n), Mn
+Hl) is the time for determining whether the test result is acceptable or not.

Problems to be Solved by the Invention As seen in this example, the conventional test method
is inserted into the handling device 3 (corresponding to Cn), and electrical signal application and data processing (corresponding to Dn) of the following test items are performed.
The test is completed by repeating the pass/fail judgment (corresponding to Mn). That is, after the DUTI is inserted, application of test signals, data processing, and pass/fail determination are continuously performed for each test item 1 to n. During this time, the test signal is constantly applied to the DUTI from the test device 8, and therefore the DUTI cannot be taken out from the handling device 3 during this time.

In this way, in the conventional testing method, a DUT cannot be taken out from the contact section 4 of the handling device 3 until all tests on that DUT are completed. In such a system, the only way to improve efficiency is to shorten the application of test signals, data processing Dn, determination time Mn, and handling time Cn.

The time for data processing Dn and pass/fail judgment Mn increases in proportion to the number of test items. Moreover, as integrated circuit devices become more complex, the number of test items increases. Therefore, this time cannot be shortened. On the other hand, handling time Cn
As the shape of integrated circuit elements becomes smaller and the number of pins increases, the length becomes longer, making it difficult to increase handling speed and prevent incorrect insertion.

This also has its limits, as it can lead to malfunctions.

Means for Solving the Problem In order to solve this problem, the present invention solves this problem by changing the processing of Dn and Mn from serially processing each item to processing each of them in batches. . That is, only data processing Dn(1) to (n) is performed continuously, and then determination processing Mn(1) to (n) is performed continuously.

Effect: With this configuration, the data processing time for test items and the pass/fail judgment time can be divided. This means that no test electrical signals are required during the pass/fail period and the DUT can therefore be removed from the contacts of the handling device.

Embodiment FIG. 1 is a time diagram showing a method for testing an integrated circuit device in an embodiment of the present invention. In FIG. 1, the insertion time Cn of the n-th DOT into the contact part is executed within the judgment time Mn-1 (1) to (n) of the n-1th DUT, and the time difference between them, that is, the waiting time, is The time is Xn. Similarly, for the n+1st DUT, the contact time Cn+
1 has been executed within the previous n-th determination time Mn(1) to (n), and its waiting time is Xn+1.

tn(0) to tn(2), tn+1(0
) to tn+02) indicate the test time divisions for the n-th and n+1-th DUTs. Next, a specific test method will be explained. First, at time tn(0), the application of the test signal to the (n-1)th DUT is finished, and the (n-1)th DUT is removed from the contact portion and enters a standby position awaiting the determination result. Meanwhile, the nth DUT is inserted into the contact at time Cn. Thereafter, the process waits for Xn time until the determination result of the (n-1)th DUT comes out.

According to the determination result at time tn(2), the waiting n-
Processing is performed to determine the quality of the first DUT. At the same time, a test signal is applied from the test device to the n-th DUT, and the test device executes data processing for Dn time. After this data processing is completed, that is, after tn+1(0), no test signal is required. Therefore, using this period, the n-th DUT is removed from the contact section and enters standby to wait for the determination result. From time tn+1(0), insertion of the (n+1)th DUT begins, and the same operation follows.

That is, from the test device 8 shown in FIG.
), the data processing completion signal for the n-1 DUT and the contact start signal are simultaneously sent to the handling device 3, and at time tn(2), the pass/fail judgment signal for the n-1 DUT and the test signal are sent to the handling device 3. The signal to apply and start data processing is issued at the same time. Similarly, time t n + 1 (0), t
At n + 1 (2), the same signal as above is sent to the handling device 3.

If a defect is determined within the pass/fail determination time, a defect determination signal is normally issued at that time. For example, if it is determined to be defective at the time of Mn-1(2), it is necessary to stop applying the test signal from the test device 8 until time tn(1) when the insertion of DUT n into the contact section 4 is completed. , therefore t n(
At the time point 1), the handling device 3 issues a signal indicating completion of insertion to the testing device 8. Therefore, in this case, the waiting time Xn due to waiting for the quality determination is eliminated.

Effects of the Invention According to the method for testing an integrated circuit device of the present invention, it is possible to equivalently eliminate the time required to handle the integrated circuit device, thereby shortening the test time and reducing the test cost.

[Brief explanation of the drawing]

FIG. 1 is a time diagram of a method for testing an integrated circuit device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional testing apparatus, and FIG. 3 is a time diagram of a conventional testing method. 1...DUT, 2...Transportation means, 3.
... Handling device, 4 ... Contact section, 5 ... Connection line, 6 ... Controller of handling device, 7 ... Interface, 8 ...Test device, 9...Test device interface, 10...Test signal generator, 11...Reader, 12... - Data processing section, Cn, Cn+1-...-n, insertion time of the n+1-th DUT into the contact section, Dn-1, Dn. [) n+1... Trial production signal application and afternoon-evening processing time, Mn - Hl) ~ (n), Mn (1) ~ Mn
(n), Mn + 1 (1)...DUT quality judgment time, Xn, Xn+1...Waiting time, t
n(0) to tn(2), tn+1(0) to tn+
1 (2>-...-= Test time break for n-th and n+1-th DUTs.

Claims (1)

[Claims] The contact insertion, removal, and movement times are controlled by receiving the contact time and its pass/fail judgment results from the test equipment in chronological order, and by returning the contact completion signal of the integrated circuit element under test from the handling equipment to the test equipment. A method for testing an integrated circuit device, characterized by: