JPH0124984Y2 - - Google Patents

Info

Publication number
JPH0124984Y2
JPH0124984Y2 JP1981174222U JP17422281U JPH0124984Y2 JP H0124984 Y2 JPH0124984 Y2 JP H0124984Y2 JP 1981174222 U JP1981174222 U JP 1981174222U JP 17422281 U JP17422281 U JP 17422281U JP H0124984 Y2 JPH0124984 Y2 JP H0124984Y2
Authority
JP
Japan
Prior art keywords
sweep
circuit
integrator
comparator
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981174222U
Other languages
Japanese (ja)
Other versions
JPS5882038U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17422281U priority Critical patent/JPS5882038U/en
Publication of JPS5882038U publication Critical patent/JPS5882038U/en
Application granted granted Critical
Publication of JPH0124984Y2 publication Critical patent/JPH0124984Y2/ja
Granted legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案はオシロスコープの掃引回路に使用する
シユミツト回路に関するものである。
[Detailed Description of the Invention] The present invention relates to a Schmitt circuit used in a sweep circuit of an oscilloscope.

遅延掃引機能を持つオシロスコープに於ては、
遅延掃引の開始を決める比較器を持ち、この比較
器は掃引毎に動作している。第1図に遅延掃引機
能を持つオシロスコープの掃引回路のブロツク図
を示す。1は主掃引回路制御フリツプフロツプ
(以下フリツプフロツプ1と称す)、2は主掃引信
号発生の積分器(以下積分器2と称す)、3は遅
延掃引開始制御比較器(以下比較器3と称す)、
4はシユミツト回路、5は遅延掃引回路制御フリ
ツプフロツプ(以下フリツプフロツプ5と称す)、
6は遅延掃引信号発生の積分器(以下積分器6と
称す)である。遅延掃引を行わない時、フリツプ
フロツプ5は他の制御手段によりRESETされ、
シユミツト回路4からトリガ信号を受けても動作
しない。しかし、この時でも比較器3とシユミツ
ト回路4は、フリツプフロツプ1の制御により積
分器2が積分してオシロスコープ管面を掃引する
たびに、比較動作を行つてフリツプフロツプ5の
トリガ端子を駆動する。この駆動信号の立上りは
非常に速い。第2図に従来例による比較器とシユ
ミツト回路の一例を示す。破線で囲んだ部分3が
第1図の比較器3に、破線で囲んだ部分4が第1
図のシユミツト回路4に相当する。9はトランジ
スタ、10は論理素子でTTL素子のインバータ、
11は抵抗で、正帰還をかけることによりヒステ
リシスを形成する。インバータ10にTTL素子
を用いることで、この出力の立上りは10nS以下
の高速となる。積分器2が動作するとシユミツト
回路4の出力は高速で変化し、これによりフリツ
プフロツプ5のトリガ端子の電流が高速に変化す
る。この高速で変化する電圧、電流の一部が積分
器2に流れ込むと積分器2の出力の直線性が損な
われ、オシロスコープ管面上で観測する波形に歪
を生じることになる。しかし従来回路においては
この高速で変化する電圧、電流を積分器2に流れ
込まないように抑制して、波形歪を小さくするこ
とは困難である。
For oscilloscopes with delayed sweep function,
It has a comparator that determines the start of the delayed sweep, and this comparator operates every sweep. Figure 1 shows a block diagram of the sweep circuit of an oscilloscope with a delayed sweep function. 1 is a main sweep circuit control flip-flop (hereinafter referred to as flip-flop 1); 2 is an integrator for generating a main sweep signal (hereinafter referred to as integrator 2); 3 is a delayed sweep start control comparator (hereinafter referred to as comparator 3);
4 is a Schmitt circuit; 5 is a delay sweep circuit control flip-flop (hereinafter referred to as flip-flop 5);
6 is an integrator (hereinafter referred to as integrator 6) for generating a delayed sweep signal. When not performing a delayed sweep, the flip-flop 5 is reset by other control means,
Even if it receives a trigger signal from the Schmitt circuit 4, it does not operate. However, even in this case, the comparator 3 and the Schmitt circuit 4 perform a comparison operation and drive the trigger terminal of the flip-flop 5 every time the integrator 2 integrates and sweeps the oscilloscope tube surface under the control of the flip-flop 1. This drive signal rises very quickly. FIG. 2 shows an example of a conventional comparator and Schmitt circuit. The part 3 surrounded by the broken line is the comparator 3 in FIG. 1, and the part 4 surrounded by the broken line is the first comparator 3.
This corresponds to the Schmitt circuit 4 shown in the figure. 9 is a transistor, 10 is a logic element and a TTL element inverter,
A resistor 11 forms hysteresis by applying positive feedback. By using a TTL element in the inverter 10, the output rises at a high speed of 10 nS or less. When the integrator 2 operates, the output of the Schmitt circuit 4 changes rapidly, which causes the current at the trigger terminal of the flip-flop 5 to change quickly. If part of this rapidly changing voltage and current flows into the integrator 2, the linearity of the output of the integrator 2 will be impaired, causing distortion in the waveform observed on the oscilloscope tube surface. However, in the conventional circuit, it is difficult to suppress the rapidly changing voltage and current from flowing into the integrator 2 and to reduce waveform distortion.

本考案はシユミツト回路に反転ゲート素子を用
い、必要に応じてシユミツト回路の動作を制御す
ることを特徴とし、その目的は波形歪みを軽減す
ることにある。
The present invention is characterized in that an inverting gate element is used in the Schmitt circuit, and the operation of the Schmitt circuit is controlled as necessary, and its purpose is to reduce waveform distortion.

第3図は本考案の実施例によるシユミツト回路
図であつて、9はトランジスタ、11は抵抗、1
2はNANDゲート、13は制御信号である。第
2図に示す比較器3の出力によりトランジスタ9
が駆動されても、NANDゲート12の制御信号
13が“0”の時は出力が変化しないので、積分
器2の出力には何ら影響を与えず、信号波形は歪
みを発生しない。従つて遅延掃引を行わない時に
は制御信号を“0”にすれば、波形歪みのない信
号をオシロスコープ管面上に表示することができ
る。
FIG. 3 is a Schmitt circuit diagram according to an embodiment of the present invention, in which 9 is a transistor, 11 is a resistor, 1
2 is a NAND gate, and 13 is a control signal. The output of the comparator 3 shown in FIG.
Even when driven, the output does not change when the control signal 13 of the NAND gate 12 is "0", so the output of the integrator 2 is not affected in any way, and the signal waveform is not distorted. Therefore, by setting the control signal to "0" when the delayed sweep is not performed, a signal without waveform distortion can be displayed on the oscilloscope tube surface.

なお、本実施例においては論理素子として
NANDゲートを用いたが、NORゲートあるいは
他の反転ゲート素子等、信号を制御できる素子で
あれば、種々応用可能なことは明白である。
In addition, in this example, as a logic element
Although a NAND gate was used, it is clear that any device that can control signals, such as a NOR gate or other inverting gate device, can be applied in various ways.

以上説明したごとく、本考案によれば、シユミ
ツト回路の論理素子にゲート回路を用いることに
より、簡便な方法でオシロスコープ管面上に歪み
のない波形表示を行うことができる。
As described above, according to the present invention, by using a gate circuit as a logic element of a Schmitt circuit, a distortion-free waveform can be displayed on the oscilloscope tube surface in a simple manner.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はオシロスコープの遅延掃引回路のブロ
ツク図、第2図は従来例による比較器、シユミツ
トの回路図、第3図は本発明の実施例によるシユ
ミツト回路図である。 1,5:フリツプフロツプ、2,6:積分器、
3:比較器、4:シユミツト回路、9:トランジ
スタ、10:インバータ、11:抵抗、12:
NANDゲート、13:制御信号。
FIG. 1 is a block diagram of a delay sweep circuit of an oscilloscope, FIG. 2 is a circuit diagram of a conventional comparator and Schmitt, and FIG. 3 is a Schmitt circuit diagram according to an embodiment of the present invention. 1, 5: flip-flop, 2, 6: integrator,
3: Comparator, 4: Schmitt circuit, 9: Transistor, 10: Inverter, 11: Resistor, 12:
NAND gate, 13: control signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 遅延機能を有するオシロスコープの遅延掃引回
路において、主掃引信号を発生する積分器と、該
積分器出力と遅延掃引の開始点を決める電圧とを
比較する比較器と、該比較器出力がベースに加え
られるトランジスタと、このトランジスタのコレ
クタが、入力端子の一つに接続された複数入力端
子を持つ反転論理ゲート素子と、このゲート素子
の出力端子から前記トランジスタのベースに接続
された抵抗とを有し、前記反転論理ゲート素子の
他の入力端子からの制御信号によつて動作、非動
作が制御されることを特徴とする前記オシロスコ
ープ遅延掃引回路の掃引制御回路用のシユミツト
回路。
In a delayed sweep circuit of an oscilloscope with a delay function, an integrator that generates the main sweep signal, a comparator that compares the output of the integrator with a voltage that determines the starting point of the delayed sweep, and the comparator output is added to the base. an inverting logic gate element having a plurality of input terminals, the collector of which is connected to one of the input terminals, and a resistor connected from the output terminal of the gate element to the base of the transistor. , a Schmitt circuit for a sweep control circuit of the oscilloscope delay sweep circuit, wherein operation and non-operation are controlled by a control signal from another input terminal of the inverting logic gate element.
JP17422281U 1981-11-25 1981-11-25 schmitt circuit Granted JPS5882038U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17422281U JPS5882038U (en) 1981-11-25 1981-11-25 schmitt circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17422281U JPS5882038U (en) 1981-11-25 1981-11-25 schmitt circuit

Publications (2)

Publication Number Publication Date
JPS5882038U JPS5882038U (en) 1983-06-03
JPH0124984Y2 true JPH0124984Y2 (en) 1989-07-27

Family

ID=29966192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17422281U Granted JPS5882038U (en) 1981-11-25 1981-11-25 schmitt circuit

Country Status (1)

Country Link
JP (1) JPS5882038U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5131157A (en) * 1974-09-10 1976-03-17 Oki Electric Ind Co Ltd
JPS5311944B2 (en) * 1973-09-17 1978-04-25

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50146455U (en) * 1974-05-20 1975-12-04
JPS5311944U (en) * 1976-07-13 1978-01-31
JPS5558737U (en) * 1978-10-14 1980-04-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5311944B2 (en) * 1973-09-17 1978-04-25
JPS5131157A (en) * 1974-09-10 1976-03-17 Oki Electric Ind Co Ltd

Also Published As

Publication number Publication date
JPS5882038U (en) 1983-06-03

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