JPH01243564A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01243564A JPH01243564A JP63069454A JP6945488A JPH01243564A JP H01243564 A JPH01243564 A JP H01243564A JP 63069454 A JP63069454 A JP 63069454A JP 6945488 A JP6945488 A JP 6945488A JP H01243564 A JPH01243564 A JP H01243564A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- metal substrate
- solder
- ceramic
- room temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000000919 ceramic Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 13
- 239000010949 copper Substances 0.000 abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に金属製基板表面上に電気回路
形成用のセラミック基板を接合材により接続する構造の
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a structure in which a ceramic substrate for forming an electric circuit is connected to the surface of a metal substrate using a bonding material.
半導体装置の半導体ペレット接続方式としては、特公昭
５９−９７６に記載されているように、放熱用金属基板
に銀ペースト等を介して半導体ペレットを接続するもの
があるが、半導体と金属との熱膨張率の違いによる処理
熱歪の影響に問題がある。As described in Japanese Patent Publication No. 59-976, there is a method for connecting semiconductor pellets for semiconductor devices, in which semiconductor pellets are connected to a metal substrate for heat dissipation via silver paste, etc.; There is a problem with the effects of processing thermal strain due to differences in expansion coefficients.
この他に金属基板を使用するもので高周波増幅用モジエ
ールとして、第６図に示すようにセラミック材を一部に
用いる構造が知られている。In addition, as a high-frequency amplification module that uses a metal substrate, a structure in which a ceramic material is partially used as shown in FIG. 6 is known.
このモジ為−ル１は第７図を参照し、金属基板２上に接
合材３を介してストリップライン及び印刷抵抗（いずれ
も図示せず）を有するセラミック基板４と基板にあけた
透孔１３内でトランジスタチップ９とを固定したもので
ある。セラミック基板４とトランジスタチップ９との間
はポンディングワイヤ１０により接続している。また、
セラきツク基板４上には同じ工程で接合材（図示せず）
を介してチップコンデンサ８及び外部取出し用リード５
を固定して高周波整合回路を形成している。Referring to FIG. 7, this module 1 includes a ceramic substrate 4 having strip lines and printed resistors (none of which are shown) on a metal substrate 2 via a bonding material 3, and a through hole 13 formed in the substrate. The transistor chip 9 is fixed inside. A bonding wire 10 connects the ceramic substrate 4 and the transistor chip 9. Also,
A bonding material (not shown) is applied on the ceramic board 4 in the same process.
Chip capacitor 8 and external lead 5 via
is fixed to form a high frequency matching circuit.
このようなモジ為−ル１は第６図でその一部断面を示す
ように、オーバーコートレジン７で埋め込み、その上を
樹脂製キャップ６で被冠するととにより完成品となる。As shown in a partial cross section in FIG. 6, such a module 1 is filled with an overcoat resin 7 and then covered with a resin cap 6 to complete the finished product.
このような構造の従来のモジエール構造では次の欠点が
あることが本発明者によって明らかとなった。The inventors have found that the conventional mosier structure of this type has the following drawbacks.
すなわち、従来のモジエールｌはセラミック基板４と金
属基板２とを接合固定する接合材３は一般的に鉛・錫ハ
ンダが用いられ両者の接合は約２００Ｃ以上の温度下で
行われる。That is, in the conventional modier 1, lead-tin solder is generally used as the bonding material 3 for bonding and fixing the ceramic substrate 4 and the metal substrate 2, and the bonding of the two is performed at a temperature of about 200C or higher.
したがって、セラミック基板４と金属基板２のハンダ材
は後に室温に復帰すると、ハンダ材の溶融点温度から室
温に至る温度差及び、セラミック基板４と金属基板２の
熱膨張係数差の積による残留応力がセラきツク基板４と
金属基板２の両者に印加されることにより、バイメタル
効果により両者は変形して「反り」を発生する。この反
り量は基板寸法が大きいほど顕著である。このような金
属基板２の反りはモジエール１０セット実装時に放熱性
の劣化を来たし、温度上昇による信頼性を低下させると
いう結果を招くことになった。Therefore, when the solder material of the ceramic substrate 4 and the metal substrate 2 returns to room temperature later, residual stress is caused by the product of the temperature difference from the melting point temperature of the solder material to the room temperature and the difference in the coefficient of thermal expansion between the ceramic substrate 4 and the metal substrate 2. is applied to both the ceramic substrate 4 and the metal substrate 2, thereby deforming them due to the bimetallic effect and causing "warpage". The amount of warpage becomes more significant as the substrate size increases. Such warpage of the metal substrate 2 causes a deterioration in heat dissipation when 10 sets of modules are mounted, resulting in a decrease in reliability due to temperature rise.
したがって本発明の目的は熱膨張係数の異なるセラミッ
ク基板と金属基板を高温下で接合し、両者が室温復帰後
に生じる金属製基板の反りを防止することにある。Therefore, an object of the present invention is to bond a ceramic substrate and a metal substrate, which have different coefficients of thermal expansion, at a high temperature, and to prevent the metal substrate from warping that occurs after both have returned to room temperature.
この様な目的を達成するために不発明はセラミック基板
と金属基板を高温下で接合した後に室温復帰後に生じる
変形（反り）と逆方向：／Ｃあらかじめ金属基板を変形
（反り）加工するものである。To achieve this purpose, the invention is to deform (warp) the metal substrate in advance in a direction opposite to the deformation (warp) that occurs after returning to room temperature after bonding the ceramic substrate and the metal substrate at high temperature. be.
セラミック基板と金属基板を高温で接合材により接合し
た後に室温復帰させた時に発生する金属基板の反りは、
接合前の金属基板が数百ミクロンの範囲であればセラミ
ック基板を一定量反らせた状態で応力バランスを取る。The warping of the metal substrate that occurs when the ceramic substrate and metal substrate are brought back to room temperature after being bonded with a bonding material at high temperature is as follows.
If the metal substrate before bonding is in the range of several hundred microns, the stress is balanced by warping the ceramic substrate by a certain amount.
したがって所定外形のセラミック基板と金属製基板の組
合せであれば実験的に両者を接合し室温ｌ復帰後のセラ
ミック基板の反り量を求め、この実験的に求めたセラミ
ック基板の反りと逆方向でセラミック基板の反りと同量
に反り加工を金属基板に対し行なうととＫより、両者の
接合・室温復帰後のセラミック・金属製基板は平面の接
合面をもつ外形となる。Therefore, in the case of a combination of a ceramic substrate and a metal substrate with a predetermined external shape, we experimentally join them together, determine the amount of warpage of the ceramic substrate after returning to room temperature, and then If the metal substrate is warped by the same amount as the substrate, the ceramic/metal substrate will have a flat bonded surface after they are bonded and returned to room temperature.
第１図乃至第５図は、本発明の一実施例を示すものであ
って金属基板を変形加工し、半導体装置を組立てる一部
工程の断面図である。FIGS. 1 to 5 show an embodiment of the present invention, and are sectional views showing a part of the process of deforming a metal substrate and assembling a semiconductor device.
この実施例の第１図において示される金属基板２はＣｕ
（鋼）製の板で表面にＮｉ （＝ツケル）めっきを施し
である。The metal substrate 2 shown in FIG. 1 of this embodiment is made of Cu.
(Steel) plate with Ni plating on the surface.
この金属基板２をプレス機等を使用して第２図に示すよ
うに変形（反り）１５の加工を行う。This metal substrate 2 is processed to be deformed (warped) 15 as shown in FIG. 2 using a press machine or the like.
この反り１５は、これと同一形状の金属板（膨張率：１
７Ｘ１０−６．ビッカース硬度１２０Ｈｖ。This warp 15 is a metal plate of the same shape (expansion coefficient: 1
7X10-6. Vickers hardness 120Hv.
０ＦＣｕ ）とセラミック板（膨張率：６５Ｘ１０−６
）とを予め鉛・錫ハンダ付けし、室温に復帰後に生じる
セラミック基板の反りと反対方向でセラミック基板の反
り量と同じ量に設計しである。0FCu) and ceramic plate (expansion coefficient: 65X10-6
) are soldered with lead and tin in advance, and designed to have the same amount of warpage as the ceramic board in the opposite direction to the warp of the ceramic board that occurs after returning to room temperature.
第２図で示した金属基板２０反り１５の内面に鉛・錫ペ
ーストハンダ３ａを、たとえばスクリーン印刷法により
セラミック基板４とほぼ同面積に塗布しておく。一方、
第３図を参照し、セラミック基板７の金属基板２と接合
させる面にハンダ付性の良好な銅または銀パラジウム等
３ｂの厚膜印刷による焼付を施したセラミック基板４を
前記鉛・錫ペーストハンダの粘着性を利用して仮り止め
する。Lead-tin paste solder 3a is applied to the inner surface of the warp 15 of the metal substrate 20 shown in FIG. 2 in approximately the same area as the ceramic substrate 4 by, for example, screen printing. on the other hand,
Referring to FIG. 3, a ceramic substrate 4 on which the surface of the ceramic substrate 7 to be bonded to the metal substrate 2 is baked by thick film printing of copper, silver palladium, etc. 3b having good solderability is attached to the ceramic substrate 4 using the lead-tin paste solder. Temporarily fasten using the adhesive properties of
なお、このセラミック基板４０反対生面上には、予め銅
メタライズ配線パターン１１が施され、この上にチタン
酸バリウム等のチップコンデンサ８を鉛・錫ペーストハ
ンダ１２を介して接続（仮り止め）し、また、セラミッ
ク基板４の一部にあけた透孔１３を通して銅ヒートシン
ク１４を介してトランジスタチップ９を接続（仮り止め
）しておくものである。Note that a copper metallized wiring pattern 11 is applied in advance on the opposite raw surface of the ceramic substrate 40, and a chip capacitor 8 made of barium titanate or the like is connected (temporarily fixed) thereon via a lead/tin paste solder 12. Further, the transistor chip 9 is connected (temporarily fixed) through a copper heat sink 14 through a through hole 13 made in a part of the ceramic substrate 4.
これらの仮結合体（第３図）を、たとえば２００Ｃに加
熱したヒートブロック（図示せず）上に載置し、ハンダ
を融かしてセラミック基板４と金属基板２とをハンダ接
合し、同時にセラミック基板で各素子を基板の配線パタ
ーンにハンダ接合する。These temporary bonded bodies (Fig. 3) are placed on a heat block (not shown) heated to, for example, 200C, the solder is melted, the ceramic substrate 4 and the metal substrate 2 are soldered together, and at the same time Each element is soldered to the wiring pattern of the ceramic board.
ハンダ付は完了後自然冷却して加熱した部分が室温に復
帰すると、熱膨張係数の大である金属基板２と熱膨張係
数の比較的小であるセラミック基板４には残留熱応力が
生じ、第４図に示すように、。After soldering is completed, when the heated part is naturally cooled and returned to room temperature, residual thermal stress is generated in the metal substrate 2, which has a large coefficient of thermal expansion, and the ceramic substrate 4, which has a relatively small coefficient of thermal expansion. As shown in Figure 4.
金属基板（ヘッダ）２は見かけ上、平らな面でセラミッ
ク基板４と接合することになる。The metal substrate (header) 2 is apparently joined to the ceramic substrate 4 with a flat surface.
このあと、セラミック基板上で配線と素子の端子間をＡ
ｕ（金）ワイヤによるボンディングを行ない、次いで第
５図に示すようにこれら素子を埋め込むようにシリコー
ンゴムレジン７を塗布し、さらにプラスチックキャップ
６を被冠してシリコーンゴムレジン７で固定することで
、前掲第６図に示すような半導体装置が完成する。なお
、第１図乃至第５図においてはセラミック基板上の素子
の配置は簡略した模型図であって、第６図、第７図にそ
のまま対応するものではない。After this, connect the wiring and the terminals of the element to A on the ceramic substrate.
Bonding is performed using U (gold) wires, and then silicone rubber resin 7 is applied to embed these elements as shown in FIG. , a semiconductor device as shown in FIG. 6 above is completed. Note that the arrangement of elements on the ceramic substrate in FIGS. 1 to 5 is a simplified model diagram, and does not directly correspond to FIGS. 6 and 7.
本発明は前記実施例に限定されるものではなく、使用さ
れる基板部材、接合材、素子の種類、配置等は特許請求
の範囲を逸脱しない範囲で種々に変更することができる
。The present invention is not limited to the embodiments described above, and the substrate members, bonding materials, types of elements, arrangement, etc. used can be variously changed without departing from the scope of the claims.
本発明は、以上説明したように構成されているので以下
に記載のような効果を奏する。Since the present invention is configured as described above, it produces the effects described below.
すなわち、半導体装置を製造する側においては、セラミ
ック基板を２分割以上に分割して金属製基板の反り量を
低減する方式より組立の合理化が容易となり、部品点数
の少ない高信頼度の半導体装置を提供することができる
。In other words, on the side of manufacturing semiconductor devices, it is easier to streamline assembly than the method of dividing the ceramic substrate into two or more parts to reduce the amount of warpage of the metal substrate, and it is possible to manufacture highly reliable semiconductor devices with a small number of parts. can be provided.
また半導体装置を使用する側においては、金属製基板が
水平であることにより、半導体装置を実装する放熱基板
の設計が容易となる。Furthermore, on the side where the semiconductor device is used, since the metal substrate is horizontal, it is easy to design a heat dissipation substrate on which the semiconductor device is mounted.
第１図乃至第５図は本発明の一実施例を示す半導体装置
の組立プロセスにおける一部工程断面図である。
第６図は金属基板上に組み立てられた半導体装置の一例
を示す縦断面図、
第７図は同じくその内部を示す平面図である。
！・・・モジエール、２・・・金属基板、３・・・接合
材（ハンダ）、４・・・セラミック基板、５・・・リー
ド、６・・・キャップ、７・・・レジン、８・・・コン
デンサチップ、９・・・トランジスタチップ、ｌＯ・・
・ワイヤ、１１・・・配線、１２・・・ハンダ、１３・
・・透孔、１４・・化−トシンク、１５・・・反り。
第 １ 図
、バ
第２図
第４図1 to 5 are partial step sectional views in an assembly process of a semiconductor device showing an embodiment of the present invention. FIG. 6 is a longitudinal sectional view showing an example of a semiconductor device assembled on a metal substrate, and FIG. 7 is a plan view showing the inside thereof. ! ... Mosier, 2... Metal substrate, 3... Bonding material (solder), 4... Ceramic substrate, 5... Lead, 6... Cap, 7... Resin, 8...・Capacitor chip, 9... Transistor chip, lO...
・Wire, 11... Wiring, 12... Solder, 13.
...Through hole, 14...Curved sink, 15...Warp. Figure 1, Figure 2, Figure 4
Claims (1)
構成部品を配置し、上記セラミック基板の他主面と金属
基板とを重ねて接合材を介し加熱処理により接合するに
あたって、上記セラミックと上記金属との熱膨張率の差
異による接合後常温復帰時の接合面の変形と逆の方向に
上記金属基板にあらかじめ変形加工を施すことを特徴と
する半導体装置の製造方法。1. When an electronic component including a semiconductor element is placed on one main surface of a ceramic substrate, and the other main surface of the ceramic substrate and a metal substrate are stacked and bonded by heat treatment via a bonding material, the ceramic and the above-mentioned A method for manufacturing a semiconductor device, characterized in that the metal substrate is previously deformed in a direction opposite to the deformation of the bonding surface upon return to room temperature after bonding due to a difference in coefficient of thermal expansion with the metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63069454A JPH01243564A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63069454A JPH01243564A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01243564A true JPH01243564A (en) | 1989-09-28 |
Family
ID=13403110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63069454A Pending JPH01243564A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01243564A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007273682A (en) * | 2006-03-31 | 2007-10-18 | Dowa Holdings Co Ltd | Heat sink and manufacturing method therefor |
| JP2014167990A (en) * | 2013-02-28 | 2014-09-11 | Canon Inc | Method of producing packaging member and method of manufacturing electronic component |
-
1988
- 1988-03-25 JP JP63069454A patent/JPH01243564A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007273682A (en) * | 2006-03-31 | 2007-10-18 | Dowa Holdings Co Ltd | Heat sink and manufacturing method therefor |
| JP2014167990A (en) * | 2013-02-28 | 2014-09-11 | Canon Inc | Method of producing packaging member and method of manufacturing electronic component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4835120A (en) | Method of making a multilayer molded plastic IC package | |
| US5367435A (en) | Electronic package structure and method of making same | |
| US4381602A (en) | Method of mounting an I.C. chip on a substrate | |
| JP3176307B2 (en) | Mounting structure of integrated circuit device and method of manufacturing the same | |
| JP2949490B2 (en) | Semiconductor package manufacturing method | |
| JP2814966B2 (en) | Semiconductor device | |
| JPH05129473A (en) | Resin-sealed surface-mounting semiconductor device | |
| JP5417572B2 (en) | Chip resistor and manufacturing method thereof | |
| JP2756184B2 (en) | Surface mounting structure of electronic components | |
| JP3119630B2 (en) | Multilayer circuit board for semiconductor chip module and method of manufacturing the same | |
| US6486551B1 (en) | Wired board and method of producing the same | |
| JPH06291165A (en) | Flip chip connecting construction | |
| JPH01243564A (en) | Manufacture of semiconductor device | |
| JP2622862B2 (en) | Substrate for mounting electronic components with leads | |
| JPH07297320A (en) | Bga type semiconductor device | |
| JPH03283646A (en) | Semiconductor device | |
| JPH0927563A (en) | Manufacture of semiconductor device | |
| JPH08167676A (en) | Semiconductor device | |
| JPH0462961A (en) | Semiconductor device and manufacture thereof | |
| KR100246848B1 (en) | Land grid array and a semiconductor package having a same | |
| JPH04329659A (en) | Hybrid integrated circuit device and manufacture thereof | |
| JPH0685165A (en) | Semiconductor device and manufacture thereof | |
| JP2675077B2 (en) | Lead frame for semiconductor device | |
| JPH05144989A (en) | Production of lead frame and method for bonding semiconductor element using the frame | |
| JPH01100957A (en) | Hybrid ic |