JP2007273682A - Heat sink and manufacturing method therefor - Google Patents

Heat sink and manufacturing method therefor Download PDF

Info

Publication number
JP2007273682A
JP2007273682A JP2006096766A JP2006096766A JP2007273682A JP 2007273682 A JP2007273682 A JP 2007273682A JP 2006096766 A JP2006096766 A JP 2006096766A JP 2006096766 A JP2006096766 A JP 2006096766A JP 2007273682 A JP2007273682 A JP 2007273682A
Authority
JP
Japan
Prior art keywords
heat sink
plating
solder
copper
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006096766A
Other languages
Japanese (ja)
Other versions
JP5011587B2 (en
Inventor
Hisatoshi Araki
久寿 荒木
Yoshinori Suzuki
芳典 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dowa Holdings Co Ltd
Original Assignee
Dowa Holdings Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dowa Holdings Co Ltd filed Critical Dowa Holdings Co Ltd
Priority to JP2006096766A priority Critical patent/JP5011587B2/en
Publication of JP2007273682A publication Critical patent/JP2007273682A/en
Application granted granted Critical
Publication of JP5011587B2 publication Critical patent/JP5011587B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heat sink of copper or copper alloy on which a semiconductor substrate is mounted by solder jointing, capable of stably preventing formation of voids, caused by Cu diffusion when Pb-free solder is used and defective solder wettability, for proper bonding characteristics to a power module case. <P>SOLUTION: In a semiconductor substrate 7 is mounted by solder jointing 2 on a heat sink 1 of copper or copper alloy, Ni plating is applied on a surface, on which the semiconductor substrate is mounted (substrate-mounting surface) and on the surface (rear surface) on the opposite side of it. The fluctuation width in the Ni plating thickness at five points, including the proximity of an end surface and a central part of plate surface, is 2.0 μm or smaller, on the substrate mounting surface and the rear surface, as well. Those, especially having an end face on which no Ni plating is applied, become appropriate objects. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子を搭載する基板(本明細書において「半導体基板」という)に接合される銅または銅合金からなる放熱板であって、板面にNiめっきが施されているものに関する。   The present invention relates to a heat radiating plate made of copper or a copper alloy bonded to a substrate on which a semiconductor element is mounted (referred to as “semiconductor substrate” in this specification), and the plate surface is subjected to Ni plating.

半導体素子から発生する熱を効率よく放散させるための手段として、半導体基板を熱伝導性の良い材料からなる「放熱板」の上に搭載する手段が広く採用されている。   As means for efficiently dissipating heat generated from a semiconductor element, means for mounting a semiconductor substrate on a “heat radiating plate” made of a material having good thermal conductivity is widely adopted.

図1に、放熱板の上に半導体基板を搭載した半導体モジュールの構成例を模式的に示す。アルミナや窒化アルミニウムなどのセラミックスからなる絶縁基板5の表面には銅パターン4が形成されており、その反対側の面には銅板などからなる導体層6が形成されている。絶縁基板5と銅パターン4および導体層6が一体となって半導体基板3を構成している。半導体基板3の銅パターン4が形成された面には、例えばはんだ層2を介して半導体素子7が搭載されている。銅パターン4と半導体素子7の間には必要に応じてAlなどの導電材料からなるリード線8が取り付けられ、回路を構成する。一方、半導体基板3の導体層6が形成された面は、はんだ層2を介して放熱板1と接合されている。   FIG. 1 schematically shows a configuration example of a semiconductor module in which a semiconductor substrate is mounted on a heat sink. A copper pattern 4 is formed on the surface of an insulating substrate 5 made of a ceramic such as alumina or aluminum nitride, and a conductor layer 6 made of a copper plate or the like is formed on the opposite surface. The insulating substrate 5, the copper pattern 4, and the conductor layer 6 are integrated to constitute the semiconductor substrate 3. On the surface of the semiconductor substrate 3 on which the copper pattern 4 is formed, for example, a semiconductor element 7 is mounted via a solder layer 2. A lead wire 8 made of a conductive material such as Al is attached between the copper pattern 4 and the semiconductor element 7 as necessary to constitute a circuit. On the other hand, the surface of the semiconductor substrate 3 on which the conductor layer 6 is formed is bonded to the heat sink 1 via the solder layer 2.

絶縁基板5は、半導体素子と同程度の小さい熱膨張係数を必要とすることから、例えばパワー半導体用絶縁基板としてはセラミックスで作られる。これに対し、放熱板1は直接半導体素子と接合されるものではないため半導体素子と同等の小さい熱膨張係数までは要求されず、むしろ熱伝導性の方が優先される。このため、放熱板には熱伝導性の良好な銅、銅合金、アルミニウムまたはアルミニウム合金の板が主として使用される。また、この放熱板は、はんだ付け時に基板との熱膨脹差に起因して「反り」が発生するため、この反りを相殺する目的で、予めプレス成形により逆方向に反り付けを行っておく手段が採られることがある。   Since the insulating substrate 5 requires a coefficient of thermal expansion as small as that of the semiconductor element, for example, the insulating substrate for power semiconductor is made of ceramics. On the other hand, since the heat sink 1 is not directly joined to the semiconductor element, it is not required to have a small thermal expansion coefficient equivalent to that of the semiconductor element. Rather, thermal conductivity is given priority. For this reason, a plate of copper, copper alloy, aluminum or aluminum alloy having good thermal conductivity is mainly used as the heat sink. In addition, since this heat sink causes "warping" due to the difference in thermal expansion with the substrate during soldering, there is a means to warp in the reverse direction by press molding in advance for the purpose of offsetting this warpage. May be taken.

銅または銅合金からなる放熱板はNiめっきが施されて使用されることが多い。その理由として、以下のことが挙げられる。
(i)はんだ接合面では、はんだ層中へのCu原子の拡散を防止することが望ましい。特にPbフリーはんだ(例えばSn−Ag系など)ではCuの拡散によるボイドが発生しやすく、はんだクラックの発生や放熱性低下の要因になる。Niめっきを施すとはんだ層へのCuの拡散が抑制される。
(ii)半導体基板搭載面の裏面をアルミニウムの放熱フィンに取り付けて使用される場合が多く、その場合、放熱板表面に酸化物被膜が形成されると放熱性が低下する。Niめっきを施すと耐食性が向上し、このような酸化物被膜の形成が抑制される。
A heat sink made of copper or a copper alloy is often used after being plated with Ni. The reason is as follows.
(I) It is desirable to prevent diffusion of Cu atoms into the solder layer on the solder joint surface. In particular, in Pb-free solder (for example, Sn—Ag series), voids due to diffusion of Cu are likely to occur, which causes generation of solder cracks and deterioration of heat dissipation. When Ni plating is applied, diffusion of Cu into the solder layer is suppressed.
(Ii) In many cases, the rear surface of the semiconductor substrate mounting surface is attached to an aluminum radiating fin, and in that case, if an oxide film is formed on the surface of the radiating plate, the heat dissipation is reduced. When Ni plating is applied, the corrosion resistance is improved and the formation of such an oxide film is suppressed.

放熱板用途では、Niめっきの後にプレスを行うと、プレス打ち抜きで端面が露出し耐食性が劣化し、またプレスキズが発生しやすいため、従来、プレス打ち抜きや反り付け後にNiめっきを施していた。   In heatsink applications, if the press is performed after Ni plating, the end face is exposed by press punching, the corrosion resistance is deteriorated, and press scratches are likely to occur. Conventionally, Ni plating is applied after press punching or warping.

特開2000−311973号公報JP 2000-311973 A 特開2000−219996号公報Japanese Patent Laid-Open No. 2000-219996

ところが、従来、Niめっきを施した銅または銅合金製の放熱板においても、Pbフリーはんだ使用時のCu拡散に起因したボイドの形成が問題になることがあり、期待されたNiめっきの効果が十分発揮されないことがあった。また、通常のPb入りはんだを使用した場合においても、はんだ濡れ性が低下する場合も見られた。さらに、放熱板をパワーモジュールの樹脂ケースにはめ込んで使用する際、放熱板の端面がNiめっきによって平滑化されているために、ケースとの良好な接合性が確保できない場合もあった。   However, conventionally, even in a heat sink made of copper or copper alloy plated with Ni, void formation due to Cu diffusion when using Pb-free solder may be a problem, and the expected effect of Ni plating is In some cases, it was not fully demonstrated. Further, even when ordinary Pb-containing solder was used, the solder wettability was sometimes reduced. Furthermore, when the heat sink is used by being fitted in the resin case of the power module, the end face of the heat sink is smoothed by Ni plating, so that there may be a case where good bondability with the case cannot be ensured.

一方、プレス打抜き前にNiめっきを施すと、特許文献2のような板厚1mm未満のバスバーや電極端子材での単なる打ち抜きでは問題とならなかった端面の露出による耐食性の劣化や表面キズの発生が、板厚1mm以上の放熱板においては悪影響を及ぼすことがあった。
本発明はコストを抑えながらこれらの問題の解消を図ることを目的とする。
On the other hand, when Ni plating is performed before press punching, deterioration of corrosion resistance and generation of surface scratches due to exposure of the end face, which was not a problem with mere punching with a bus bar or electrode terminal material having a thickness of less than 1 mm as in Patent Document 2, However, a heat sink having a thickness of 1 mm or more may have an adverse effect.
An object of the present invention is to solve these problems while suppressing costs.

発明者はNiめっきを施したにもかかわらず、はんだ層にボイドが形成されることがある原因を究明すべく、多くのサンプルを調査してきた。その結果、Niめっき厚さが薄い部分では、Cuの拡散を十分抑止することができないために、結局Cuがはんだ層にまで達し、ボイドが生じることがわかった。そこで、Niめっき厚さを十分に厚くする対策をとったところ、Cu拡散に伴うボイドの発生は回避された。しかし、プレスによる反り付けを施していても、あらかじめ付けていた反り付け量が変動し、狙いの反り付け量から外れてしまうことが多々あった。その原因について種々検討したところ、めっき工程の時にかかる熱や電着応力、放熱板の中心付近と端面付近とのめっき厚さの差、およびプレスの反り付け後に電気めっきが施されていることなどが要因として挙げられ、特に前記めっき厚さの差の制御が重要であることがわかってきた。すなわち、単にめっき厚さを厚くするだけでは、反り付け量変動の対策にならない。また、Niめっきを厚くすることはコスト増につながるため、好ましいとは言えない。
さらに、はんだ濡れ性の低下はNiめっき厚さが不均一であることが原因となりうることを突き止めた。
The inventor has investigated many samples in order to investigate the cause of the formation of voids in the solder layer despite the Ni plating. As a result, it was found that in the portion where the Ni plating thickness is thin, Cu diffusion cannot be sufficiently suppressed, so that Cu eventually reaches the solder layer and a void is generated. Therefore, when measures were taken to sufficiently increase the Ni plating thickness, generation of voids due to Cu diffusion was avoided. However, even when warping is applied by a press, the amount of warping previously applied fluctuates and often deviates from the target amount of warping. After various investigations about the cause, heat and electrodeposition stress applied during the plating process, difference in plating thickness between the center and end face of the heat sink, and electroplating after press warping, etc. As a factor, it has been found that control of the difference in the plating thickness is particularly important. That is, simply increasing the plating thickness does not provide a measure for fluctuations in the amount of warping. Further, it is not preferable to make the Ni plating thick because it leads to an increase in cost.
Furthermore, it has been found that the decrease in solder wettability can be caused by non-uniform Ni plating thickness.

そこで、さらに詳細な研究を進めた結果、Niめっき厚さのバラツキを小さくした放熱板において、コストを抑えながらボイド発生の問題を解消できることがわかった。同時に、はんだ濡れ性不良についても大幅に改善されることが確認された。   Therefore, as a result of further detailed research, it was found that the problem of void generation can be solved while suppressing costs in a heat sink having a small variation in Ni plating thickness. At the same time, it was confirmed that the solder wettability was greatly improved.

すなわち本発明では、半導体基板をはんだ接合により搭載するための板厚1〜5mmの銅または銅合金製の放熱板において、半導体基板を搭載する面(基板搭載面)およびその反対側の面(裏面)にNiめっきが施されており、板面を鉛直方向から見た場合に、ある端面に平行な方向をX方向、それに直角な方向をY方向と定め、X方向に対向するそれぞれの端面から4mmの距離にあり且つY方向中央の板面上位置をそれぞれX1、X2とし、Y方向に対向するそれぞれの端面から4mmの距離にあり且つX方向中央の板面上位置をそれぞれY1、Y2とし、直線X1−X2と直線Y1−Y2の交点における板面上位置をPとしたとき、Niめっき厚さに関し、基板搭載面あるいはさらに裏面が下記(1)式を満たす放熱板が提供される。
ΔA≦2.0μm ……(1)
ここで、ΔA(μm):X1、X2、Y1、Y2、Pの各位置におけるNiめっき厚さの最大値と最小値の差(絶対値)である。
That is, according to the present invention, in a heat sink made of copper or copper alloy having a thickness of 1 to 5 mm for mounting a semiconductor substrate by solder bonding, the surface on which the semiconductor substrate is mounted (substrate mounting surface) and the opposite surface (back surface) ) Is plated with Ni, and when the plate surface is viewed from the vertical direction, the direction parallel to a certain end surface is defined as the X direction, and the direction perpendicular thereto is defined as the Y direction, from each end surface facing the X direction. The positions on the plate surface at a distance of 4 mm and in the center in the Y direction are X 1 and X 2 , respectively, and the positions on the plate surface at a distance of 4 mm from the respective end surfaces facing in the Y direction are Y 1 respectively. , Y 2 , where P is the position on the plate surface at the intersection of the straight line X 1 -X 2 and the straight line Y 1 -Y 2 , regarding the Ni plating thickness, A heat sink to fill is provided.
ΔA ≦ 2.0μm (1)
Here, ΔA (μm) is a difference (absolute value) between the maximum value and the minimum value of the Ni plating thickness at each position of X 1 , X 2 , Y 1 , Y 2 , and P.

1、X2、Y1、Y2、Pの各位置におけるNiめっき厚さの平均値が、基板搭載面、あるいはさらに裏面において0.1〜10μmの範囲になるように調整することが好ましい。また、Niめっきが施されていない端面を有する放熱板が提供される。 It is preferable to adjust so that the average value of the Ni plating thickness at each position of X 1 , X 2 , Y 1 , Y 2 , and P is in the range of 0.1 to 10 μm on the substrate mounting surface or further on the back surface. . Moreover, the heat sink which has an end surface to which Ni plating is not given is provided.

このような放熱板は、Niめっきが施された銅または銅合金の条材をプレス打抜きする工程、あるいはさらに反り付けを施す工程を有する製造法によって実現できる。前記プレス打ち抜きする工程および反り付けを施す工程を順送金型プレスにより行い、その順送金型内での材料の移送を、当該金型内に設けられたサイドガイドにより材料をリフトさせて行うことにより、材料と下型との移送時の接触を回避すれば、プレス時におけるNiめっき面へのキズの発生が抑止できる。   Such a heat sink can be realized by a manufacturing method having a step of press punching a strip of copper or copper alloy on which Ni plating is applied, or a step of further warping. The press punching step and the warping step are performed by a progressive die press, and the material is transferred in the progressive die by lifting the material with a side guide provided in the die. If the contact between the material and the lower mold during transportation is avoided, generation of scratches on the Ni plating surface during pressing can be suppressed.

さらに、前記プレス打ち抜きする工程または反り付けを施す工程の後に、打ち抜かれた板材をアルカリ、アルコールまたは炭化水素系の洗浄液を用いて脱脂した後、速やかに乾燥させる工程を有する製造法によると、例えば素地の露出した端面の酸化による変色が防止でき、かつ基板搭載面についてロジン系フラックスを用いてはんだ付けを行ったとき、はんだ濡れ面積が95%以上となるような、はんだ濡れ性の良好な放熱板が提供できる。   Furthermore, according to the manufacturing method having a step of drying quickly after degreasing the punched plate material using an alkali, alcohol or hydrocarbon-based cleaning liquid after the press punching step or the warping step, for example, Dissipation of the exposed end surface of the substrate due to oxidation, and heat dissipation with good solder wettability, such that when the substrate mounting surface is soldered using a rosin flux, the solder wetting area is 95% or more. A board can be provided.

本発明によれば、より少ないNi付着量によって、Pbフリーはんだ使用時のボイドの形成や、Pb入りはんだ使用によるはんだ濡れ性の低下を安定して防止することが可能になった。また、熱伝導率の低いNiの付着量が過剰にならないようにすることは、放熱性の向上につながる。さらに、Niめっきが施されていない端面を有する放熱板によって、パワーモジュール樹脂ケースとの接合性も向上した。Ni付着量が節約できること、および連続めっきラインを用いてNiめっきを施すことができることによって、製造コストも低減でき、かつめっき後にプレス打ち抜きを行った後に残存する加工油の洗浄を適正に行うことによって、良好なはんだ濡れ性を維持することが可能となる。   According to the present invention, it is possible to stably prevent the formation of voids when using Pb-free solder and the decrease in solder wettability due to the use of Pb-containing solder with a smaller amount of Ni adhesion. Also, keeping the amount of Ni deposited with low thermal conductivity from becoming excessive leads to improved heat dissipation. Furthermore, the heat dissipation plate having the end face not subjected to Ni plating also improved the bondability with the power module resin case. By saving the amount of Ni deposited and being able to apply Ni plating using a continuous plating line, the manufacturing cost can also be reduced, and the remaining processing oil can be properly washed after press punching after plating. It is possible to maintain good solder wettability.

また、反り量の変動を起こすNiめっきを反り付け工程より前に施すことや、Niめっき厚さのバラツキを小さくした放熱板とすることで、プレス直後からの反り変動量を小さくすることが可能となる。板厚1〜5mmの条材をプレスするときに生じてしまう有害なキズの発生も抑えられる。プレス打ち抜きを行った後に残存する加工油の洗浄を適正に行うことによって、良好なはんだ濡れ性が維持できるとともに、Niめっきの無い打ち抜き端面においても変色を防止することが可能になる。   In addition, it is possible to reduce the amount of warpage fluctuation immediately after pressing by applying Ni plating that causes fluctuation of the warpage amount before the warping process or by using a heat sink with reduced variation in Ni plating thickness. It becomes. Generation | occurrence | production of the harmful damage | wound which arises when pressing the strip | belt material of board thickness 1-5mm is also suppressed. By appropriately cleaning the processing oil remaining after the press punching, it is possible to maintain good solder wettability and to prevent discoloration even at the punched end surface without Ni plating.

図2にパワーモジュール用放熱板の板面におけるNiめっき厚さ測定位置を模式的に示す。発明者らは、プレス打抜き後に電気Niめっきを施して製造された従来の放熱板において、表面のNiめっき厚さを詳細に調べてきた。その結果、特に放熱板の中央部と端面付近の間でめっき厚さの差が生じやすいことがわかった。すなわち、基板搭載面、裏面とも、図2に示される中央位置Pと端面近傍位置X1、X2、Y1、Y2のめっき厚さの差が大きくなる傾向にある。したがって、これらの差を小さくすることが重要である。 FIG. 2 schematically shows the Ni plating thickness measurement position on the plate surface of the power module heat sink. The inventors have investigated the Ni plating thickness of the surface in detail in a conventional heat sink manufactured by applying electric Ni plating after stamping. As a result, it has been found that a difference in plating thickness tends to occur particularly between the central portion of the heat sink and the vicinity of the end face. That is, on both the substrate mounting surface and the back surface, the difference in plating thickness between the center position P and the end surface vicinity positions X 1 , X 2 , Y 1 , Y 2 shown in FIG. 2 tends to increase. Therefore, it is important to reduce these differences.

前記端面近傍のX1、X2、Y1、Y2の板面上の位置は、それぞれの端面からの距離が4mmで、かつ、X1およびX2についてはY方向中央の位置、Y1およびY2についてはX方向中央の位置とする。なお、放熱板には用途に応じて部分的に穴が開けられたり、はんだ層厚さを確保するための突起が形成されたりすることがある。もし、上記の位置が穴や突起などの加工部位に当たっている場合は、前記加工部位の近傍(概ね4mm以内)で、端面から4mmの距離にある板面上の位置を替わりに測定位置とすればよい。 The positions of X 1 , X 2 , Y 1 , and Y 2 on the plate surface in the vicinity of the end surface are 4 mm from the respective end surfaces, and for X 1 and X 2 , the position in the center in the Y direction, Y 1 And Y 2 are set at the center in the X direction. In addition, a hole may be partially made in a heat sink according to a use, or the processus | protrusion for ensuring a solder layer thickness may be formed. If the above position hits a processing part such as a hole or a projection, the position on the plate surface at a distance of 4 mm from the end surface in the vicinity of the processing part (approximately within 4 mm) is used as the measurement position instead. Good.

また中央Pの板面上の位置は、直線X1−X2(図2のLX)と直線Y1−Y2(図2のLY)の交点に設定する。もし、Pの位置が穴や突起などの加工部位に当たっている場合は、前記加工部位の近傍(概ね4mm以内)の板面上位置を替わりに測定位置とすればよい。
このように設定した板面上の位置X1、X2、Y1、Y2、PについてNiめっき厚さを測定することにより、放熱板としてのNiめっき厚さのバラツキを良好に評価することができる。
The position of the center P on the plate surface is set at the intersection of the straight line X 1 -X 2 (L X in FIG. 2) and the straight line Y 1 -Y 2 (L Y in FIG. 2). If the position of P hits a processing site such as a hole or a protrusion, the position on the plate surface in the vicinity of the processing site (approximately within 4 mm) may be used as the measurement position instead.
By measuring the Ni plating thickness for the positions X 1 , X 2 , Y 1 , Y 2 , and P on the plate surface set in this way, the variation of the Ni plating thickness as the heat sink should be satisfactorily evaluated. Can do.

発明者の詳細な調査によれば、このようにして定めた測定位置について、Niめっき厚さを測定し、得られた各測定点のNiめっき厚さが前記(1)式を満たしているとき、基板搭載面では、Niめっき厚さのバラツキに伴うはんだ層中でのボイドの発生や、はんだ濡れ性不良が安定して防止される。また裏面では、銅または銅合金より熱伝導率の低いNiの付着量が均一化されることにより放熱性も均一化される。さらに、基板搭載面および裏面とも、必要なNiめっき厚さに対し過剰にNi付着量を多くする必要がなくなり、材料コスト低減および放熱性の向上が実現できる。
なお、無電解めっきは厚さのバラツキの制御は容易であるが、コストやめっき応力が大きく、本発明では電気めっきを適用することが好ましい。
According to the inventor's detailed investigation, the Ni plating thickness is measured at the measurement position thus determined, and the Ni plating thickness at each of the obtained measurement points satisfies the formula (1). On the substrate mounting surface, generation of voids in the solder layer due to variations in the Ni plating thickness and solder wettability are stably prevented. In addition, on the back surface, heat dissipation is also uniformed by uniformizing the adhesion amount of Ni having a lower thermal conductivity than copper or copper alloy. Furthermore, it is not necessary to increase the amount of Ni adhesion excessively with respect to the required Ni plating thickness on both the substrate mounting surface and the back surface, and material costs can be reduced and heat dissipation can be improved.
Although electroless plating can easily control the thickness variation, the cost and plating stress are large, and it is preferable to apply electroplating in the present invention.

Niめっき厚さの測定は、後述するように、蛍光X線膜厚測定器、電解式膜厚測定器または断面観察により行う。なお、X1、X2、Y1、Y2、Pの各位置におけるNiめっき厚さの平均値が0.1〜10μmの範囲になるように調整されていることが望ましい。Niめっき厚さが薄すぎるとCuの拡散を十分に抑止することができず、過剰に厚いとコスト増につながり、また、めっき厚のバラツキを本発明の範囲に抑えることがだんだん難しくなる。Niめっき厚さの平均値は3〜7μmであることが一層好ましい。 The Ni plating thickness is measured by a fluorescent X-ray film thickness measuring device, an electrolytic film thickness measuring device, or cross-sectional observation, as will be described later. Incidentally, X 1, X 2, Y 1, Y 2, it is desirable that the average value of the Ni plating thickness at each position P is adjusted to the range of 0.1 to 10 [mu] m. If the Ni plating thickness is too thin, Cu diffusion cannot be sufficiently suppressed, and if it is excessively thick, the cost increases, and it becomes increasingly difficult to suppress the variation in plating thickness within the scope of the present invention. The average value of the Ni plating thickness is more preferably 3 to 7 μm.

このような均一性の高いNiめっきは、プレス打抜きを行う前の「条」の状態で予めNiめっきを施す方法により実現できる。特に、銅または銅合金の条材の両面にNiめっきを施すことができ、また片面毎に独立しためっき厚制御が可能な連続電気めっきラインに条材を通板することによって、各々の面に目的に応じたNiめっき付着量を確保することも可能である。   Such highly uniform Ni plating can be realized by a method in which Ni plating is performed in advance in a “strip” state before press punching. In particular, Ni plating can be applied to both sides of a copper or copper alloy strip, and each strip can be passed through a continuous electroplating line capable of independent plating thickness control on each side. It is also possible to ensure a Ni plating adhesion amount according to the purpose.

めっき後は、プレス打抜きを含む加工工程を経ることによって基板搭載面および裏面にNiめっき層を形成した放熱板が構築される。先にNiめっきを施してから打ち抜くことにより、Niめっきが施されていない端面を有する放熱板が得られる。これにより、パワーモジュール樹脂ケースとの接合性を同時に向上させることができる。   After plating, a heat sink having Ni plating layers formed on the substrate mounting surface and the back surface is constructed through processing steps including press punching. By punching after performing Ni plating first, the heat sink which has an end surface in which Ni plating is not given is obtained. Thereby, bondability with a power module resin case can be improved simultaneously.

プレス工程では、条から部品を切り離す打抜きの他、必要に応じて突起を形成したり、あるいはさらに、はんだ接合時の冷却過程で熱膨張に起因する「反り」を相殺するための「逆反り」を形成したりすることができる。これらの加工は順送金型を用いることにより効率的に実施できる。   In the pressing process, in addition to punching to separate parts from the strip, protrusions are formed as necessary, or “reverse warping” to offset “warping” caused by thermal expansion in the cooling process during soldering. Can be formed. These processes can be carried out efficiently by using a progressive die.

プレス工程のあとには、打ち抜かれた板材をアルカリ、アルコールまたは炭化水素系の洗浄液を用いて脱脂した後、速やかに乾燥させる工程を実施することが望ましい。これにより、端面の耐変色性や良好なはんだ濡れ性を安定して確保することができる。ここでいうアルカリは例えば苛性ソーダや苛性カリ、無機ソーダ塩類等の物質である。炭化水素系の物質としてはパラフィン、アセトン、ジクロロメタン等が挙げられる。   After the pressing step, it is desirable to perform a step of quickly drying after degreasing the punched plate material using an alkali, alcohol or hydrocarbon-based cleaning liquid. Thereby, the discoloration resistance of the end surface and good solder wettability can be secured stably. The alkali here is a substance such as caustic soda, caustic potash or inorganic soda salt. Examples of the hydrocarbon-based substance include paraffin, acetone, dichloromethane and the like.

本発明の放熱板には板厚1〜5mmの銅(純度99.96%以上)または銅合金を使用する。銅合金としてはCu−Fe−P系、Cu−Sn系などが挙げられる。加工ピンでリング状の窪みを付けてその中央に突起を隆起させる方法で突起を形成させる上で、HVが70〜200好ましくは80〜150程度の硬さに調整された板材をプレス成形に供することが望ましい。また、放熱板は矩形のものが多いが、少なくともその1辺の長さが50mm以上、さらには100mmを超えるものが好ましく、本発明の効果をよく利用できる。   The heat sink of the present invention uses copper (purity 99.96% or more) or copper alloy having a thickness of 1 to 5 mm. Examples of the copper alloy include Cu—Fe—P and Cu—Sn. When forming a protrusion by attaching a ring-shaped depression with a processing pin and raising the protrusion at the center, a plate material adjusted to a hardness of about 70 to 200, preferably about 80 to 150, is used for press molding. It is desirable. In addition, the heat sink is often rectangular, but at least one side is preferably 50 mm or longer, and more than 100 mm, and the effects of the present invention can be used well.

得られた本発明の放熱板に半導体基板を搭載する際には、通常用いられるSn−Pb系はんだ、またはSn−3.5Ag、Sn−5Sb等のPbフリーはんだが適用できる。例えば、板面に所定量のフラックスとはんだを配置し、その上に複数の半導体基板を設置した状態ではんだの融点より概ね50〜100℃高い温度の炉(例えばN2+H2雰囲気)に入れ、十分にはんだが溶けてから炉外に出して放冷する。 When a semiconductor substrate is mounted on the obtained heat sink of the present invention, Sn-Pb solder that is usually used, or Pb-free solder such as Sn-3.5Ag and Sn-5Sb can be applied. For example, a predetermined amount of flux and solder are placed on the plate surface, and a plurality of semiconductor substrates are placed thereon, and then placed in a furnace (eg, N 2 + H 2 atmosphere) at a temperature approximately 50 to 100 ° C. higher than the melting point of the solder. After the solder is sufficiently melted, take it out of the furnace and let it cool.

板厚3mm、幅235mmのCu−0.07Fe−0.02P合金(焼鈍後、約25%の冷間圧延を行ったもの)の条材について、表面をアルカリおよび電解脱脂したのち、連続電気Niめっきラインに通板することにより両面にNiめっきを施した。両面ともNiめっき付着量が平均3.5μm厚さとなるように条件を設定した。
一方、比較材として、Niめっきを施していないことだけが上記と異なる条材を用意した。
A strip of a Cu-0.07Fe-0.02P alloy (thickness of about 25% after annealing) having a thickness of 3 mm and a width of 235 mm was subjected to continuous electric Ni after the surface was alkali and electrolytically degreased. Ni plating was performed on both surfaces by passing through a plating line. Conditions were set so that the average amount of Ni plating adhered to both surfaces was 3.5 μm.
On the other hand, as a comparative material, a strip material different from the above was prepared only in that Ni plating was not applied.

これらの条材を用いて、順送金型により「突起形成」、「打抜き」、「逆反り形成」を行い、100×70mmの放熱板をそれぞれ約500個製造した。突起は、基板搭載面の半導体基板搭載位置に加工ピンでリング状の窪みを付けてその中央に突起を隆起させる方法で高さ約150μmのものを合計12個形成し、逆反りはプレス直後において反り量がX方向に300μm、Y方向に200μmとなるように金型およびプレス条件を設定した。また、比較材を用いたものについては、その後、バッチ処理にて従来の手法でNiめっきを施した。   Using these strips, “projection formation”, “punching”, and “reverse warp formation” were performed using a progressive die, and about 500 heat sinks each having a size of 100 × 70 mm were manufactured. A total of 12 protrusions having a height of about 150 μm are formed by attaching a ring-shaped depression with a processing pin at the semiconductor substrate mounting position on the substrate mounting surface and raising the protrusion at the center, and the reverse warping occurs immediately after pressing. The mold and pressing conditions were set so that the warpage amount was 300 μm in the X direction and 200 μm in the Y direction. Moreover, about the thing using a comparative material, Ni plating was given by the conventional method by batch processing after that.

反り量は、水平面上に置かれた被測定材料(板状部品)の表面についてダイヤルゲージ、レーザー変位計、接触式表面形状測定器などで測定することができるが、接触式表面形状測定器での測定が好ましい。「直線に沿って測定する」とは、水平面上に置かれた被測定材料の表面を鉛直方向から見たときの直線上を測定することをいう。反り量の値は、基準となる水平面に対する表面の相対的高さの、測定範囲内における最大値と最小値の差である。ここではダイヤルゲージを用いて測定した。   The amount of warpage can be measured with a dial gauge, laser displacement meter, contact type surface shape measuring instrument, etc. on the surface of the measured material (plate-shaped part) placed on a horizontal plane. Is preferable. “Measuring along a straight line” means measuring a straight line when the surface of the material to be measured placed on a horizontal plane is viewed from the vertical direction. The value of the amount of warpage is the difference between the maximum value and the minimum value within the measurement range of the relative height of the surface with respect to the reference horizontal plane. Here, measurement was performed using a dial gauge.

また、本発明のプレス加工後の製品については、炭化水素系の洗浄液(具体的にはノルマルパラフィンを98.5%溶媒中に含むもの)で5分間超音波洗浄を施した後、速やかにブロワー乾燥をおこなった。   In addition, the product after press working of the present invention is subjected to ultrasonic cleaning for 5 minutes with a hydrocarbon-based cleaning liquid (specifically, containing 98.5% normal paraffin in a solvent), and then quickly blower Drying was performed.

得られた放熱板から無作為に各10個のサンプルを抽出し、図1に示したa〜eおよびf〜jの各板面上位置(それぞれ前記P、Y1、Y2、X1、X2に対応)におけるNiめっき厚さを蛍光X線膜厚測定器により測定した。具体的には、それぞれの測定位置にX線を照射して表面から反射してきた蛍光X線を検出器で検出し、標準Ni薄膜試料であらかじめ作成してある検量線と検出されたX線強度からNiめっき膜厚を算出した。 Ten samples are randomly extracted from the obtained heat sink, and the positions on the plate surfaces a to e and f to j shown in FIG. 1 (P, Y 1 , Y 2 , X 1 , respectively) Ni plating thickness at X 2 to the corresponding) was measured by a fluorescent X-ray film thickness meter. Specifically, fluorescent X-rays reflected from the surface by irradiating each measurement position with X-rays are detected by a detector, and a calibration curve prepared in advance with a standard Ni thin film sample and detected X-ray intensity. From this, the Ni plating film thickness was calculated.

その結果、Niめっきを施した後に打抜きを行って作製した本発明品はいずれも、Niめっき厚さが基板搭載面および裏面とも前記(1)式を満たしており、めっき厚さのバラツキが安定して非常に小さくなっていた。これに対し、比較材を用いてプレス後にNiめっきを行って作製した従来品では、全てのサンプルとも、基板搭載面または裏面の少なくとも一方で前記(1)式を満たしておらず、Niめっき厚のバラツキが大きかった。
表1には、あるサンプルについてのNiめっき厚さ測定結果を例示する。
As a result, all the products of the present invention manufactured by punching after Ni plating satisfy the above formula (1) on both the substrate mounting surface and the back surface, and the variation in plating thickness is stable. And it was very small. On the other hand, in the conventional product manufactured by performing Ni plating after pressing using a comparative material, all samples did not satisfy the above formula (1) on at least one of the substrate mounting surface and the back surface, and the Ni plating thickness The variation was large.
Table 1 illustrates Ni plating thickness measurement results for a certain sample.

Figure 2007273682
Figure 2007273682

表1のデータに見られるように、従来品は特に中央位置と端面位置のいずれかのめっき厚さの差が大きいことがわかる。他の9個のサンプルも概ねこれに近い状況である。   As can be seen from the data in Table 1, it can be seen that the conventional product has a particularly large difference in plating thickness between the center position and the end face position. The other nine samples are almost similar to this.

次に、上記本発明品と従来品からさらに各10個のサンプルを抽出して反り付け直後から定常状態の反り量になるまでの反り変動量について調査した。
本発明品についてはプレス反り付け後にX方向300μm、Y方向200μmの目標値で反りをつけた後に洗浄工程を行い、その後トータルで7日間放置したものについて反り量を測定し、さらに7日間放置して反り量を測定することにより、反り量の変動が生じなくなったこと、すなわち定常状態の反り量になったことを確認した。なお、放置した放熱板の端面に変色等は観察されなかった。
また、比較材を用いた従来品はプレス反り付け直後にX方向300μm、Y方向200μmの目標値で反りをつけてからバッチ処理で電気Niめっきを施した後に反り量を測定し、さらに7日間放置して反り量を測定することにより、定常状態の反り量になったことを確認した。
Next, 10 samples each were extracted from the product of the present invention and the conventional product, and the amount of warpage variation from immediately after the warpage to the amount of warpage in a steady state was investigated.
For the products of the present invention, after applying warp to the press, warping was performed with target values of 300 μm in the X direction and 200 μm in the Y direction, and then the cleaning process was performed. By measuring the amount of warpage, it was confirmed that the amount of warpage no longer fluctuated, that is, the amount of warpage was in a steady state. In addition, discoloration etc. were not observed on the end surface of the left heat sink.
In addition, the conventional product using the comparative material is warped at the target value of 300 μm in the X direction and 200 μm in the Y direction immediately after the warping of the press, and then the amount of warpage is measured after performing the electric Ni plating by batch processing, and further 7 days The amount of warpage was measured by leaving it alone, and it was confirmed that the amount of warpage was in a steady state.

上記のX方向300μm、Y方向200μmの目標値で反りを付けた直後の実測によるX方向の反り量をδX0、Y方向の反り量をδY0とし、定常状態の反り量になったときの実測によるX方向の反り量をδX1、Y方向の反り量をδY1とするとき、反り変動を下式により求めた。
X方向の反り変動量(%)=|δX0−δX1|/δX0×100
Y方向の反り変動量(%)=|δY0−δY1|/δY0×100
その結果、本発明では全てのサンプルにおいて、X方向およびY方向の反り変動量が7%以下であった。これに対し、比較材を用いた従来品では、3個のサンプルにおいてX方向、Y方向の少なくとも1方の反り変動量が7%を超えていた。
When the warpage amount in the X direction is δ X0 , the warpage amount in the Y direction is δ Y0 and the warpage amount in the Y direction is δ Y0 immediately after the warpage is applied with the target values of 300 μm in the X direction and 200 μm in the Y direction. when the warp amount in the X direction and [delta] X1, Y direction warpage [delta] Y1 by actual measurement, the warp variation was calculated by the following equation.
X direction warpage variation (%) = | δ X0 −δ X1 | / δ X0 × 100
Y direction warpage variation (%) = | δ Y0 −δ Y1 | / δ Y0 × 100
As a result, in the present invention, the amount of warpage fluctuation in the X direction and the Y direction was 7% or less in all samples. In contrast, in the conventional product using the comparative material, the amount of warpage fluctuation in at least one of the X direction and the Y direction exceeded 7% in three samples.

次に、半導体基板として、窒化アルミニウム基板の表面に銅パターンを形成した厚さ約0.3mmのもので、放熱板側のはんだ接合面(図1の導体層6に相当する表面)が70×50mmのものを用意した。これを本発明品の放熱板および従来品の放熱板からそれぞれ無作為に抽出した各100個の放熱板にはんだ接合により搭載した。はんだはロジン系フラックスを含有したSn−3.5Ag合金ペーストを用意し、これを放熱板の所定位置に通常の手法ではんだ層厚さに応じた適正量を塗布し、その上に半導体基板を載せて300℃、N2+H2雰囲気の炉に装入し、約10分経過後に炉外に出して放冷した。 Next, a semiconductor substrate having a thickness of about 0.3 mm with a copper pattern formed on the surface of an aluminum nitride substrate, the solder joint surface on the heat sink side (the surface corresponding to the conductor layer 6 in FIG. 1) is 70 ×. A 50 mm one was prepared. This was mounted by soldering on 100 heat sinks each randomly extracted from the heat sink of the present invention and the heat sink of the conventional product. For the solder, prepare Sn-3.5Ag alloy paste containing rosin-based flux, apply an appropriate amount according to the thickness of the solder layer to the specified position of the heat sink by a normal method, and put the semiconductor substrate on it It was placed in a furnace at 300 ° C. and N 2 + H 2 atmosphere, and after about 10 minutes, it was taken out of the furnace and allowed to cool.

はんだ接合を終えた試料のうち、各50個について、基板接合部の超音波写真を撮影し、得られた写真を画像解析することによって、はんだ層にボイドが発生した箇所、およびはんだ濡れ性が低下してはんだ濡れ面積が95%以下の箇所(以下これらを「はんだ欠陥」という)があるかどうかを調べた。その結果、本発明品の放熱板を用いた試料には、50個全てにおいてはんだ欠陥は認められなかった。これに対し従来品の放熱板を用いた試料には、50個中5個にはんだ欠陥(実用上許容される程度のものも含む)が見つかった。   Of the 50 samples that have been soldered, an ultrasonic photograph of the board joint is taken for each of the 50 samples, and the resulting photograph is subjected to image analysis, so that voids are generated in the solder layer and the solder wettability is reduced. It was investigated whether or not there were places where the solder wetted area was 95% or less (hereinafter referred to as “solder defects”). As a result, no solder defects were observed in all 50 samples using the heat sink of the present invention. On the other hand, in the sample using the heat sink of the conventional product, 5 out of 50 solder defects (including those practically acceptable) were found.

また、はんだ接合を終えた試料のうち残りの各50個について、所定のパワーモジュールの樹脂ケース中に装入する操作を試みた。その結果、本発明品の放熱板は端面にNiめっきが施されていないので、端面にもNiめっきが施されている従来品の放熱板と比べ、端面と樹脂ケースとの間に安定した強い接合力が得られた。   Further, an operation was attempted in which the remaining 50 samples among the samples after solder bonding were inserted into a resin case of a predetermined power module. As a result, since the heat sink of the product of the present invention is not Ni-plated on the end face, it is stable and strong between the end face and the resin case compared to the heat sink of the conventional product in which the end face is also Ni-plated. Bonding force was obtained.

放熱板の上に半導体基板を搭載した半導体モジュールの構成例を模式的に示した断面図。Sectional drawing which showed typically the example of a structure of the semiconductor module which mounted the semiconductor substrate on the heat sink. 放熱板の板面におけるめっき厚さ測定箇所を模式的に示した図。The figure which showed typically the plating thickness measurement location in the board surface of a heat sink.

Claims (10)

半導体基板をはんだ接合により搭載するための板厚1〜5mmの銅または銅合金製の放熱板において、半導体基板を搭載する面(以下「基板搭載面」という)およびその反対側の面(以下「裏面」という)にNiめっきが施されており、板面を鉛直方向から見た場合に、ある端面に平行な方向をX方向、それに直角な方向をY方向と定め、X方向に対向するそれぞれの端面から4mmの距離にあり且つY方向中央の板面上位置をそれぞれX1、X2とし、Y方向に対向するそれぞれの端面から4mmの距離にあり且つX方向中央の板面上位置をそれぞれY1、Y2とし、直線X1−X2と直線Y1−Y2の交点における板面上位置をPとしたとき、Niめっき厚さに関し、少なくとも基板搭載面が下記(1)式を満たす放熱板。
ΔA≦2.0μm ……(1)
ここで、ΔA(μm)は、X1、X2、Y1、Y2、Pの各位置におけるNiめっき厚さの最大値と最小値の差、である。
In a heat sink made of copper or copper alloy having a thickness of 1 to 5 mm for mounting a semiconductor substrate by solder bonding, a surface on which the semiconductor substrate is mounted (hereinafter referred to as “substrate mounting surface”) and an opposite surface (hereinafter referred to as “substrate mounting surface”). When the plate surface is viewed from the vertical direction, the direction parallel to a certain end surface is defined as the X direction, and the direction perpendicular to the Y direction is defined as the Y direction. X1 and X2 are positions on the plate surface at a distance of 4 mm from the end surface of the Y-axis, and Y1 is a position on the plate surface at a distance of 4 mm from each end surface facing the Y-direction and at the center in the Y-direction. , Y2, and a position on the plate surface at the intersection of the straight line X1-X2 and the straight line Y1-Y2, where P is the heat sink that satisfies at least the following expression (1) with respect to the Ni plating thickness.
ΔA ≦ 2.0μm (1)
Here, ΔA (μm) is a difference between the maximum value and the minimum value of the Ni plating thickness at each position of X1, X2, Y1, Y2, and P.
基板搭載面および裏面とも前記(1)式を満たす請求項1に記載の放熱板。   The heat sink according to claim 1, wherein both the substrate mounting surface and the back surface satisfy the formula (1). 1、X2、Y1、Y2、Pの各位置におけるNiめっき厚さの平均値が、基板搭載面において0.1〜10μmの範囲にある請求項1に記載の放熱板。 2. The heat sink according to claim 1, wherein the average value of the Ni plating thickness at each position of X 1 , X 2 , Y 1 , Y 2 , and P is in the range of 0.1 to 10 μm on the substrate mounting surface. 1、X2、Y1、Y2、Pの各位置におけるNiめっき厚さの平均値が、基板搭載面および裏面とも0.1〜10μmの範囲にある請求項2に記載の放熱板。 The heat sink according to claim 2, wherein the average value of the Ni plating thickness at each position of X 1 , X 2 , Y 1 , Y 2 , and P is in the range of 0.1 to 10 µm on both the substrate mounting surface and the back surface. Niめっきが施されていない端面を有する請求項1〜4のいずれかに記載の放熱板。   The heat sink in any one of Claims 1-4 which has an end surface to which Ni plating is not given. 基板搭載面についてロジン系フラックスを用いてはんだ付けを行ったとき、はんだ濡れ面積が95%以上となる請求項1〜5に記載の放熱板。   The heat sink according to any one of claims 1 to 5, wherein when the board mounting surface is soldered using a rosin flux, the solder wetted area becomes 95% or more. Niめっきが施された銅または銅合金の条材をプレス打抜きする工程を有する請求項1〜6のいずれかに記載の放熱板の製造法。   The manufacturing method of the heat sink in any one of Claims 1-6 which has the process of carrying out the press punching of the strip of copper or copper alloy to which Ni plating was given. プレス打抜きする工程の後に、反り付けを施す工程を有する請求項7に記載の放熱板の製造法。   The manufacturing method of the heat sink of Claim 7 which has the process of giving warp after the process of press punching. 前記プレス打ち抜きする工程および反り付けを施す工程を順送金型プレスにより行い、その順送金型内での材料の移送を、当該金型内に設けられたサイドガイドにより材料をリフトさせて行うことにより、材料と下型との移送時の接触を回避する請求項8に記載の放熱板の製造法。   The press punching step and the warping step are performed by a progressive die press, and the material is transferred in the progressive die by lifting the material with a side guide provided in the die. The manufacturing method of the heat sink of Claim 8 which avoids the contact at the time of the transfer of material and a lower mold | type. 前記プレス打ち抜きする工程または反り付けを施す工程の後に、打ち抜かれた板材をアルカリ、アルコールまたは炭化水素系の洗浄液を用いて脱脂した後、速やかに乾燥させる工程を有する請求項7〜9のいずれかに記載の放熱板の製造法。   10. The method according to claim 7, further comprising a step of degreasing the punched plate material using an alkali, alcohol, or hydrocarbon-based cleaning liquid and then quickly drying it after the press punching step or the warping step. The manufacturing method of the heat sink of description.
JP2006096766A 2006-03-31 2006-03-31 Manufacturing method of heat sink Active JP5011587B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006096766A JP5011587B2 (en) 2006-03-31 2006-03-31 Manufacturing method of heat sink

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006096766A JP5011587B2 (en) 2006-03-31 2006-03-31 Manufacturing method of heat sink

Publications (2)

Publication Number Publication Date
JP2007273682A true JP2007273682A (en) 2007-10-18
JP5011587B2 JP5011587B2 (en) 2012-08-29

Family

ID=38676179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006096766A Active JP5011587B2 (en) 2006-03-31 2006-03-31 Manufacturing method of heat sink

Country Status (1)

Country Link
JP (1) JP5011587B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214561A (en) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp Power module substrate with heat sink, power module substrate with cooler, and power module
JP2014138170A (en) * 2013-01-18 2014-07-28 Sh Materials Co Ltd Semiconductor element mounting substrate and manufacturing method of the same
JP2017087219A (en) * 2015-11-02 2017-05-25 Dowaメタルテック株式会社 Heat sink and its manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6332108B2 (en) * 2015-03-30 2018-05-30 三菱マテリアル株式会社 Manufacturing method of power module substrate with heat sink

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01243564A (en) * 1988-03-25 1989-09-28 Hitachi Ltd Manufacture of semiconductor device
JPH08316381A (en) * 1995-05-23 1996-11-29 Hitachi Cable Ltd Manufacture of heat sink for semiconductor package
JP2001308254A (en) * 2000-04-26 2001-11-02 Hitachi Ltd Semiconductor device and method of manufacturing it
JP2002009212A (en) * 2000-06-23 2002-01-11 Denki Kagaku Kogyo Kk Method for manufacturing heat dissipation structure
JP2004122155A (en) * 2002-09-30 2004-04-22 Dowa Mining Co Ltd Method and apparatus for manufacturing cooling plate for electronic equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01243564A (en) * 1988-03-25 1989-09-28 Hitachi Ltd Manufacture of semiconductor device
JPH08316381A (en) * 1995-05-23 1996-11-29 Hitachi Cable Ltd Manufacture of heat sink for semiconductor package
JP2001308254A (en) * 2000-04-26 2001-11-02 Hitachi Ltd Semiconductor device and method of manufacturing it
JP2002009212A (en) * 2000-06-23 2002-01-11 Denki Kagaku Kogyo Kk Method for manufacturing heat dissipation structure
JP2004122155A (en) * 2002-09-30 2004-04-22 Dowa Mining Co Ltd Method and apparatus for manufacturing cooling plate for electronic equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214561A (en) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp Power module substrate with heat sink, power module substrate with cooler, and power module
JP2014138170A (en) * 2013-01-18 2014-07-28 Sh Materials Co Ltd Semiconductor element mounting substrate and manufacturing method of the same
JP2017087219A (en) * 2015-11-02 2017-05-25 Dowaメタルテック株式会社 Heat sink and its manufacturing method

Also Published As

Publication number Publication date
JP5011587B2 (en) 2012-08-29

Similar Documents

Publication Publication Date Title
US10872841B2 (en) Ceramic metal circuit board and semiconductor device using the same
EP3136431B1 (en) Substrate for power modules, substrate with heat sink for power modules and power module with heat sink
JP4207896B2 (en) Semiconductor device
EP2911192B1 (en) Substrate for power module with heat sink, power module with heat sink, and method for producing substrate for power module with heat sink
JP4793622B2 (en) Ceramic circuit board, power module, and method of manufacturing power module
JP4560645B2 (en) Heat sink for mounting a plurality of semiconductor substrates and semiconductor substrate assembly using the same
JP2014207482A (en) Ceramics circuit board
EP3358615B1 (en) Silicon nitride circuit board and semiconductor module using same
JP4893096B2 (en) Circuit board and semiconductor module using the same
JP4893095B2 (en) Circuit board and semiconductor module using the same
KR102154373B1 (en) Power module
JP2008041752A (en) Semiconductor module, and radiation board for it
JP7159395B2 (en) Circuit boards and semiconductor modules
JPWO2015114987A1 (en) Power module substrate and power module using the same
US20170181272A1 (en) Ceramic circuit board and method for producing same
JP4683043B2 (en) Manufacturing method of semiconductor device
JP5011587B2 (en) Manufacturing method of heat sink
JP4703377B2 (en) Stepped circuit board, manufacturing method thereof, and power control component using the same.
JP5370460B2 (en) Semiconductor module
JP5218621B2 (en) Circuit board and semiconductor module using the same
JP5069485B2 (en) Metal base circuit board
US10043775B2 (en) Bonding material, bonding method and semiconductor device for electric power
JPWO2018012616A1 (en) Ceramic circuit board and semiconductor module
JP4560644B2 (en) Semiconductor substrate heatsink with improved soldering
JP4685245B2 (en) Circuit board and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090206

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110222

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110420

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120131

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120329

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120424

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20120517

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120517

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20120517

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150615

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5011587

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250