JPH01241162A - Aluminum wiring of semiconductor device - Google Patents
Aluminum wiring of semiconductor deviceInfo
- Publication number
- JPH01241162A JPH01241162A JP6744988A JP6744988A JPH01241162A JP H01241162 A JPH01241162 A JP H01241162A JP 6744988 A JP6744988 A JP 6744988A JP 6744988 A JP6744988 A JP 6744988A JP H01241162 A JPH01241162 A JP H01241162A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- wiring
- film
- high melting
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 238000002844 melting Methods 0.000 claims abstract description 17
- 230000008018 melting Effects 0.000 claims abstract description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910000838 Al alloy Inorganic materials 0.000 claims 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 15
- 239000010703 silicon Substances 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 10
- 230000005012 migration Effects 0.000 abstract description 8
- 238000013508 migration Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052753 mercury Inorganic materials 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 230000009257 reactivity Effects 0.000 abstract description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract 3
- 239000010936 titanium Substances 0.000 abstract 3
- 229910052719 titanium Inorganic materials 0.000 abstract 3
- 150000002739 metals Chemical class 0.000 abstract 2
- 239000005368 silicate glass Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000005546 reactive sputtering Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置のアルミニウム配線に係り、特にホ
トリソグラフィ時のハレーションやアルミニウム配線の
エレクトロマイグレーション、スリット断線、ヒロック
防止に好適なアルミニウム配線の形成方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to aluminum wiring for semiconductor devices, and in particular to formation of aluminum wiring suitable for preventing halation during photolithography, electromigration of aluminum wiring, slit breakage, and hillocks. Regarding the method.
従来は、特開昭５６−１５３３号に記載のようにハレー
ション防止策として、アルミニウム膜形成後その上にシ
リコン膜を堆積し、アルミニウム膜とシリコン膜の間で
の光の干渉を利用してハレーションを防止していた。又
、ＴｉＮを反射防出膜として使用した例として、第３４
回応用物理学関係連合講演会昭和６２年春季第５１１項
に述べられているが、配線を加工後ＴｉＮを除去してい
るので。Conventionally, as a halation prevention measure as described in JP-A-56-1533, a silicon film was deposited on the aluminum film after it was formed, and the halation was prevented by utilizing light interference between the aluminum film and the silicon film. was prevented. In addition, as an example of using TiN as an anti-reflection film, No. 34
As stated in Section 511 of the Spring 1986 Conference on Recycling Applied Physics, the TiN was removed after the wiring was processed.
配線の信頼性は従来のＡＱ−８ｉと同様であった。The reliability of the wiring was similar to that of the conventional AQ-8i.
又、従来の配線構造（１ｗｔ％Ｓｉ入りアルミニウム）
においては、エレクトロマイグレーション、ストレスマ
イグレーション、ヒロック発生等の問題点があった。Also, conventional wiring structure (1wt% Si-containing aluminum)
However, there were problems such as electromigration, stress migration, and hillock formation.
上記従来技術は、被覆シリコン膜がアルミニウム膜中に
拡散し、シリコン含有率を増加させることによるアルミ
ニウム膜中でのシリコン粒析出の増加、及びアルミニウ
ム配線（１％シリコン入り）における、ストレスマイグ
レーション、エレクトロマイグレーション、ヒロック発
生等の点について配慮がされておらず、アルミニウム配
線の信頼性について大きな悪影響を与えてしまうという
問題があった。The above-mentioned conventional technology is characterized by the fact that the coating silicon film diffuses into the aluminum film and increases the silicon content, thereby increasing the precipitation of silicon grains in the aluminum film, as well as stress migration and electrolysis in the aluminum wiring (containing 1% silicon). There was a problem in that no consideration was given to issues such as migration and the occurrence of hillocks, which had a large negative impact on the reliability of the aluminum wiring.
本発明の目的はアルミニウム配線形成時のりソゲラフイ
エ程でのハレーションを防止し、かつアルミニウム配線
のエレクトロマイグレーション。The object of the present invention is to prevent halation during formation of aluminum wiring and to prevent electromigration of aluminum wiring.
ストレスマイグレーション、ヒロック等を防止し。Prevents stress migration, hillocks, etc.
信頼性の高いアルミニウム配線を提供することにある。Our goal is to provide highly reliable aluminum wiring.
〔問題点を解決するための手段〕
上記目的は、従来のアルミニウム配線構造を、下記に示
すいずれかの構造とすることにより、達成される。[Means for Solving the Problems] The above object is achieved by replacing the conventional aluminum wiring structure with one of the structures shown below.
１、アルミニウム配線の上にＴｉＮ、ＴａＮ。1. TiN and TaN on aluminum wiring.
ＺｒＮ、ＨｆＮ等の高融点金属の窒化膜を形成する。A nitride film of a high melting point metal such as ZrN or HfN is formed.
２、アルミニウム配線の間に、上記高融点金属の窒化膜
を形成する。2. Form a nitride film of the above-mentioned high melting point metal between the aluminum wirings.
３、上記２の構造のアルミニウム上に、上記高融点金属
の窒化膜を形成する。3. A nitride film of the high melting point metal is formed on the aluminum having the structure described in 2 above.
水銀ランプのｉ線、ｇｍに対するＴｉＮ等の高融点金属
窒化膜の反射率は、現在ハレーション防止として用いて
いるＳｉとほぼ同じであるため。This is because the reflectance of a high melting point metal nitride film such as TiN with respect to the i-line and gm of a mercury lamp is almost the same as that of Si, which is currently used for halation prevention.
ハレーションの効果は従来方法と同程度と考えられる。The halation effect is considered to be on the same level as the conventional method.
また、これらの窒化膜のＡＱとの反応性も低いことから
、配線形成後の熱処理等により、ＡＱ配線に影響を及ぼ
すことはない、さらにＴｉＮのような高融点金属の窒化
物膜をＡｆｉ膜上に用いると、熱処理によるＡＱ粒子が
移動し、応力の変化に伴ない発生するヒロックにおいて
も、上記高融点金属の窒化膜は熱処理においても、ＡＱ
粒子の移動をおさえるので膜の表面での移動が生じにく
い。そのためＡＱのヒロック発生を防止できる。In addition, since these nitride films have low reactivity with AQ, heat treatment after wiring formation will not affect the AQ wiring. When used on top of the high melting point metal nitride film, even during heat treatment, AQ particles move and hillocks occur due to changes in stress.
Since the movement of particles is suppressed, movement on the surface of the membrane is less likely to occur. Therefore, the occurrence of AQ hillock can be prevented.
この高融点金属の窒化膜をＡＱ配線の表面及び間に用い
ることにより、Ａｆｌの応力によって発生するストレス
マイグレーションについても、この高融点金属の窒化膜
がＡＱの移動を妨げるため、その発生を抑制することが
でき、さらにエレクトロマイグレーションにおいても、
この高融点金属の窒化膜があることにより、ボイド形成
がＡＱ配線全体に生じることはないため、信頼度が向上
する。By using this high melting point metal nitride film on the surface of and between the AQ wiring, stress migration caused by the stress of Afl can be suppressed since the high melting point metal nitride film prevents the movement of AQ. Furthermore, in electromigration,
The presence of this refractory metal nitride film prevents void formation from occurring over the entire AQ wiring, thereby improving reliability.
以下、本発明の実施例を第】図により説明する。 Hereinafter, embodiments of the present invention will be explained with reference to the figures.
第１図（ａ）〜（ｄ）は本発明の一実施例としてｎ−チ
ャンネルＭＯＳトランジスタのｉｎ工程の流れを示すも
ので、それぞれ各工程における断面図である。FIGS. 1(a) to 1(d) show the flow of the in-process of an n-channel MOS transistor as an embodiment of the present invention, and are sectional views of each process.
まず、第１図（ａ）に示すように比抵抗１０Ω信のｐ型
（１００）シリコン基板１を局部的に酸化し、７００ｎ
ｍの素子間分離用シリコン酸化膜２を形成する。続い１
２０ｎｍ厚のゲート酸化膜３を形成した後、当該ＭＯＳ
トランジスタのしきい値電圧調整のため、はう素をイオ
ン打込み法によって該素子全面に６０ｋｅＶで６Ｘ１０
１１ｅｌｌ−”打込む０次に低圧ＣＶＤ法により３００
ｎｍの多結晶シリコン４を形成する。その後、ＰＯ（１
ｇ。First, as shown in FIG. 1(a), a p-type (100) silicon substrate 1 with a resistivity of 10Ω is locally oxidized,
A silicon oxide film 2 for element isolation of m is formed. Continuation 1
After forming the gate oxide film 3 with a thickness of 20 nm, the MOS
In order to adjust the threshold voltage of the transistor, 6×10 ions were applied to the entire surface of the device at 60 keV by ion implantation.
11ell-” implanted by 0-order low pressure CVD method.
Polycrystalline silicon 4 with a thickness of 10 nm is formed. Then PO(1
g.
Ｏｘの混合ガス中で熱処理を行ない、多結晶シリコン膜
４中にリンを拡散させる。続いてホトレジストをマスク
としてＣＦａ系ガスを用いたプラズマエツチング法によ
り多結晶シリコン膜４を所望の形状に加工し、その後上
記ホトレジストを除去する０次いでひ素を該素子全面に
８０ｋｅＶで５Ｘ １０ ”（！ＩＩ−”イオン打込み
を行なう。Heat treatment is performed in a mixed gas of Ox to diffuse phosphorus into the polycrystalline silicon film 4. Next, using the photoresist as a mask, the polycrystalline silicon film 4 is processed into a desired shape by plasma etching using CFa-based gas, and then the photoresist is removed. Then, arsenic is applied to the entire surface of the device at 80 keV at 5X 10'' (! II-” Perform ion implantation.
続いて第１図（ｂ）に示すように、１０ｍｏＱ％のリン
硅酸ガラス５をＣＶＤ法により５００ｎｍの厚さに堆積
させる。次にＣＦａ系プラズマエツチング法により、リ
ン硅酸ガラス５にコンタクト孔６を開ける。Subsequently, as shown in FIG. 1(b), 10 moQ% phosphosilicate glass 5 is deposited to a thickness of 500 nm by CVD. Next, a contact hole 6 is formed in the phosphosilicate glass 5 by a CFa-based plasma etching method.
次いで第１図（ｃ）に示すように１ｗｔ％のシリコンを
含んだアルミニウム膜７を３５０ｎｍ形成する。次に窒
化チタン膜８を反応性スパッタ法で１１００ｎ形成し１
次に１ ｗ ｔ％のシリコンを含んだアルミニウム膜７
を３５０ｎｍ形成する。Next, as shown in FIG. 1(c), an aluminum film 7 containing 1 wt% silicon is formed to a thickness of 350 nm. Next, a titanium nitride film 8 with a thickness of 1100 nm is formed by reactive sputtering.
Next, an aluminum film 7 containing 1 wt% silicon
is formed to a thickness of 350 nm.
次に窒化チタン膜８を反応性スパッタ法で１１００ｎ形
成する。Next, a titanium nitride film 8 of 1100 nm is formed by reactive sputtering.
その後第１図（ｄ）に示すように、ホトレジストをマス
クとしてＢ ＣＱ ａ系ガスを用いたプラズマエツチン
グ法で窒化チタン膜、アルミニウム膜を所望の形状に加
工し、その後上記ホトレジストを除去する。続いて４５
０℃、３０分間の水素処理を行なった後、パッシベーシ
ョン膜９を形成してＭＯＳトランジスタが完成する。Thereafter, as shown in FIG. 1(d), the titanium nitride film and the aluminum film are processed into a desired shape by plasma etching using a B CQ a-based gas using the photoresist as a mask, and then the photoresist is removed. followed by 45
After hydrogen treatment at 0° C. for 30 minutes, a passivation film 9 is formed to complete the MOS transistor.
本実施例によれば、アルミニウム膜のシリコン含有量を
増やすことはなく、ストレスマイグレーション、エレク
トロマイグレーションにおいても高い信頼性があるアル
ミニウム配線を形成できる６本実施例では、ＭＯＳトラ
ンジスタへの適用例を示したが１本発明はこれに限らず
アルミニウムを配線材料として用いるすべての半導体装
置に適用可能である。また、本実施例では、ＴｉＮを用
いたが、 ’Ｉ” ａ Ｎ 、 ７． ｒ Ｎ 、 Ｈ
ｆ Ｎ等の高融点金属の窒化膜も用いることができ、そ
の形成方法としては１反応性スパッタ法、窒化物ターゲ
ットのスパッタ法、ＣＶＯ法、金属（１）Ｎｚ 、ＮＨ
３ガス等による窒化法等がある。According to this example, it is possible to form an aluminum wiring that is highly reliable even in stress migration and electromigration without increasing the silicon content of the aluminum film.6 In this example, an example of application to a MOS transistor is shown. However, the present invention is not limited to this, and is applicable to all semiconductor devices that use aluminum as a wiring material. In addition, in this example, TiN was used, but 'I'' a N , 7. r N , H
A nitride film of a high melting point metal such as fN can also be used, and its formation methods include 1-reactive sputtering method, nitride target sputtering method, CVO method, metal (1)Nz, NH
There are nitriding methods using three gases, etc.
本発明によれば、アルミニウム膜中のシリコン含有量を
増加させることはなく、シリコン析出量が増加しコンタ
クト孔部分の電気的接触が悪くなることはない、また、
アルミニウム上及びその間に窒化チタン膜等の高融点金
属の窒化膜を堆積させることにより、アルミニウム配線
のヒロックを防止し、エレクトロマイグレーションやス
トレスマイグレーション等においても大きな効果がある
。According to the present invention, the silicon content in the aluminum film is not increased, the amount of silicon precipitated is not increased, and the electrical contact at the contact hole portion is not deteriorated.
By depositing a nitride film of a high melting point metal such as a titanium nitride film on and between aluminum, hillocks in the aluminum wiring can be prevented and there is a great effect on electromigration, stress migration, etc.
第１図（ａ）〜（ｄ）は本発明の一実施例を示すＭＯＳ
トランジスタの製造工程の加工部断面図である。FIGS. 1(a) to 1(d) show a MOS according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a processed portion in a transistor manufacturing process.
Claims (1)
ｉＮ、ＴａＮ、ＺｒＮ、ＨｆＮ等の高融点金属窒化物膜
から成る二層重ね膜で、上記高融点金属窒化物膜が上層
に存在することを特徴とする半導体装置のアルミニウム
配線。 ２、アルミニウムもしくはアルミニウム合金膜から成る
配線層の間に少なくとも一層以上のＴｉＮ、ＴａＮ、Ｚ
ｒＮ、ＨｆＮ等の高融点金属窒化物層が存在することを
特徴とする半導体装置のアルミニウム配線。 ３、アルミニウムもしくはアルミニウム合金膜から成る
配線層の間に少なくとも一層以上のＴｉＮ、ＴａＮ、Ｚ
ｒＮ、ＨｆＮ等の高融点金属窒化物層が存在し、かつ上
記配線層の上層にもＴｉＮ、ＴａＮ、ＺｒＮ、ＨｆＮ等
の高融点金属窒化物層が存在することを特徴とする半導
体装置のアルミニウム配線。[Claims] 1. Aluminum or aluminum alloy film and T
An aluminum wiring for a semiconductor device, characterized in that it is a two-layered film consisting of a high-melting point metal nitride film such as iN, TaN, ZrN, HfN, etc., and the above-mentioned high-melting point metal nitride film is present as an upper layer. 2. At least one layer of TiN, TaN, Z between wiring layers made of aluminum or aluminum alloy film
An aluminum wiring for a semiconductor device characterized by the presence of a high melting point metal nitride layer such as rN or HfN. 3. At least one layer of TiN, TaN, Z between wiring layers made of aluminum or aluminum alloy film
An aluminum semiconductor device characterized in that a high melting point metal nitride layer such as rN, HfN, etc. is present, and a high melting point metal nitride layer such as TiN, TaN, ZrN, HfN, etc. is also present in the upper layer of the wiring layer. wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6744988A JPH01241162A (en) | 1988-03-23 | 1988-03-23 | Aluminum wiring of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6744988A JPH01241162A (en) | 1988-03-23 | 1988-03-23 | Aluminum wiring of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01241162A true JPH01241162A (en) | 1989-09-26 |
Family
ID=13345245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6744988A Pending JPH01241162A (en) | 1988-03-23 | 1988-03-23 | Aluminum wiring of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01241162A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5302538A (en) * | 1992-08-04 | 1994-04-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing field effect transistor |
| US5972786A (en) * | 1992-01-21 | 1999-10-26 | Sony Corporation | Contact hole structure in a semiconductor and formation method therefor |
| US9330940B2 (en) | 2001-02-28 | 2016-05-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
-
1988
- 1988-03-23 JP JP6744988A patent/JPH01241162A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5972786A (en) * | 1992-01-21 | 1999-10-26 | Sony Corporation | Contact hole structure in a semiconductor and formation method therefor |
| US5302538A (en) * | 1992-08-04 | 1994-04-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing field effect transistor |
| US9330940B2 (en) | 2001-02-28 | 2016-05-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
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