JPH01239914A - Wafer treatment apparatus - Google Patents
Wafer treatment apparatusInfo
- Publication number
- JPH01239914A JPH01239914A JP6777788A JP6777788A JPH01239914A JP H01239914 A JPH01239914 A JP H01239914A JP 6777788 A JP6777788 A JP 6777788A JP 6777788 A JP6777788 A JP 6777788A JP H01239914 A JPH01239914 A JP H01239914A
- Authority
- JP
- Japan
- Prior art keywords
- processing
- wafer
- treatment conditions
- semiconductor wafer
- mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 235000012431 wafers Nutrition 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 230000007246 mechanism Effects 0.000 claims abstract description 39
- 238000000576 coating method Methods 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は、枚葉処理装置に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a single wafer processing apparatus.
（従来の技術）
半導体の製造工程において、生産効率を向上させるため
の一手段として、複数の処理機構１例えば半導体ウェハ
のレジスト塗布、加熱処理、現像機構等を連続して配置
して処理する装置を使用し、また複数の半導体ウェハを
１単位すなわち１０ツトとして取扱い処理することが行
われている。(Prior Art) In the semiconductor manufacturing process, as a means to improve production efficiency, a device that sequentially arranges and processes a plurality of processing mechanisms 1, such as resist coating, heat treatment, and development mechanisms for semiconductor wafers, is used. In addition, a plurality of semiconductor wafers are handled and processed as one unit, that is, 10 pieces.
そして、各ロットを構成する半導体ウェハの処理条件を
、各ロフトおよび各処理機構毎に設定し直すようにして
いる。Then, processing conditions for semiconductor wafers constituting each lot are reset for each loft and each processing mechanism.
（発明が解決、しようとする課題）
しかしながら、連続して配置した処理機構の数が多くな
るとロット毎に全処理機構の処理条件を設定し直すのに
は時間がかかり、装置の稼動率を著しく低下させるばか
りではなく、条件設定を誤るおそれがある。(Problem to be solved by the invention) However, when the number of processing mechanisms arranged in succession increases, it takes time to reset the processing conditions of all processing mechanisms for each lot, which significantly reduces the operating rate of the equipment. There is a risk that not only the performance will be lowered, but also that the condition settings may be incorrect.
また、近年の傾向として、多品種少量生産が通常となり
つつある。したがって、ロットを構成する半導体ウェハ
の数も減少し、半導体ウェハ１枚毎に処理条件が異なる
こともあり、上記点を考慮した処理装置が要望されてい
た。Additionally, as a trend in recent years, high-mix, low-volume production is becoming the norm. Therefore, the number of semiconductor wafers constituting a lot has decreased, and the processing conditions may differ for each semiconductor wafer, so there has been a demand for a processing apparatus that takes the above points into consideration.
本発明は上述の従来事情に対処してなされたもので、稼
動率を低下させることなく半導体ウェハ毎に処理条件が
自動的に設定可能な枚葉処理装置を堤供しようとするも
のである。The present invention has been made in response to the above-mentioned conventional situation, and is intended to provide a single wafer processing apparatus in which processing conditions can be automatically set for each semiconductor wafer without reducing the operating rate.
（課題を解決するための手段）
すなわち本発明は、レジスト塗布・現４ｇ＜などの複数
の処理機溝を備え、この処理機構に半導体ウェハを１枚
ずつ移送して処理する枚葉処理装置において、各半導体
ウェハに対応した処理条件を記憶する記憶手段と、この
記憶手段から移送された半導体ウェハに対応する処理条
件を読出し、この処理条件により上記各処理機構を制御
して上記半導体ウェハを処理する制御手段を備えたこと
を特徴とする。(Means for Solving the Problems) That is, the present invention provides a single wafer processing apparatus which is provided with a plurality of processing machine grooves such as resist coating and coating grooves, and which transfers semiconductor wafers one by one to this processing mechanism for processing. , a storage means for storing processing conditions corresponding to each semiconductor wafer; and processing conditions corresponding to the transferred semiconductor wafers are read from the storage means, and each processing mechanism is controlled according to the processing conditions to process the semiconductor wafers. The invention is characterized in that it is equipped with a control means.
（作 用）
本発明枚葉処理装置では、各半導体ウェハに対応した処
理条件を記憶する記憶手段と、この記憶手段から移送さ
れた半導体ウェハに対応する処理条件を読出し、この処
理条件により各処理機構を制御して半導体ウェハを処理
する制御手段を備えているので、半導体ウェハの各処理
条件を自動的に設定して処理することができる。(Function) The single wafer processing apparatus of the present invention includes a storage means for storing processing conditions corresponding to each semiconductor wafer, and a processing condition corresponding to the transferred semiconductor wafer is read from the storage means, and each processing is performed according to the processing condition. Since the control means for controlling the mechanism to process the semiconductor wafer is provided, each processing condition for the semiconductor wafer can be automatically set and processed.
（実施例）
以下、本発明枚葉処理装置の一実施例を図面を参照して
説明する。(Example) Hereinafter, an example of the single wafer processing apparatus of the present invention will be described with reference to the drawings.
装置本体（１）の−六個には、半導体ウェハ■を例えば
２５枚程度収納するウェハカセット（図示せず）を載置
し、上記半導体ウェハ■を１枚ずつウェハカセット（図
示せず）から取り出して搬出するローダ−（■と、複数
の処理機構例えばこのローダ−■から搬出された半導体
ウェハ■をレジストコータの載置台に保持し、第１の処
理例えばスピンコーティング法等によりこの半導体ウェ
ハ０表面にレジストを塗布するレジスト塗布工程０）、
このレジスト塗布機構＠）により塗布されたレジスト中
に残留する溶剤を加熱蒸発させるプリベーク機構■と、
このプリベーク機構■によって熱処理された半導体ウェ
ハ０を他の処理装置例えば露光装置（図示せず）に搬送
して渡すセンダー■が直列状に並置されている。A wafer cassette (not shown) storing, for example, about 25 semiconductor wafers ■ is placed in the -6 of the apparatus body (1), and the semiconductor wafers ■ are loaded one by one from the wafer cassette (not shown). A loader (■) to be taken out and carried out and a plurality of processing mechanisms such as the semiconductor wafer (■) carried out from this loader (■) are held on a mounting table of a resist coater, and the semiconductor wafer (■) is coated by a first process such as a spin coating method. Resist coating step 0) of applying resist to the surface;
A pre-bake mechanism ■ that heats and evaporates the solvent remaining in the resist applied by this resist coating mechanism @);
Senders (2) are arranged in series to convey and deliver the semiconductor wafers 0, which have been heat-treated by the pre-bake mechanism (2), to another processing device, such as an exposure device (not shown).
一方、装置本体０）の他方側には、上述の各機構と並ぶ
ように、上記露光装置（図示せず）によって露光処理さ
れた半導体ウェハ（８）を受取った後に次の処理機構に
渡すレシーバ−（９）と、このレシーバ−（９）から渡
された上記半導体ウェハ（８）を第２の処理例えばスピ
ン法等により現像処理する現像機ｔＪ（１０）、この現
像機構（ｌＯ）によってパターン形成されたレジストに
残留する現像液を蒸発除去し半導体ウェハ（８）とレジ
ストどの密着性を強化するためのボストベーク機４ｉ！
（１１）と、このポストベーク機構（１１）によって熱
処理された半導体ウェハ（１２）をウェハカセット（図
示せず）に収納するアンローダ−（１３）が直列状に夫
夫−框体上に配置されている。On the other hand, on the other side of the apparatus main body 0), in line with the above-mentioned mechanisms, there is a receiver that receives the semiconductor wafer (8) exposed by the exposure apparatus (not shown) and then passes it to the next processing mechanism. - (9), a developing machine tJ (10) which develops the semiconductor wafer (8) passed from this receiver (9) by a second process such as a spin method, and a pattern is formed by this developing mechanism (1O). A post bake machine 4i is used to evaporate and remove the developer remaining on the formed resist and strengthen the adhesion between the semiconductor wafer (8) and the resist!
(11) and an unloader (13) for storing the semiconductor wafer (12) heat-treated by the post-bake mechanism (11) in a wafer cassette (not shown) are arranged in series on the frame. ing.
また、半導体ウェハ■の予め定められた位置に形成され
た識別表示記号例えばアルファベット、数字、バーコー
ドなどのＩＤマーク（図示せず）および各半導体ウェハ
に対応する上記夫夫の処理機構における各処理条件を予
めＩＣメモリーなどの記憶素子に入力することにより、
夫夫の半導体ウェハの処理条件を記憶しておく記憶手段
（１４）と、この記憶手段（１４）から上記ＩＤマーク
（図示せず）に対応する各処理条件を引き出して上記複
数の処理機構に指示するマイクロコンピュータ等を使用
した制御手段（１５）が設けられている。そして、例え
ば、ローダ−（３）において読取り手段（図示せず）に
より半導体ウェハ■のＩＤマーク（図示せず）の内容を
読取って制御手段（１５）に伝送する如く構成されてい
る。処理条件の記憶は半導体ウェハ毎でなくとも種別単
位で処理条件を記憶してもよい。In addition, identification marks (not shown) such as alphabets, numbers, bar codes, etc. are formed at predetermined positions on the semiconductor wafers, and each process in the husband's processing mechanism corresponds to each semiconductor wafer. By inputting conditions in advance into a memory device such as an IC memory,
A storage means (14) for storing the processing conditions of the husband's semiconductor wafers, and each processing condition corresponding to the ID mark (not shown) is extracted from the storage means (14) and sent to the plurality of processing mechanisms. A control means (15) using a microcomputer or the like for giving instructions is provided. For example, the loader (3) is configured to read the contents of the ID mark (not shown) on the semiconductor wafer (2) using a reading means (not shown) and transmit the read information to the control means (15). The processing conditions need not be stored for each semiconductor wafer, but may be stored for each type.
この方がメモリ容量が少くて済む利点がある。This has the advantage of requiring less memory capacity.
次に、動作作用について説明する。Next, the operation effect will be explained.
先ず、予め、半導体ウェハ■のＩＤマーク（図示せず）
と、このＩＤマーク（図示せず）に対応する各処理条件
に関する情報を記憶手段（１４）に記憶させておく。ロ
ーダ−■でウェハカセット（図示せず）に収納されてい
る半導体ウェハ（２）を１枚取出して、読取り手段（図
示せず）により半導体ウェハ■のＩＤマーク（図示せず
）の情報内容を読取りこの内容を制御手段（１５）に伝
送する。そして、上記半導体ウェハ■をレジスト塗布工
程であるレジスト塗布機構０）に搬送する。First, in advance, mark the ID mark (not shown) on the semiconductor wafer.
Information regarding each processing condition corresponding to this ID mark (not shown) is stored in the storage means (14). A loader ■ takes out one semiconductor wafer (2) stored in a wafer cassette (not shown), and a reading means (not shown) reads the information content of the ID mark (not shown) of the semiconductor wafer ■. The read contents are transmitted to the control means (15). Then, the semiconductor wafer (2) is transported to a resist coating mechanism 0) which is a resist coating process.
ＩＤマーク（図示せず）の内容を受けた制御手段（１５
）により記憶手段（１４）内に記憶されている内容のう
ち、上記ＩＤマーク（図示せず）に対応する各処理条件
を自動的に読出し、この読出した処理に応じた制御を制
御系に指示する。Control means (15) receiving the contents of the ID mark (not shown)
) automatically reads each processing condition corresponding to the ID mark (not shown) from among the contents stored in the storage means (14), and instructs the control system to control according to the read processing. do.
なお、記憶手段（１４）内における記憶は、例えば第２
図に示すように上記ＩＤマーク（図示せず）に対応する
各半導体ウェハｍ（２１）、ｍ ＋ １ （２２）、ｍ
＋２ （２３）、・・・についてのデータ領域（２４
）、 （２５）、（２６）、・・・が確保されている。Note that the storage in the storage means (14) is, for example, the second
As shown in the figure, each semiconductor wafer m (21), m + 1 (22), m corresponding to the ID mark (not shown)
+2 (23), data area (24
), (25), (26), etc. are secured.
各処理機構における各処理条件例えばレジスト塗布条件
ｍ（２７）、ｍ＋１ （２８）、ｍ ＋ ２ （２９）
、・・・は、同一アドレスに記憶されている。Each processing condition in each processing mechanism, for example, resist coating conditions m (27), m + 1 (28), m + 2 (29)
, . . . are stored at the same address.
したがって、今、レジスト塗布処理しようとする半導体
ウェハ■が、ＩＤマーク（図示せず）によって、記憶手
段（１４）内に記憶されている内容のうち半導体ウェハ
ｍ（２１）に該当する処理条件で処理すべき旨指定され
ると、この処理条件を制御手段（１５）によって読出す
。そして、例えば、レジスト塗布条件ｍ（２７）をレジ
スト塗布機構（４）に指示して、この条件で枚葉処理す
るように制御する。Therefore, the semiconductor wafer (2) to be subjected to the resist coating process is now under the processing conditions corresponding to the semiconductor wafer (m) (21) among the contents stored in the storage means (14) according to the ID mark (not shown). When the processing is specified, the processing conditions are read out by the control means (15). Then, for example, the resist coating condition m (27) is instructed to the resist coating mechanism (4), and the resist coating mechanism (4) is controlled to perform single wafer processing under these conditions.
上記レジスト塗布処理が終了するとレジスト塗布機構（
１）から処理終了の旨制御手段（１５）に伝達される。When the above resist coating process is completed, the resist coating mechanism (
1), the fact that the process has ended is transmitted to the control means (15).
この後、上記半導体ウェハ（２）は次の処理工程である
プリベーク機構０に搬送されてプリベーク処理されるこ
とになるが、その処理条件は上記の場合と同じ半導体ウ
ェハｍ （２］）に該当するプリベーク処理条件にて処
理するように上記プリベーク機構■に指示される。After this, the semiconductor wafer (2) will be transported to the next processing step, pre-bake mechanism 0, and will be pre-baked, but the processing conditions are the same as in the case above, which corresponds to semiconductor wafer m (2). The pre-bake mechanism (2) is instructed to perform processing under the pre-bake processing conditions.
一方、次の半導体ウェハ■は、ローダ−■にて上記同様
にＩＤマーク（図示せず）が読取られ、例えば半導体ウ
ェハｍ ＋ １ （２２）に対応するデータ領域（２５
）の内容に従って処理するように、制御手段（１５）が
レジスト塗布機構（イ）他の各機構に自動的に指示する
。以下、上述の手順に従って、処理を行う。On the other hand, the ID mark (not shown) of the next semiconductor wafer (2) is read by the loader (2) in the same manner as above, and the data area (25
) The control means (15) automatically instructs the resist coating mechanism (a) and other mechanisms to perform processing according to the contents of the above. Hereinafter, processing is performed according to the above-mentioned procedure.
なお、上記実施例では半導体ウェハ■のＩＤマークの読
取りをローダ−（３）にて読取ることで説明したが、他
の各処理機構において読取りその情報を制御手段（１５
）に伝達するように構成してもよい。In the above embodiment, the ID mark of the semiconductor wafer (2) is read by the loader (3), but other processing mechanisms read the ID mark and the information is transmitted to the control means (15).
).
また、各処理機構における処理条件の記憶は、上記実施
例のようにＩＤマーク別すなわち半導体ウェハ別に設け
たデータ領域に各処理条件をすべて記憶する方法の他、
各処理別にデータ領域を設けてＩＤマークに対応した処
理条件を記憶するようにしてもよい。In addition, the processing conditions in each processing mechanism can be stored in a data area provided for each ID mark, that is, for each semiconductor wafer, as in the above embodiment, as well as other methods.
A data area may be provided for each process to store processing conditions corresponding to the ID mark.
レジスト塗布現像工程は、レジスト量１回転数、回転時
間、加熱時間、加熱温度、現像時間等の条件設定項目が
多いので１本発明は非常に有効である。The present invention is very effective in the resist coating and developing process because there are many condition setting items such as resist amount per revolution, rotation time, heating time, heating temperature, and development time.
上述したように本発明枚葉処理装置によれば、処理条件
が変っても稼動率を低下させることなく自動的に枚葉処
理することができる。As described above, according to the single wafer processing apparatus of the present invention, even if the processing conditions change, single wafer processing can be automatically performed without reducing the operating rate.
第１図は本発明枚葉処理装置の一実施例を説明するため
の植成図、第２図は第１図の部分説明図である。
２・・・半導体ウェハ、 ４・・・レジスト塗布機構
、１０・・・現像機構、 １４・・・記憶手段、
１５・・・制御手段。FIG. 1 is a planting diagram for explaining one embodiment of the single wafer processing apparatus of the present invention, and FIG. 2 is a partial explanatory diagram of FIG. 1. 2... Semiconductor wafer, 4... Resist coating mechanism, 10... Developing mechanism, 14... Storage means,
15... Control means.
Claims (1)
の処理機構に半導体ウェハを１枚ずつ移送して処理する
枚葉処理装置において、各半導体ウェハに対応した処理
条件を記憶する記憶手段と、この記憶手段から移送され
た半導体ウェハに対応する処理条件を読出し、この処理
条件により上記各処理機構を制御して上記半導体ウェハ
を処理する制御手段を備えたことを特徴とする枚葉処理
装置。In a single wafer processing apparatus which is equipped with a plurality of processing mechanisms such as resist coating and developing, and which transfers semiconductor wafers one by one to the processing mechanisms for processing, a storage means for storing processing conditions corresponding to each semiconductor wafer; A single wafer processing apparatus comprising: a control means for reading processing conditions corresponding to a transferred semiconductor wafer from a storage means and controlling each of the processing mechanisms according to the processing conditions to process the semiconductor wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6777788A JPH01239914A (en) | 1988-03-22 | 1988-03-22 | Wafer treatment apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6777788A JPH01239914A (en) | 1988-03-22 | 1988-03-22 | Wafer treatment apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01239914A true JPH01239914A (en) | 1989-09-25 |
Family
ID=13354722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6777788A Pending JPH01239914A (en) | 1988-03-22 | 1988-03-22 | Wafer treatment apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01239914A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG94851A1 (en) * | 2000-07-12 | 2003-03-18 | Tokyo Electron Ltd | Substrate processing apparatus and substrate processing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169343A (en) * | 1980-05-30 | 1981-12-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS57118639A (en) * | 1981-01-16 | 1982-07-23 | Toshiba Corp | Process control of semiconductor photo-etching |
-
1988
- 1988-03-22 JP JP6777788A patent/JPH01239914A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169343A (en) * | 1980-05-30 | 1981-12-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS57118639A (en) * | 1981-01-16 | 1982-07-23 | Toshiba Corp | Process control of semiconductor photo-etching |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG94851A1 (en) * | 2000-07-12 | 2003-03-18 | Tokyo Electron Ltd | Substrate processing apparatus and substrate processing method |
| US6593045B2 (en) | 2000-07-12 | 2003-07-15 | Tokyo Electron Limited | Substrate processing apparatus and method |
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