JPH01239417A - Pulse reading-in circuit for pulse encoder - Google Patents

Abstract

PURPOSE:To securely prevent the wrong output of an origin reset signal by confirming a rotation direction when there is a C pulse invalidation signal and resetting a reset inhibition signal, and using a next 1st C-pulse effective edge signal as a reset signal. CONSTITUTION:An ineffective edge detecting means 11 for a C pulse and an effective edge inhibition detecting means 12 are provided newly and when there is an ineffective edge signal for the C pulse in the OR signal of output signals, an inhibition signal memory 16 outputs the reset signal output inhibition signal 15 for inhibiting the reset signal 10 from being outputted. Then it is confirmed that a rotation direction signal 6 coincides with an actual direction, the inhibition signal 15 is reset, and the effective edge signal 17 for the C pulse is outputted in this state as the origin reset signal 10 through a reset means 18. Consequently, even if inversion is caused almost at the ineffective edge of the C pulse, the wrong output of the reset signal is securely prevented.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is to reliably prevent erroneous output of a home reset signal in a pulse encoder used for position detection in a fixed position stop control device for a main axis of a machine tool, etc. This invention relates to a pulse reading circuit that enables the following.

[Conventional technology]

A conventional example of a pulse reading circuit for a pulse encoder is shown in the fourth example.
This will be explained based on the diagram. In this figure, the pulse edge detection means 1.2 detects the rising edge and the falling edge of the A-phase pulse and the B-phase pulse shown in FIG. The rotation direction is determined from the phase relationship between the A phase and the B phase, and a rotation direction signal 6 is output. On the other hand, the C/0 pulse, which is output once per revolution of the encoder, is rotated in the normal direction by detecting the rising edge and falling edge by the rising edge detecting means 7 and falling edge detecting means 8, respectively, and the output signal and the rotating direction signal 6. A reset signal 10 is outputted by a valid edge detection means 9 which determines a rising edge as a valid edge when the time is reversed and a falling edge when the reverse occurs, and this reset signal 10 is used as an origin signal for a counter reset/node, etc. was.

[Problem to be solved by the invention]

The C pulse has a width as shown in Fig. 6, so in order to make the origin position accurate, it is set at the rising edge shown as the effective edge in Fig. 6(a) during forward rotation, and at the rising edge shown in Fig. 6 during reverse rotation. (b) Reset signal 1 at falling edge as shown in C
It is necessary to output 0, and this operation is generally performed at a rising edge when the rotation direction signal 6 is at H level, and at a falling edge when it is at L level.

However, in the above circuit, as shown in the time chart of FIG. 7, when the circuit is rotated forward to the X position and then reversed, the rotation direction remains unchanged until either the A-phase pulse or the B-phase pulse is input to the rotation direction determining means 5. cannot be determined, and the rotation direction signal 6 is output with a delay from the actual rotation direction, so the reset signal 10 may be output at the y position of the rising edge (invalid edge) of the C pulse, which should not be output. There was a drawback.

In order to eliminate the above-mentioned drawbacks, the present invention provides a pulse reading circuit for a pulse encoder that can reliably prevent erroneous output of a reset signal even if the C pulse is reversed in the vicinity of an invalid edge. The purpose is to

[Means to solve the problem]

In order to achieve the above object, the present invention provides an invalid edge detection means 11 in parallel with the effective edge detection means 9 of the C pulse, and also provides a valid edge inhibition detection means 12 at the next stage of the effective edge detection means 9. When an invalid edge signal 13 of the C pulse is present in the logical sum of the output signals, the valid edge inhibition detection means 12 and the AND element 14 are reset.
6, after outputting the reset signal output prohibition signal 15, wait for the input of a new edge signal 3.4 of either the A phase pulse or the B phase pulse, and release it. In this state, the valid edge signal of the C pulse is output. 17 as the AND element 14
7) Resetting means 18 for outputting the reset signal 10 via the reset signal 10.

[Effect]

The reset signal output prohibition signal 15 is canceled after confirming that the rotation direction signal 6 matches the actual rotation direction, and the valid edge signal 17 of the first C pulse thereafter is output as the reset signal 10. Invalid edge signal 1
, 3 can reliably prevent erroneous output of the reset signal 10 due to erroneous determination.

〔Example〕

FIGS. 1 and 2 show an embodiment of the present invention, and the same parts are denoted by the same reference numerals as in FIGS. 4 to 7. In these figures, the rising edge detecting means 7 and the falling edge detecting means 8 are followed by a valid edge detecting means 9 and an invalid edge detecting means 9, which determine whether the edge of the C pulse is valid or invalid based on these output signals and the rotation direction signal 6. A detection means 11 is provided in parallel, and the effective edge signal 17 which is the output thereof and the reset signal output prohibition signal 15 output from the prohibition signal memory 16 are inputted to the next stage of the valid edge detection means 9 to detect the valid edge signal. Valid edge inhibition detection means 12 is provided for detecting that 17 is not outputted as the reset signal 10. The prohibition signal memory 16 stores a logic signal between the valid edge prohibition detecting means 12 and the valid edge prohibiting detecting means 12 when there is an invalid edge signal 13 of the C pulse in the OR element 19 of the output signals of the valid edge prohibition detecting means 12 and the invalid edge detecting means 11. The reset signal output prohibition signal 15 is outputted to the product element 14, and the logical sum and edge signals 3.4 of the A-phase pulse and the B-phase pulse are input to the reset means 18 of the prohibition signal memory 16.

The reset signal output prohibition signal 15 is output when a new edge signal 3, 4 of at least one of the A-phase pulse and the B-phase pulse is input to the reset means 18 after outputting it, or when the logical sum is updated in the middle thereof. By invalidating the previous edge signals 3 and 4, waiting for the input of new edge signals 3 and 4, and confirming that the rotation direction signal 6 matches the actual rotation direction, the prohibition signal memory 16 is reset. is released, and in this state the first C
If the valid edge signal 17 of the pulse is output as the reset signal 10 through the AND element 14 as shown in FIG.
Erroneous output of 0 can be prevented.

〔Effect of the invention〕

According to the present invention, in the pulse reading circuit of a pulse encoder, a reset signal output prohibition signal that prohibits the output of a reset signal when there is an invalid edge signal of a C pulse is sent to confirm that the rotation direction signal matches the actual rotation direction. Since the first valid edge signal after that is output as the origin reset signal, erroneous output of the reset signal is reliably prevented even if the C pulse is reversed near the invalid edge, and the counter etc. The effect is that the origin can be maintained normally.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention, and FIG. 2 is a block diagram of an embodiment of the invention.
3 is a time chart showing the operation of FIGS. 1 and 2, FIG. 4 is a block diagram of the conventional example, and FIG. 5 is a time chart showing the pulse waveform of FIG. 4.
6 is an explanatory diagram of the operation of the reset signal of FIG. 4, and FIG. 7 is a time chart showing the operation of FIG. 4. 3.4... Edge signal, 6... Rotation direction signal, 7.
... Rise detection means, 8. Fall detection means, 9. Valid edge detection means, 10. Reset signal, 11. Invalid edge detection means, 12. Valid edge inhibition detection means. 13... Invalid edge signal, 14...
...Logic product element, 15...Reset signal output prohibition signal, 16...Prohibition signal memory, 17...Valid edge signal, 100 μm Port C・4. . Figure 3 Figure 4 → Seisha Yun Figure 6

Claims (1)

[Claims] 1) The C pulse is generated by the rotation direction signal obtained from the phase relationship between the A-phase pulse and the B-phase pulse of the pulse encoder and the output signals of the C pulse rise detection means and fall detection means that are output once per revolution of the encoder. In the pulse reading circuit which outputs the origin reset signal using the effective edge detection means, a C circuit is connected in parallel with the effective edge detection means.
A pulse invalid edge detection means is provided, and a valid edge prohibition detection means is provided at the next stage of the valid edge detection means, and when there is an invalid edge signal of the C pulse in the logical sum of these output signals, the valid edge prohibition detection means is provided. and a prohibition signal memory that outputs a reset signal output prohibition signal to the AND element, and an A after outputting the reset signal output prohibition signal.
Resetting means waits for input of a new edge signal of at least one of the phase pulse and the B-phase pulse, releases it, and in this state outputs the valid edge signal of the C pulse as a reset signal via the AND element. A pulse reading circuit for a pulse encoder featuring: