JPH01238063A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01238063A JPH01238063A JP63063631A JP6363188A JPH01238063A JP H01238063 A JPH01238063 A JP H01238063A JP 63063631 A JP63063631 A JP 63063631A JP 6363188 A JP6363188 A JP 6363188A JP H01238063 A JPH01238063 A JP H01238063A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- propagation time
- input
- input signal
- inner gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000005611 electricity Effects 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置、特に、その入力部の静電耐圧の向上および
入力信号伝播時間の短縮化に関し、電線を溶断しに＜＜
シて、静電耐圧の向上および入力信号伝播時間の短縮を
図ることを目的とし、入力パッドと内部ゲートとの間に
接続された保護回路としての半導体装置であって、入力
パッドに接続された不純物領域と基板とにより形成され
、電源に接続される接合ダイオードと、接合ダイオード
の不純物領域と前記内部ゲートとの間に接続された金属
層と、を具備するように構成する。[Detailed Description of the Invention] [Summary] In order to improve the electrostatic withstand voltage of a semiconductor device, especially its input part, and shorten the input signal propagation time, there is a need for melting down electric wires.
A semiconductor device that serves as a protection circuit connected between an input pad and an internal gate, with the aim of improving electrostatic withstand voltage and shortening input signal propagation time. The semiconductor device is configured to include a junction diode formed by an impurity region and a substrate and connected to a power source, and a metal layer connected between the impurity region of the junction diode and the internal gate.
本発明は半導体装置、特に、その入力部の静電耐圧の向
上および入力信号伝播時間の短縮化に関する。The present invention relates to a semiconductor device, and particularly to improving the electrostatic withstand voltage of an input portion thereof and shortening the input signal propagation time.
〔従来の技術および発明が解決しようとする課題〕従来
の半導体装置の入力保護回路の一例が、第３図、第４図
（第３図の断面図）に示される。[Prior Art and Problems to be Solved by the Invention] An example of a conventional input protection circuit for a semiconductor device is shown in FIGS. 3 and 4 (cross-sectional view of FIG. 3).
第３図、第４図においては、入力パッドＰ。と内部ゲー
ト （図示例では、入力バッファＣ２のトランジスタＱ
２のゲート）との間に入力保護回路ＣＩが設けられてい
る。入力保護回路Ｃ＋ は、不純物拡散領域（Ｐ” ）
６により構成される抵抗Ｒ１と、不純物拡散領域（Ｐ”
）６および不純物拡散領域（Ｎ−）により構成され、
電源電圧Ｖ。。以上のオーバシュートを吸収する接合ダ
イオードＤ＋と、不純物拡散領域（Ｎ” ） ７と基板
（Ｐ−） とに構成され、電源電圧ＧＮＤ以下のアン
ダシュートを吸収する接合ダイオードＤ２ とにより構
成されている。なお、第３図において、入力バッファＣ
２は、ＰチャネルトランジスタＱ＋およびＮチャネルト
ランジスタＱ２により構成されている。In FIGS. 3 and 4, the input pad P. and internal gate (in the illustrated example, transistor Q of input buffer C2
An input protection circuit CI is provided between the input protection circuit and the gate of FIG. The input protection circuit C+ is an impurity diffusion region (P”)
6 and the impurity diffusion region (P”
)6 and an impurity diffusion region (N-),
Power supply voltage V. . It is composed of a junction diode D+ that absorbs the above overshoot, and a junction diode D2 that is composed of an impurity diffusion region (N") 7 and a substrate (P-) and absorbs an undershoot below the power supply voltage GND. In addition, in Fig. 3, the input buffer C
2 is composed of a P-channel transistor Q+ and an N-channel transistor Q2.
また、第４図において、１はＰ−シリコン単結晶基板、
２はフィールド酸化膜（Ｓｉｎ２）、３はゲート酸化膜
（Ｓｉ０２）、４はゲート電極（ポリシリコン）、５は
Ｎ−不純物拡散領域、８はＮ゛不純物拡散領域、９は絶
縁膜（ＰＳＧ） 、１０は導電層（ポリシリコンもしく
はアルミニウム）である。In addition, in FIG. 4, 1 is a P-silicon single crystal substrate;
2 is a field oxide film (Sin2), 3 is a gate oxide film (Si02), 4 is a gate electrode (polysilicon), 5 is an N− impurity diffusion region, 8 is a N− impurity diffusion region, 9 is an insulating film (PSG) , 10 is a conductive layer (polysilicon or aluminum).
しかしながら、第３図、第４図の入力保護回路Ｃ４にお
いては、抵抗ＲＩがＰ゛不純物拡散領域６により形成さ
れているために、Ｎ−不純物拡散領域５との間の寄生容
量が大きく、この結果、トランジスタＱ２のゲート電極
４までの信号伝播時間が大きいという課題があった。However, in the input protection circuit C4 of FIGS. 3 and 4, since the resistor RI is formed by the P impurity diffusion region 6, the parasitic capacitance between it and the N− impurity diffusion region 5 is large. As a result, there was a problem that the signal propagation time to the gate electrode 4 of the transistor Q2 was long.
また、従来の半導体装置の入力保護回路の他の例が第５
図、第６図（第５図の断面図）に示される。すなわち、
入力保護回路ＣＩ ’ は、ポリシリコン層１０で形成
される抵抗Ｒ２と、トランジスタＱ３とにより構成され
ており、従って、第３図、第４図の回路に比較して抵抗
Ｒ２の寄生容量は著しく小さくなる。この結果、入力信
号の内部ゲートへの信号伝播時間は短かくなる。Another example of the conventional input protection circuit for a semiconductor device is the fifth example.
6 (a sectional view of FIG. 5). That is,
The input protection circuit CI' is composed of a resistor R2 formed of a polysilicon layer 10 and a transistor Q3. Therefore, the parasitic capacitance of the resistor R2 is significantly smaller than the circuits shown in FIGS. 3 and 4. becomes smaller. As a result, the signal propagation time of the input signal to the internal gate is shortened.
しかしながら、第４図、第５゛図の回路においては、大
容量の静電気に対して大電流がトランジスタＱ３を介し
て流れるために、ポリシリコン層抵抗Ｒ２は溶断し易い
という課題があった。However, the circuits shown in FIGS. 4 and 5 have a problem in that the polysilicon layer resistor R2 is easily blown out because a large current flows through the transistor Q3 in response to a large amount of static electricity.
従って、本発明の目的は、配線を溶断しにくくして、静
電耐圧の向上および入力信号伝播時間の短縮を図ること
にある。Therefore, an object of the present invention is to improve the electrostatic withstand voltage and shorten the input signal propagation time by making the wiring less likely to be blown out.
上述の課題を解決するための手段は第１図に示される。 A means for solving the above problem is shown in FIG.
すなわち、入力パッドＰ。側に接合ダイオードＤ、、Ｄ
２を接続し、内部ゲートＱ２側に導電層（たとえばポリ
シリコン）より形成される抵抗Ｒ２を接続する。That is, the input pad P. Junction diodes D,,D on the side
2 is connected, and a resistor R2 formed of a conductive layer (for example, polysilicon) is connected to the internal gate Q2 side.
上述の手段によれば、抵抗Ｒ２の寄生容量は小さく、従
って、入力信号の内部ゲートへの伝播時間は短かくなる
。また、大容量の静電気はダイオードＤ１ もしくはＤ
２を介して電源端子Ｖ。。もしくはＧＮＤに流れるので
、抵抗Ｒ２には大電流は流れず、従って、抵抗Ｒ２は溶
断しにくい。According to the above measures, the parasitic capacitance of the resistor R2 is small, and therefore the propagation time of the input signal to the internal gate is shortened. Also, a large amount of static electricity can be removed by diode D1 or D.
2 to the power supply terminal V. . Alternatively, since it flows to GND, a large current does not flow through the resistor R2, and therefore, the resistor R2 is difficult to blow out.
第１図をその断面図である第２図を参照して説明する。 FIG. 1 will be explained with reference to FIG. 2, which is a sectional view thereof.
なお、第２図においては、接合ダイオードＤ１ は図示
していないが、接合ダイオードＤ２と並列に形成されて
おり、たとえばＮ−ウェルとその中に設けられたＰ＋不
純物拡散領域とにより形成し、Ｎ−ウェルを電ＲＶ ｃ
ｃに接続する。Although the junction diode D1 is not shown in FIG. 2, it is formed in parallel with the junction diode D2, and is formed by, for example, an N-well and a P+ impurity diffusion region provided therein. -Electrify the well RV c
Connect to c.
第１図、第２図の入力保護回路０１″においては、接合
ダイオードＤ１、Ｄ２により入力パッドＰａに印加され
た大容量の静電気を電源端子Ｖ。Ｃ，ＧＮＤに吸収する
。他方、通常の入力信号は、ポリシリコン層抵抗Ｒ２（
１０）を介して入゛カゲートＱ２に伝播する。この場合
、ポリシリコン層１０、絶縁層９．２、および基板１に
より形成される容量、すなわち寄生容量は、フィールド
酸化膜２が非常に厚いので、小さい。従って、入力信号
の入カゲートＱ２への伝播時間は短かい。In the input protection circuit 01'' shown in FIGS. 1 and 2, a large amount of static electricity applied to the input pad Pa is absorbed into the power supply terminals V.C and GND by the junction diodes D1 and D2.On the other hand, the normal input The signal is transmitted through the polysilicon layer resistance R2 (
10) to the input gate Q2. In this case, the capacitance formed by the polysilicon layer 10, the insulating layer 9.2, and the substrate 1, that is, the parasitic capacitance, is small because the field oxide film 2 is very thick. Therefore, the propagation time of the input signal to the input gate Q2 is short.
以上説明したように本発明によれば、静電耐圧の向上お
よび入力信号伝播時間の短縮を、配線等の溶断を招くこ
となく達成できる。As described above, according to the present invention, it is possible to improve electrostatic withstand voltage and shorten input signal propagation time without causing wiring or the like to melt.
第１図は本発明に係る半導体装置の一実施例を示す回路
図、
第２図は第１図の断面図、
第３図、第５図は従来の半導体装置の回路図、第４図、
第６図は、それぞれ、第３図、第５図の断面図である。
Ｐａ・・・入力パッド、
ＣＩ＋ＣＩ’ 、Ｃ２”・・・入力保護回路、Ｄ１、
Ｄ２・・・接合ダイオード、
Ｒ２・・・導電層（ポリシリコン）抵抗、Ｃ２・・・入
力バッファ。FIG. 1 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional view of FIG. 1, FIGS. 3 and 5 are circuit diagrams of conventional semiconductor devices, and FIG.
FIG. 6 is a sectional view of FIG. 3 and FIG. 5, respectively. Pa...Input pad, CI+CI', C2"...Input protection circuit, D1,
D2... Junction diode, R2... Conductive layer (polysilicon) resistance, C2... Input buffer.
Claims (1)
間に接続された保護回路としての半導体装置であって、 前記入力パッドに接続された不純物領域と基板とにより
形成され、電源に接続される接合ダイオード（Ｄ＿１、
Ｄ＿２）と、 該接合ダイオードの不純物領域と前記内部ゲートとの間
に接続された金属層（Ｒ＿２）と、を具備した半導体装
置。[Claims] 1. A semiconductor device as a protection circuit connected between an input pad (P_0) and an internal gate (Q_2), comprising an impurity region connected to the input pad and a substrate. A junction diode (D_1,
D_2); and a metal layer (R_2) connected between the impurity region of the junction diode and the internal gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63063631A JPH01238063A (en) | 1988-03-18 | 1988-03-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63063631A JPH01238063A (en) | 1988-03-18 | 1988-03-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01238063A true JPH01238063A (en) | 1989-09-22 |
Family
ID=13234887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63063631A Pending JPH01238063A (en) | 1988-03-18 | 1988-03-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01238063A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635745A (en) * | 1994-09-08 | 1997-06-03 | National Semiconductor Corporation | Analog multiplexer cell for mixed digital and analog signal inputs |
-
1988
- 1988-03-18 JP JP63063631A patent/JPH01238063A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635745A (en) * | 1994-09-08 | 1997-06-03 | National Semiconductor Corporation | Analog multiplexer cell for mixed digital and analog signal inputs |
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