JPH01235268A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to accomplish both higher integration and larger capacitance by a method wherein an oxidation-resisting property is given to the first mask to be used for cutting grooves, a stepping is provided on the side face of a columnar projection by the groove cutting conducted in two stages using the first and the second masks, and a diffusion layer which becomes a memory node is formed on the lower side face of said stepping. CONSTITUTION:The first masks 21 covering each memory cell region are formed on a substrate. The first masks 21 are composed of an SiO film 211, an oxidation- resistant Si3N4 film and an SiO2 film 213. The first groove 41 is formed using the first mask as an etching mask, a plurality of columnar projections 3 are arranged and formed, and the second oxidation-resistant mask 23 is formed on the side face of each columnar projection 3. The second groove 4 is formed in the first groove 41 using the first and the second masks as etching-resistant masks, and a stepping 5 is formed on the side face of each columnar projection 3. Subsequently, an AsSG film 24 is formed by deposition on the whole surface. Then, a heat treatment is conducted, As is diffused from the AsSG film 24 to the lower side face which is not covered by a mask, and an n<-> type layer 6, which becomes an electrode on one side of a capacitor and also becomes a memory node, is formed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a dynamic RAM (DRAM) in which a memory cell is configured by a MOS capacitor and a MOSFET.
and its manufacturing method.

(Prior Art) MOS type DRAMs are becoming more highly integrated and have a larger capacity due to miniaturization of elements. As a DRAM structure suitable for high integration and large capacity, semiconductor columnar protrusions are arranged in each memory cell area by forming grooves vertically and horizontally in the semiconductor substrate, and MOS capacitors and MOSFETs are placed on the side surfaces of each columnar protrusion. It has been proposed to vertically stack (for example, Japanese Unexamined Patent Publication No. 152056/1983). Such a RAM structure is shown in FIGS. 14(a) and 14(b). Si substrate 8
1, first, grooves are formed by anisotropic etching, and a plurality of columnar projections 82 are arranged and formed. An element isolation insulating film 83 is embedded in the bottom of the trench. A capacitor insulating film 84 is formed on the lower side surface of each columnar projection 82, and a capacitor electrode 85 serving as a plate electrode is embedded in the groove. A gate electrode 88 is formed on the upper side surface of the columnar projection 82 with a gate insulating film 87 interposed therebetween. Capacitor electrode 85 and gate electrode 88 are separated by an insulating film 86. Then, an n-type layer 91 that becomes the source or drain of the MOSFET is formed on the upper end surface of the columnar protrusion 82, and the entire surface is flattened with an insulating film 89, 90. The bit line 9 consists of a film of
3 is arranged. As is clear from the 14th m (a), the gate electrode 88 surrounds the columnar projection 82 and
These lines are arranged continuously in one direction and serve as word lines.

In this way, the DRAM structure of FIG. 14 uses the bottom of the trench as an element isolation region, and the MOS capacitor and
Since the OSFETs are stacked vertically to form an integrated structure, the area occupied by the memory cell is small, and high integration is possible.

However, in the DRAM structure shown in FIG. 14, the bit line 93 is connected to the n-type layer formed on the upper end surface of the columnar projection 82 via the contact hole 92. Therefore, the size of the upper end surface of the columnar protrusion is determined by the size of the bit line contact hole 92 and the alignment margin between the bit line contact and the upper end surface of the columnar protrusion 82 . Therefore, the upper end area of the columnar protrusion 82 cannot be made the minimum size for processing by using the minimum design rule. Also, M.O.
Although it is desirable to form an n-type layer on the semiconductor side of the S capacitor, which serves as one electrode of the capacitor and serves as a storage node, it is difficult to form this n-type layer in the DRAM structure shown in FIG. This is because a capacitor must be formed on the lower side surface of the columnar protrusion before forming the gate electrode, and in order to selectively dope only the side surface of the capacitor region with impurities, the MOSFET formation region must be covered with some kind of mask. This is necessary because this is difficult after groove formation.

(Problems to be Solved by the Invention) As described above, the conventional DRAM uses an array of minute semiconductor columnar protrusions to form a memory cell in which a MOS capacitor and a MOSFET are vertically stacked on the side surface of each columnar protrusion. However, there was a limit to the miniaturization of memory cells due to the need for alignment margins for bit line contacts. Also, MOSFE
There is a problem in that it is difficult to form a diffusion layer that will serve as a storage node on the substrate side of the MOS capacitor that is buried under the T.

The present invention solves these problems and achieves - high integration of layers;
The purpose of the present invention is to provide a DRAM that enables a large capacity and a method for manufacturing the same.

[Structure of the invention]

(Means for Solving the Problems) A DRAM according to the present invention has firstly a plurality of semiconductor columnar projections arranged in a matrix on a substrate, a MOS capacitor formed at the lower part of the side surface of each columnar projection, and a MOSFET formed at the upper part. The memory cell is configured by M
A structure in which a source or drain diffusion layer of an OSFET is formed and a bit line contacts therein, and the bit line is brought into contact with the upper end surface of a columnar protrusion in a self-aligned manner without providing a contact hole. .

Second, in the above basic structure, the present invention has a step in the middle of the side surface of the columnar protrusion, a diffusion layer serving as a storage node is formed on the lower side surface of the step, and a capacitor insulating film is provided on the lower side surface. It is characterized in that a capacitor electrode is formed.

The present invention also provides a memory cell in which a plurality of semiconductor columnar protrusions are arranged in a matrix on a substrate, a MOS capacitor is formed at the lower part of the side surface of each columnar protrusion, and a MOSFET is formed above the columnar protrusion, and a MOSFET is formed on the upper end surface of the columnar protrusion. This is a method for manufacturing a DRAM having a structure in which a source or drain diffusion layer is formed and a bit line is in contact with the layer, in which a first mask containing an oxidation-resistant film is first formed on a semiconductor substrate, and then etched by anisotropic etching. First grooves running vertically and horizontally are formed in the substrate, and a plurality of columnar projections are arranged and formed.

Next, a second mask containing an oxidation-resistant film is formed on the side surface of each columnar projection, and anisotropic etching is performed using the first and second masks to form a second groove in the substrate. Then, a MOS capacitor is formed on the lower side surface of the columnar projection with the first and second masks remaining. At this time, the second
Using this mask, a diffusion layer that will become a storage node is formed on the lower side surface of the columnar projection. The capacitor electrode is buried up to the second trench. After that, the mask of node 2 is removed, and a gate electrode is formed on the upper side surface of the columnar projection with a gate insulating film interposed therebetween. Then, with the entire surface covered with an insulating film, the first mask is removed to expose only the upper end surface of the columnar protrusion, and a diffusion layer that becomes the source or drain of the MOSFET is formed here, and a diffusion layer that is connected to this upper end surface is formed. Lay out the bit line.

(Function) According to the present invention, by using the first mask for trenching as an oxidation-resistant mask and leaving it until the final stage of device formation, the bit line contact region is self-aligned with the upper end surface of the columnar protrusion. This eliminates the need for alignment margins for bit line contacts. As a result, memory cells can be miniaturized, and DRAMs can be highly integrated and have a large capacity.

Also, regarding soft errors, miniaturization reduces the substrate area involved in soft errors, so soft errors in bit line mode are suppressed.

Soft errors in the cell mode are similarly suppressed because each memory cell is formed on the side surface of the columnar protrusion, so that the a-ray incident obliquely is interrupted by the arrangement of the columnar protrusions. In addition, by creating a step on the side surface of the columnar protrusion by two-stage trenching using the first and second masks, and forming a diffusion layer that will serve as a memory node on the lower side surface of the step, excellent characteristics can be achieved. A DRAM cell can be obtained.

(Example) The present invention will be explained in detail below.

FIG. 1 is a plan view showing 4 bits of a DRAM according to an embodiment. FIGS. 2(a) and 2(b) are sectional views taken along line AA' and line BB' in FIG. 1, respectively. A p-type layer 2 with a higher concentration is formed on the surface of the high-resistance p-type Si substrate 1.
A plurality of minute columnar protrusions 3 (31, 32, . . .
) are arranged in a matrix. A step 5 is formed on the side surface of the columnar protrusion 3. An n-'' type layer 6 which becomes a storage node is formed on the side surface below the step 5, and a capacitor insulating film 7 is formed on this surface to form a groove. A capacitor electrode 8 is embedded in the n-type layer 4. The depth of the n-type layer 6 is set to be approximately equal to or deeper than the upper side surface position of the step 5. The capacitor electrode 8 is continuously formed as a plate electrode common to all memory cells. A p+ type layer 9 for element isolation is diffused at the bottom of the groove. From the step 5 of each columnar projection 3 A gate electrode 12 (121°, 122, . . . ) is formed on the upper side surface with a gate insulating film 11 interposed therebetween.The gate electrode 12 and the capacitor electrode 8 are
They are vertically stacked and buried in the trench 4, separated by the insulating film 10. The gate electrode 12 surrounds the columnar projection 3 and is continuously arranged in one direction of the matrix, and serves as a word line. The remaining concave portion in which the gate electrode 12 is buried is filled with a polycrystalline silicon film 14 via an insulating film 13 and is planarized. The surface of the substrate on which the capacitor electrode and the gate electrode are buried is covered with an insulating film 15, on which a bit line 17 (171°, 172, . . . ) made of films A and E is disposed. An n+ type layer 16 that becomes the source or drain of the MOSFET is diffused on the upper end surface of each columnar protrusion 3, and the bit line 17 is self-contained with respect to this n type layer 16 without going through a PEP process for forming a contact hole. Consistent direct contact.

3(a) to 3(i) are cross-sectional views corresponding to FIG. 2(a) showing the manufacturing process of this DRAM.

To explain the manufacturing process in detail, first, a p-type Si substrate 1 is
Boron, for example, at a dose of 5 x 1012/cM2,
Ion implantation is performed at an accelerating voltage of 100 keV to form a p-type layer 2 having a higher concentration than the substrate. This p″″ type layer 2 is MO
This is for forming the channel region of the SFET, and the thickness is approximately 2 μm.

This p-type layer may be formed by epitaxial growth instead of ion implantation. A first mask 21 covering each memory cell area is formed on this substrate by a conventional photolithography method. Specifically, the first mask 21 is a 5i02 film 210. of 10 nm thick formed by thermal oxidation. It is composed of a 200 nm thick 5L3N4 film which is an oxidation-resistant film, and a 5i02 film 213 with a 600 nm thickness deposited by CVD (FIG. 3(a)). Using this first mask as an etching mask, a first groove 41 is formed to a depth that penetrates through the p-type layer 2 by reactive ion etching (RIE), and a plurality of columnar projections are formed by this groove 41. 3 is formed in an array. After that, each columnar projection 3
Si3N4 film 23 serving as a mask for the oxidation-resistant film 2 is placed on the side surface of the
form. More specifically, first, a 5i02 film 22 with a thickness of 20 nm is deposited by the CVD method, and then carbon dioxide is further deposited on this.
A Si3N4 film 23 of approximately 200 nm is deposited using the VD method, and anisotropic etching is performed using the RIE method to leave these laminated films only on the side surfaces of the columnar protrusions 3 (FIG. 3(b)).
. Then, using the first and second masks as etching-resistant masks, the first groove 4 is etched by RIH containing chlorine gas.
A second groove 42 having a depth of approximately 3 μm is further formed within the groove 1 . As a result, a step 5 is formed on the side surface of each columnar projection 3. After the etched surface is subjected to a predetermined post-treatment, an As5G film 24, which is a glass film containing arsenic (As) of about 50 nm, is deposited on the entire surface by CVD. Then, for example, heat treatment is performed at 1000°C for about 60 minutes, and the AsSG film 24 to A
s is diffused to form an n-type layer 6 which will become one electrode of the capacitor and a storage node (FIG. 3(C)).

At this time, the n-type layer 6 has a surface impurity concentration of, for example, 1 x
It should be about 1019/ax3. Although not shown in the figure, after this, oblique ion implantation of boron, for example, is performed to form the n-type layer 6 in order to form the capacitor into a HIC structure.
A p-type layer can also be formed on the outer periphery of the substrate.

Thereafter, after removing the AsSG film 24 using an ammonium fluoride solution, the entire surface is coated with S i 0 by CVD.
Approximately 1100 nm of the second film 25 is deposited, and this is etched by RIE to leave only the sidewalls of the columnar protrusions 3 as a third mask. Then, using this 5i02 film 25, the substrate was etched by about 0.5 μm by RIE method, and
A third trench 43 is formed to separate the "type layer 6 into each memory cell. In this state, boron ions are implanted at a dose of 5 x 10"/cII2 at an accelerating voltage of 100 keV to form the third trench 43 that separates the trench 4 into each memory cell. A p+ type layer 9 is formed at the bottom of the layer as a channel stopper to ensure element isolation (see Fig. 3).
d)). It is also possible to omit the step of depositing the SiO3 film 25 as the third mask and use the As5G film 24 described above instead. Thereafter, the 5i02 film 25 is removed and thermal oxidation is performed to form a capacitor insulating film 7 of about 10 nm on the lower side surface of the columnar projection 3 (FIG. 3(e)). As this capacitor insulating film, a laminated film of a 5lO2 film and a Si3N4 film may be used, or a metal oxide film such as Ta205, a thermal nitride film, or a suitable combination thereof may be used. Then, a capacitor electrode 8 made of a first layer polycrystalline silicon film is buried in the trench 4 ((f)). Specifically, the phosphorus-doped first layer polycrystalline silicon film was
nm is deposited and etched by a CDE method using CF4 gas, and the surface is buried at approximately the position of the step 5. In this example, the maximum width of the groove 4 is approximately 0.6 μm.
Therefore, if a polycrystalline silicon film with a thickness of about 0.3 μm or more is deposited, the surface will be almost flat, and by etching the entire surface by CDE, a capacitor electrode 8 is buried as shown in the figure. be able to. If the surface cannot be made flat due to the deposition of the polycrystalline silicon film, it is flattened using a fluid film such as photoresist, and the entire surface is etched under conditions such that the etching rates of the fluid film and the polycrystalline silicon film are approximately equal. This structure can be obtained by

In this way, the first mask 21 and the second mask of each columnar projection 3 are
MO using the lower side not covered by the mask 23 of
An S capacitor is formed.

Next, the Si3N4 film 23 serving as the second mask covering the upper side surface of the columnar protrusion 3 where the MOSFET is to be formed and the 5i02 film 22 therebelow are removed, and the temperature is 900°C.
Thermal oxidation is performed for about 60 minutes in a 2+HC atmosphere to form a gate insulating film 11 on the upper side surface of the columnar projection 3. At the same time, a film of about three times the thickness of 5i is deposited on the capacitor electrode 8.
02 film 10 is formed. After this, a second layer of phosphorus-doped polycrystalline silicon film is deposited to a thickness of approximately 25 nm, and then subjected to RIE
A gate electrode 12 is formed on the upper side surface of each columnar projection 3 (FIG. 3(g)). Gate electrode 1
2 are left in a self-aligned manner all around each columnar projection 3 without a mask, but it is necessary to arrange them continuously in one direction of the matrix to form a word line. Therefore, in practice, a photoresist mask is formed in the trench region along the word line direction. In this way, a MOSFET is formed using the upper side surface of the columnar projection 3.

After that, the surface of the gate electrode 12 is thermally oxidized to 5i02
Cover with film 13, and place a first layer polycrystalline silicon film I%14 in the recess.
embed and planarize the entire substrate.

The 5i02 film 13 may be formed by CVD instead of thermal oxidation. In order to fill the polycrystalline silicon film 14 flatly, it is sufficient to deposit the polycrystalline silicon film over the entire surface, planarize the surface with a photoresist, and then etch the entire surface by dry etching at an equal etching rate.

Thereafter, for example, thermal oxidation is performed in water vapor at 850° C. for about 10 minutes, and the surfaces of the gate electrode 12 and the buried polycrystalline silicon film 14 are covered with a 5i02 film 26 (see Fig. 3 (h).
)). At this time, the upper end surface of the columnar projection 3 is covered with the Si3N4 film 212, which is an oxidation-resistant mask, and almost no 5i02 film is formed. Next, the Si3N4 film 212 is etched away using, for example, a gas containing CF4 gas, and the As
Dose amount: 5 x 10”/cm2. Acceleration voltage: 40k
Ions are implanted at eV to form a MOS on the upper end surface of each columnar protrusion 3.
An n-type layer 16 is formed to become the source or drain of the FET. If necessary, dose m3 x 10 phosphorus at this time.
13/cm2. An n-type layer is formed under the n-type layer 16 by ion implantation at an acceleration voltage of 100 keV, and a MOS
The FET has an LDD structure. Then, for example, the temperature is 850
℃, thermal oxidation is performed in a steam atmosphere, and 5i is deposited on the substrate surface.
02 film 15 is formed. The 5i02 film 15 has a thickness of about 40 nm on the surfaces of the gate electrode 12 made of polycrystalline silicon film and the buried polycrystalline silicon film 14, and has a thickness of about 10 nm on the upper end surface of the columnar protrusion 3.

Therefore, the 5i02 film is etched using an ammonium fluoride solution to selectively expose only the upper end surface of the columnar projection 3. Then, by vapor deposition and patterning of a W film, a bit line 17 that intersects the word line is connected to the n-type layer 16.
(Fig. 3(i)). Thus, in this embodiment, only the upper end surface of the columnar projection 3 can be exposed in a self-aligned manner without requiring a PEP process for bit line contact.

The DRAM according to this embodiment has the following features.

The bit line and the source or drain of the MOSFET are connected in a self-aligned manner without using a contact hole forming process including photolithography. Therefore, there is no need for an alignment margin when using a photolithography process, and the size of the upper end surface of the columnar protrusion is not limited by the alignment margin as in the prior art. As a result, by making the columnar protrusions as small as possible to the processing limit, a fine memory cell can be realized, and DRAMs can be highly integrated and have a large capacity. In addition, by reducing the board area involved in soft errors, soft errors in bit line mode can be reduced.
The miniaturization of memory cells also reduces soft errors in cell mode.

Since the MOS capacitor utilizes the entire circumference of the lower side surface of the columnar protrusion, a relatively large storage capacity can be secured. MOSFETs also utilize the entire circumference of the upper side of the columnar protrusion, so the channel width can be increased.In order to obtain a large channel conductance, the channel base can be shortened, and the gate insulating film can be made thinner than necessary. Therefore, excellent characteristics with less threshold fluctuation due to hot electrons can be obtained. Further, a step is formed in the middle of the columnar protrusion, and the n-type layer serving as a storage node is diffused to a depth equal to or deeper than the height of the step. That is, the bonding surface position of the n-type layer is formed inward from the upper side surface position. This is a MOS formed on the upper side.
This is meaningful in improving the characteristics of the FET. That is, the n-type layer serving as a storage node is also the source or drain of the MOSFET, and if this layer is formed shallower than the height of the step, the channel region of the MOSFET will bend at the step. This is because the channel base is not determined by the straight distance between the side surfaces of the columnar projections, and defects are generally likely to occur at the corners, which enter the channel region and make the characteristics of the MOSFET unstable. Such a problem can be avoided by forming the n-type layer with a diffusion depth at least equal to the height of the step as in the embodiment.

Further, the method of this embodiment includes digging a first groove in the substrate using a first mask, further forming a second mask on the side surface of the first groove, and forming a second groove on the bottom of the first groove. The process of digging a trench is adopted. Only by using these first and second masks can an n-type layer, which will become a storage node, be selectively formed on the lower side surface of the columnar protrusion under the MOSFET formation region. Further, by leaving the first mask used for forming the trench until near the final step, self-alignment of the bit line contact becomes possible, thereby making it possible to miniaturize the memory cell.

In the above embodiment, the case of the oven bit line method was explained, but the present invention is applicable to the DR of the folded bit line method.
It can be similarly applied to AM. A plan view in that case is shown in FIG. 4 in correspondence with FIG. 1.

FIGS. 5(a) to 5(e) are cross-sectional views of the manufacturing process of an embodiment in which the steps of patterning the gate electrode and subsequent planarization of the substrate are changed from the previous embodiment.

As shown in FIG. 3(f), the process is the same as the previous embodiment until the capacitor electrode 8 is buried and the nitride film 23, which is the mask of the node 2, is removed and the gate insulating film 11 is formed. . After this, a phosphorus-doped polycrystalline silicon film 12 for forming a gate electrode is deposited to a thickness of approximately 200 nm, and a fluid film 31 such as photoresist is applied to the entire surface to flatten it (FIG. 5(a)). . Then, the surface of the Si3N4 film 212 is exposed by etching the entire surface by a dry etching method under the condition that the etching speed of the fluid film 31 and the polycrystalline silicon film 12 are equal, for example, a CDE method using a gas containing cF4 gas. Figure 5(b)). Next, by normal photolithography and anisotropic dry etching, a polycrystalline silicon film 12 is left on the side surfaces of the columnar protrusions 3 and in the wiring region serving as a word line to form a gate electrode and a word line. Then, thermal oxidation is performed at a temperature of, for example, 850° C. in a steam atmosphere to form a 5i02 film 32 of approximately 1100 nm on the surface of the gate electrode 12 (FIG. 5(C)). Next, as a viscous CVD5i02 film on the entire surface, for example, boron.
A phosphorus glass film (BPSG film) 33 is deposited on the entire surface, and after it is fluidized and flattened at a temperature of about 900° C., the entire surface is dry-etched to expose the Si3N4 film 212 (FIG. 5(d)). ). Next exposed 5i3N41I2
12 is selectively etched away, and an n-type layer 16 is formed on the upper end surface of the columnar projection 3 by ion implantation. after that,
The 5i02 film 21t on the surface of the n-type layer 16 is removed using an ammonium fluoride solution without a mask, and the bit line 17 is formed by depositing and patterning a W film (FIG. 5(e)).

This embodiment also provides the same effects as the previous embodiment. Further, in this embodiment, since a thicker 5i02 film 33 is left below the bit line than in the previous embodiment, the capacitance of the bit line relative to the substrate or word line can be reduced, and the speed of the DRAM can be increased.

Improved performance is achieved.

FIGS. 6(a) and 6(b) are similar to FIGS. 5(b) and (c) of the previous embodiment.
) This is an example in which the process corresponding to the above is modified. In etching after planarization with the polycrystalline silicon film 12 for gate electrode and the fluid film 31, the planarized surface is located above the upper end surface of the columnar protrusion 3 by an amount equivalent to the thickness of the gate electrode film.
Adjust the etching amount (Fig. 6(a)). This is a guideline for ensuring that the upper edge of the gate electrode 12 is located below the upper end surface of the columnar protrusion 3 when patterning the gate electrode 12 in the next step (FIG. 6(b)). . Thereby, the parasitic capacitance of the gate electrode and word line can be reduced, and the capacitance of the bit line can also be reduced.

In the above embodiment, a step is formed between the MO5FET formation region and the capacitor formation region on the side surface of the columnar protrusion, but this step can be eliminated. FIGS. 7(a) and 7(b) show the main steps of such an embodiment. A Si3N4 film 23 is formed on the side surface of the columnar protrusion 3 obtained by forming the first groove in the same manner as in the above embodiment, and a second groove 42 is formed by etching (FIG. 7(a)).
. After that, by dry etching containing CF4 gas,
The Si surface exposed in the second groove 42 is etched to reduce the level difference (FIG. 7(b)). After this, through the same steps as in the previous example, the MOS capacitor and MOSFET
The bit line is arranged in contact with the upper end surface of the columnar projection in a self-aligned manner.

According to this embodiment, even if the diffusion depth of the n-type layer serving as a storage node is shallow, the MOSFET is
No corner enters the channel region of M
The characteristics of the OSFET can be improved.

FIGS. 8(a) to 8(c) show the main steps of an embodiment in which element isolation is performed more reliably. Figure 3 (b) above
After forming the second groove 42 through the process of
For example, boron ions are implanted into the bottom of the groove 42 at 100 keV and at a dose of j13 x 1012/cm2.
A p+ type layer 9 is formed to serve as a channel stopper. At this time, ion implantation is performed perpendicular to the substrate. After that, CVDS
An iO2 film 41 is deposited on the entire surface to a thickness of about 1100 nm, and a fluid film, such as a photoresist 42, is further applied and flattened. Then, for example, the photoresist film 42 is etched in an atmosphere containing 02 gas, and only the bottom of the groove is etched with about 0.
．． A thickness of about 5 μm is left (Fig. 8(a)). Using this photoresist 42 as a mask, the 5i02 film 41 is selectively etched using an ammonium fluoride solution, leaving the 5i02 film 41 only at the bottom of the groove 4. Thereafter, an arsenic glass film (AsSG film) 43 containing arsenic as an impurity is deposited on the entire surface to a thickness of about 70 nm. Then, a heat treatment is performed at, for example, 1000 DEG C. in a nitrogen atmosphere to form an n-type layer 6 by diffusion from the As5G film 43 (FIG. 8(b)). At this time, since the thick 5i02 film 41 remains at the bottom of the trench, the n-type impurity is not diffused. After this, As5G film 4
3 is removed, a capacitor insulating film 7 is formed, and a capacitor electrode 8 made of a first layer polycrystalline silicon film is buried in the trench (FIG. 8(C)). After this, a DRAM can be formed according to the steps starting from FIG. 3(g).

According to this embodiment, adjacent memory cells can be reliably isolated by the thick 5i02 film 41 and the p-type layer 9. Furthermore, as a result of providing the thick 5i02 film 41, the impurity concentration of the p-type layer 9 can be lowered, thereby making the MOS
Junction leakage between the capacitor and the n-'J1 layer 6 can be reduced. This leads to improved data retention characteristics of the DRAM.

FIGS. 9(a) and 9(b) show main steps of another embodiment that achieves the same effect as the embodiment shown in FIG. 8.

5 used as the third mask in the step shown in FIG. 3(d) above.
After removing the i02 film 25, a CVD5i02 film 5 is applied to the entire surface.
1 is deposited to a thickness of about 70 nm, and then a photoresist 52 is applied and planarized.

Then, the photoresist 52 is etched by the RIE method in a gas atmosphere containing 02 gas, and the bottom of the groove is etched with approximately 0.
．． Approximately 5 μm is left (Fig. 9(a)).

Using the remaining photoresist 52 as a mask, the 5i02 film 51 is selectively etched using, for example, an ammonium fluoride solution, leaving the 5i02 film 51 only at the bottom of the groove.

Thereafter, the photoresist 52 is removed, a capacitor insulating film is formed, and the DR is formed, for example, according to the steps from FIG. 3(f) onwards.
AM can be obtained.

Also in this embodiment, it is possible to reliably isolate adjacent memory cells. Also, in this example, M
5i02 after forming the n-type layer in the OS capacitor region
Since the process of leaving the membrane 51 at the bottom of the groove is performed,
The thickness of this 5i02 film 51 is less likely to change in subsequent steps, resulting in highly uniform element isolation characteristics.

As another method for forming a thick 5i02 film for element isolation at the bottom of the trench, for example, it is useful to selectively form a Si3N4 film on the side surfaces of the trench and oxidize it in a water vapor atmosphere.

This allows a 5i02 film of about 70 nm to be easily formed at the bottom of the trench.

In the above embodiments, in order to continuously arrange gate electrodes as word lines, the gate electrode patterning process involves photolithography, in which a mask such as a photoresist is formed between adjacent memory cells along the word line direction. The process was used. However, by considering the memory cell arrangement, it is possible to pattern the gate electrode and word line without using photolithography using a photoresist. Such an embodiment will now be described.

FIGS. 10(a) and 10(b) show DRAMs according to such embodiments.
FIG. 2 is a plan view and a sectional view taken along line AA'.

Portions corresponding to those in the previous embodiment are designated by the same reference numerals and detailed explanations will be omitted. In this embodiment, as shown in FIG. 10(a), the columnar protrusions 3 forming the memory cells are arranged at intervals a1 in the word line direction and at intervals a1 in the bit line direction. At this time, the distance a is set to such a value that the trench is automatically filled when the second layer polycrystalline silicon film 12 for the gate electrode and word line is deposited by, for example, the CVD method.

Specifically, the distance a is set to a value smaller than twice the thickness of the second layer polycrystalline silicon film 12. For example, when the second layer polycrystalline silicon film 12 is approximately 20 nm, the distance a is set to 40 nm.
The thickness is 0 nm or less, for example, 300 nm. The distance in the bit line direction is set to a value larger than twice the film thickness of the second layer polycrystalline silicon film 12, for example, b-600 for a film thickness of 200 nm.
Let it be nm. By having such a columnar projection arrangement,
After depositing the second layer polycrystalline silicon film 12, by etching the entire surface using anisotropic etching,
The illustrated state in which the gate electrodes 12 are continuous in the word line direction and separated in the bit line direction can be obtained.

In this embodiment, the distance a between the bit line contacts may be smaller than the distance C between the bit lines shown in FIG. 10(a). Therefore, in this embodiment, after exposing the upper end surface of the columnar protrusion 3, W) 61 using WF6 gas or the like is selectively grown on the exposed Si surface to a thickness of about 100 nm, and on this, A,
Deposit an e-5t-Cu film of approximately 400 nm and perform RIE.
The bit line 17 is formed by patterning by a normal photolithography method using a photolithography method.

According to this embodiment, the process is simplified because a photolithography process using a photoresist is not used for patterning the gate electrode/word line, and the density of integration can be increased because the memory cell spacing becomes smaller. . In addition, since the W film 61 is selectively grown on the base of the bit line, A,
When etching the bit line of the i'-Si--Cu film, the W film 61 acts as a stopper, and it is possible to prevent defects such as short circuit between the substrate and the bit line due to etching of the substrate.

FIGS. 11(a) and 11(b) are diagrams for specifically explaining how continuous word lines are formed according to this embodiment. Here, a memory cell area for 4 bits is shown in a plan view. The interval d in the figure is the width of the columnar protrusion 3 in the word line direction, and b.

C is the distance between columnar protrusions in the bit line direction and the word line direction, respectively. W is the thickness of the second layer polycrystalline silicon film 12. If the value of the interval C is larger than twice the film thickness W, if the polycrystalline silicon film is etched without using a resist process, the polycrystalline silicon film will be left only on the side surfaces of the columnar protrusions 3, and the gate Each electrode is isolated (first
Figure 1(a)). On the other hand, if the value of the interval C is set smaller than twice W and the value of the interval is set larger than twice W, the gate electrodes are connected only in the word line direction (11th
Figure (b)).

FIGS. 12(a) and 12(b) are examples of specific spacing setting methods for making gate electrodes continuous in the word line direction as described above. FIG. First, as shown in (a), a mask material 62 for substrate etching is formed into a predetermined shape. At this time, the width R1 of the mask material 62 is set to the interval S. Next, mask material 62 is applied to the entire surface.
A mask material 63 made of the same material is deposited. At this time, the film thickness P of the second layer mask material 63 is determined by the final spacing between the columnar protrusions in the word line direction.

For example, if R-0.5 um and S-0.5 um, and the final desired spacing is S'-0.3 μm, then the film thickness P should be about 0.1 μm. In this state, the entire surface is etched by anisotropic etching, leaving the second layer mask material 63 on the side walls of the first layer mask material 62. When the substrate is etched by the RIE method using these mask materials 62 and 63, grooves with an interval S'-0.3 .mu.m between the columnar protrusions 3 can be formed.

If such a method is used, the interval between the columnar protrusions 3 can be set to be equal to or less than the minimum processing dimension. This allows DRA
It is possible to further increase the density of M.

FIGS. 13(a) to 13(f) show the manufacturing process of another embodiment in which the method of separating the capacitor electrode and the gate electrode is different.

After the step shown in FIG. 3(f) in the previous embodiment, a 5i02 film 71 of, for example, about 700 nm is deposited on the entire surface by CVD, and a photoresist 72 is applied to the surface to flatten the surface (see FIG. 13(f)). a)). Next, the entire surface of the photoresist 72 and the 5i02 film 71 are etched by RIE under conditions such that the etching rate is the same, and a 5i film of about 100 nm is etched on the capacitor electrode 8 that has already been buried.
02 film 71 is left (FIG. 13(b)). At this time, it is desirable that the etching atmosphere has a selectivity of about 10 times or more to the Si3N4 film 212.

Next, a gate insulating film 11 of about 15 nm is applied to the MOSFET region.
After forming the gate electrode 1 by thermal oxidation, a phosphorus-doped second layer polycrystalline silicon film is deposited to a thickness of, for example, 200 nm, and patterned by normal anisotropic etching to form the gate electrode 1.
2 (Fig. 13(C)). Thereafter, as in the embodiment shown in FIG. 3, an insulating film 13 is formed on the surface of the gate electrode, and a polycrystalline silicon film 14 is buried in the four parts for planarization (FIG. 13(d)). Next, a PSG film 74 of about 400 layers is applied to the entire surface.
After depositing the Si3N4 film 212 to expose the Si3N4 film 212 (FIG. 13(e)), the exposed Si3N4 film 21□ is selectively removed. Then, ion implantation is performed to form an n-type layer 16 that will become a source or drain diffusion layer. Further, a polycrystalline silicon film 17 doped with arsenic over the entire surface.
1 and molybdenum silicide (MoSi2) film 171□
By forming a laminated film and patterning it, a Bi-Sotho line is formed (FIG. 13(f)).

According to this embodiment, it is possible to separate the vertically stacked and buried capacitor electrode 8 from the gate electrode 12 of the MOSFET without using a thermal oxide film. this is,
This is effective in suppressing crystal defects due to stress caused by trench formation and thermal processes, and improving data retention characteristics of memory cells.

In the above embodiments, in order to adjust the threshold value of the MOSFET, a p-type layer is formed by ion implantation etc. on the entire surface of the substrate to the depth of the MOSFET formation region before trench processing. need only be present on the side surface of the columnar protrusion, which is the MOSFET region. Therefore, for example, after forming a columnar protrusion and embedding a canopy, ions may be implanted to adjust the impurity concentration only in the channel region. In this case, since the ion implantation is performed on the substantially vertical side surfaces, the side surfaces are doped with impurities uniformly by performing oblique ion implantation that includes rotation of the wafer. The rotation of Ueno\ may be continuous or 90 degrees.
It may also be rotated discontinuously.

The bit line material may be the W film, A, or 17-8 described in the example.
In addition to the 1-Cu film, other high melting point metals such as molybdenum, silicides of high melting point metals, or a combination of these and polycrystalline silicon films can be used.

In the embodiment, a p-type St substrate is used, but the entire memory cell region can also be formed into a p-type well by boron diffusion, for example. At this time, if the impurity concentration at the bottom of the trench, which becomes the element isolation region, is about I×1017/c113,
The p-type impurity diffusion step for element isolation can be omitted.

Other vehicle inventions can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, an arrangement of semiconductor columnar projections is utilized, and a MOS capacitor and an M
In a DRAM with a structure in which OSFETs are stacked vertically,
By making bit line contacts to the upper end surfaces of columnar protrusions without using the photolithography process for forming contact holes, the memory cell area can be miniaturized to the processing limit, realizing highly integrated and large-capacity DRAMs. can do. Further, according to the present invention, when forming the columnar protrusion, the first. Grooves are formed in two stages using the second mask, and MO
A diffusion layer that becomes a storage node can be selectively formed on the lower side surface of the columnar protrusion that becomes the S capacitor formation region.

Also this first one. By etching the substrate using a second mask and forming a diffusion layer to a predetermined depth or more on the lower side of the columnar protrusion, the channel base of the MOS transistor is determined without including corners in the channel region, resulting in uniformity and stability. Excellent DRAM characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a DRAM according to an embodiment of the present invention;
2(a) and 2(b) are sectional views taken along lines AA' and BB' in FIG. The figure shows a DR using a folded bit line method.
A plan view corresponding to FIG. 1 when the present invention is applied to AM,
5(a) to 5(e) are cross-sectional views showing the manufacturing process of other embodiments of the present invention, and FIGS. 6(a) and 6(b) are main points of embodiments in which the heights of the gate electrodes are different. 7(a) and (b) are sectional views showing the manufacturing process of the main part of an embodiment for eliminating the level difference on the side surface of the columnar protrusion, and FIGS. 8(a) to (c)
9A and 9B are cross-sectional views showing the manufacturing process of the main part of an embodiment that further ensures element isolation, and FIGS. 9(a) and 9(b) show the main part manufacturing process of another embodiment that also ensures element isolation. cross section,
FIGS. 10(a) and 10(b) are a plan view and a sectional view taken along the line AA' of the DRAM according to an embodiment in which the photolithographic process is not used for word line patterning, and FIGS. 11(a) and 11(b) are A diagram for explaining that word lines are connected without using a photo-etching process, and FIGS. 12(a) and 12(b) are cross-sections showing the main steps of an example in which word lines are connected without using a photo-etching process. 13(a) to 13(f) are cross-sectional views showing the manufacturing process of an embodiment in which the isolation insulating films of the capacitor electrode and the gate electrode are different, and FIGS. 14(a) to 13(b) are the conventional DRAM. It is a top view and its AA' cross-sectional view which show an example. DESCRIPTION OF SYMBOLS 1...p-type St substrate, 2...p-type layer, 3(3+. 32,...)...columnar projection, 4...groove, 5...
Step, 6...n-type layer (storage node), 7...capacitor insulation 11, 8...capacitor electrode (first layer polycrystalline silicon film), 9...p medium layer, 10...・Insulating film, 11... Gate insulating film, 12 (121, 122,
...)...Gate electrode (second layer polycrystalline silicon film)
, 13... Insulating film, 14... Third layer polycrystalline silicon film, 15... Insulating film, 16... n medium layer, 17 (1
7+. 172,...)...Bit line, 21...First mask, 211...5i02 film, 212...Si3N
4 film, 213...5i02 film, 22...5i02 film, 23...Si3N4 film (second mask), 24...
・As SG film, 25...5i02 film, 31-33・
...5i02 film, 41...5i02 film, 42...photoresist, 43...As5G film, 51...5i
02 film, 52... photoresist, 61... W film,
62.63...Mask material, 71...5i02 film, 7
2...Fluid membrane, 74...S i 02 membrane. Applicant's representative Patent attorney Takehiko Suzue B Figure 1 Figure 2 Figure 3 Figure 30 Figure 3 5 Figure 5 - Figure 11 Figure 12 Figure 13 Figure 13 Figure 13 Figure 14

Claims (6)

[Claims] (1) A plurality of semiconductor columnar protrusions separated by grooves running vertically and horizontally on a substrate are arranged in a matrix, a MOS capacitor is formed on the lower side surface of each columnar protrusion, a MOSFET is formed on the upper side surface, and a MOSFET is formed on the upper end surface of each protrusion columnar shape. In a semiconductor memory device configured by forming a source or drain diffusion layer of each MOSFET and connecting a bit line to the diffusion layer, the bit line is self-aligned and in contact with the upper end surface of the columnar protrusion. A semiconductor memory device characterized by: (2) A plurality of semiconductor columnar protrusions separated by grooves running vertically and horizontally on the substrate are arranged in a matrix, a MOS capacitor is formed on the lower side surface of each columnar protrusion, a MOSFET is formed on the upper side surface, and a MOSFET is formed on the upper end surface of each columnar protrusion. In a semiconductor memory device configured such that a source or drain diffusion layer of each MOSFET is formed and a bit line is connected to the diffusion layer, the columnar protrusion is connected to the upper part where the MOSFET is formed and the M
A semiconductor memory device having a step between a lower part where an OS capacitor is formed, and a diffusion layer serving as a storage node formed on a side surface of the lower part. (3) The semiconductor memory device according to claim 2, wherein the diffusion layer serving as the storage node is formed to a depth that reaches at least an upper side surface position of the columnar projection. (4) A plurality of semiconductor columnar protrusions separated by grooves running vertically and horizontally on the substrate are arranged in a matrix, a MOS capacitor is formed on the lower side surface of each columnar protrusion, a MOSFET is formed on the upper side surface, and a MOSFET is formed on the upper end surface of each columnar protrusion. A method for manufacturing a semiconductor memory device in which a source or drain diffusion layer of each MOSFET is formed and a bit line is connected to the diffusion layer, the method comprising: forming a first mask including an oxidation-resistant film on a semiconductor substrate; a step of forming first grooves running vertically and horizontally in the substrate by anisotropic etching to form a plurality of semiconductor columnar projections in an array; and a second step of forming an oxidation-resistant film on the side surfaces of the columnar projections.
forming a second groove in the first groove by anisotropically etching the substrate using the first and second masks as etching-resistant masks; forming a diffusion layer to serve as a storage node on the lower side surface of the columnar protrusion using the mask as a diffusion-resistant mask; forming an element isolation layer on the bottom of the second groove;
forming a capacitor insulating film on the lower side surface of the columnar protrusion and embedding a capacitor electrode in the second groove; covering the surface of the capacitor electrode with an insulating film;
forming a gate electrode on the upper side surface of the columnar protrusion via a gate insulating film by removing the mask; and covering the area other than the first mask with an insulating film made of a different material from the first mask. A step of removing the mask to expose the upper end surface of the columnar protrusion, forming a diffusion layer to serve as a source or drain on the exposed upper end surface, and forming a bit line connected to the diffusion layer by depositing and patterning a conductor film. 1. A method of manufacturing a semiconductor memory device, comprising: a step of arranging a semiconductor memory device. (5) A plurality of semiconductor columnar protrusions separated by grooves running vertically and horizontally on the substrate are arranged in a matrix, a MOS capacitor is formed on the lower side surface of each columnar protrusion, a MOSFET is formed on the upper side surface, and a MOSFET is formed on the upper end surface of each columnar protrusion. A method for manufacturing a semiconductor memory device in which a source or drain diffusion layer of each MOSFET is formed and a bit line is connected to the diffusion layer, the method comprising: forming a first mask including an oxidation-resistant film on a semiconductor substrate; a step of forming first grooves running vertically and horizontally in the substrate by anisotropic etching to form a plurality of semiconductor columnar projections in an array; and a second step of forming an oxidation-resistant film on the side surfaces of the columnar projections.
forming a second groove in the first groove by anisotropically etching the substrate using the first and second masks as etching-resistant masks; forming a diffusion layer serving as a storage node on the lower side surface of the columnar protrusion using the mask as a diffusion-resistant mask; forming a third mask on the side surface of the columnar protrusion including the second mask; A third layer is formed in the second groove by anisotropic etching using the mask No. 3 as an etching-resistant mask.
forming a groove and forming a diffusion layer for element isolation at the bottom of the third groove, and forming a capacitor on the lower side surface of the columnar protrusion with the third mask removed and the second mask remaining. forming an insulating film and embedding the capacitor electrode up to the second groove; covering the surface of the capacitor electrode with an insulating film; removing the second mask; and forming a gate insulating film on the upper side surface of the columnar protrusion; a step of forming a gate electrode through the first mask, and a step of covering a region other than the first mask with an insulating film made of a different material, and removing the first mask to expose the upper end surface of the columnar protrusion. A semiconductor memory device comprising the steps of: forming a diffusion layer to serve as a source or drain on the exposed upper end face, and arranging a bit line connected to the diffusion layer by depositing a conductor film and patterning it. manufacturing method. (6) A plurality of semiconductor columnar protrusions separated by grooves running vertically and horizontally on the substrate are arranged in a matrix, a MOS capacitor is formed on the lower side surface of each columnar protrusion, a MOSFET is formed on the upper side surface, and a MOSFET is formed on the upper end surface of each columnar protrusion. A method for manufacturing a semiconductor memory device in which a source or drain diffusion layer of each MOSFET is formed and a bit line is connected to the diffusion layer, the method comprising: forming a first mask including an oxidation-resistant film on a semiconductor substrate; a step of forming first grooves running vertically and horizontally in the substrate by anisotropic etching to form a plurality of semiconductor columnar projections in an array; and a second step of forming an oxidation-resistant film on the side surfaces of the columnar projections.
forming a second groove in the first groove by anisotropically etching the substrate using the first and second masks as etching-resistant masks; forming a diffusion layer to serve as a storage node on the lower side surface of the columnar protrusion using the mask as a diffusion-resistant mask; forming an element isolation layer on the bottom of the second groove;
forming a capacitor insulating film on the lower side surface of the columnar projection and embedding a capacitor electrode in the second groove; covering the surface of the capacitor electrode with a first insulating film; and removing the second mask. a step of forming a gate electrode on the upper side surface of the columnar projection via a gate insulating film; a step of covering and planarizing the entire surface of the substrate on which the gate electrode is formed with a second insulating film; Etching the insulating film to expose the first mask, removing it by selective etching to expose the upper end surface of the columnar protrusion, and forming a diffusion layer to serve as a source or drain on the exposed upper end surface. A method of manufacturing a semiconductor memory device, comprising the steps of: depositing a conductive film and patterning to provide a bit line connected to the diffusion layer.