JPS63150A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the area of a memory cell by forming a channel region in a transistor for transfer and a capacitor for memory to one side wall of an island region and shaping two memory cells in one island region. CONSTITUTION:Word lines 21 and bit lines 22 mutually crossed at right angles and formed to a latticed shape are formed, and a plurality of unit memories 101,102 ... are each shaped among pairs of the word lines 21. The respective unit memory cell is constituted of transistors for transfer formed on one side surfaces in grooves shaped to a semiconductor substrate and capacitors communicated with the transistors for transfer and formed on the same side surfaces in the same grooves. The semiconductor substrate such as a P-type one 23 is used, and a plurality of the grooves 24 are each shaped in parallel through reactive ion etching (RIE), etc. to the substrate 23. Accordingly, areas occupied by the memory cells are reduced, thus allowing the increase of density.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device forming an MO8 type dynamic RAM, and particularly relates to a semiconductor memory device in which a storage capacitor is formed on the ll1ll wall of a groove in a semiconductor substrate. The present invention relates to a semiconductor memory device.

(Prior Art) For example, a memory cell of a conventional dynamic RAM is composed of a capacitor that stores information by accumulating charge, and a transfer transistor that exchanges the charge with an external circuit.

Such a dynamic RAM has a structure as shown in FIG. 6, for example.

In FIG. 6, the storage capacitor is connected to the semiconductor substrate 11.
An impurity layer 14 having a conductivity type opposite to that of the substrate 11 is formed on the surface of the substrate 11, and an electrode 13 is disposed on the substrate 11 to face the substrate 11 with an insulating film 12 interposed therebetween. Further, the transfer transistor includes a gate electrode 16 disposed oppositely on the substrate 11 via an insulator 115, a high concentration impurity tI4. The region 17 is composed of an impurity layer 14 which is also roughly one electrode of the capacitor.

The source of the charge that can be stored in the storage capacitor is the insulation W! of the capacitor section. Thickness of A12, electrode 13 and impurity layer 14
In order to increase the amount of accumulated charge, the insulation l112 must be made thinner or the facing area must be increased. However, since there is a limit to the amount of insulation 1112 that can be saved, a larger capacitor area is required, which has been a major obstacle in increasing the integration of memory cells.

Therefore, as a means of highly integrating dynamic R and AM by reducing the area occupied by the capacitor without reducing the capacitance of the capacitor, for example,
It has been proposed to form a trench in semiconductor II and form a capacitor therein, as described in Japanese Patent Laid-Open No. 58-149989.

However, even when a capacitor is formed in a groove in this manner, a space for forming a transfer transistor and a space for alignment thereof are required, which is a major obstacle to high integration.

(Problems to be solved by the invention) This invention was made in view of the above points, and it improves the problem of the space of transfer transistors, which was an obstacle to high integration, and reduces the space occupied by memory cells. An object of the present invention is to provide a semiconductor memory device that can be manufactured more easily and at a better yield by reducing the area and thus increasing the density, and by using self-alignment of the capacitor electrode and the gate electrode of the transfer transistor. It is something.

[Structure of the Invention] (Means and Effects for Solving the Problems) That is, in the semiconductor memory device according to the present invention, a trench in which an insulator is buried and a trench having a step in an opening are formed in a semiconductor substrate. A plurality of island regions are formed in an array by digging, and a channel region of a transfer transistor and a storage capacitor are formed on one side wall of the island region, so that two memory cells are formed in one island region. It is. In the semiconductor memory device configured in this manner, the area of the memory cell can be effectively reduced by forming the channel region of the transistor on the sidewall of the trench.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a planar pattern state of a semiconductor memory device, in which word lines 21 and bit lines 22 are formed orthogonally to each other in a lattice shape, each forming a -pair of word lines 21 and bit lines 22. A plurality of unit memory cells 101 and 102 between 121
, ... are being formed. Each unit memory cell is constituted by a transfer transistor formed on one side of a trench formed in the semiconductor substrate and a capacitor connected thereto and formed on the same side in the same trench. The semiconductor substrate is, for example, a P-type semiconductor substrate 23, and as shown in FIG. 2, this substrate 23 is etched with a plurality of layers by reactive ion etching (RIE) or the like. 1124 are formed in parallel. Further, this groove 24 is formed to be located between and parallel to the bit lines 22. Then, an impurity $25 for preventing field reversal is formed at the bottom of this groove 24,
Further, an insulating layer 26 is buried inside this groove 24 .

Further, as shown in FIG. 3, a groove 27 is formed in the substrate 23 in a direction perpendicular to the groove 24, and this groove 27 is formed to be shallower than the groove 24 described above. An opening step 27a that is wider than the groove 27 is formed at the opening of the groove 27. Further, an N-type impurity layer 28 is formed on the inner surface of the sidewall of the trench 27, and a conductive layer 30 made of, for example, polycrystalline silicon containing impurities is formed inside the trench 27.
is buried through the oxide film 29. Also, 1112
An impurity layer 31 for preventing field reversal is formed at the bottom of the trench 7, so that the impurity layers 28 formed on the 1llIl walls of the trench 27 are insulated from each other.

The word line 21 is formed of a conductive layer made of polycrystalline silicon containing impurities, for example, and is formed on the side wall of the opening step 27a with an oxide film 32 interposed therebetween. An N-type impurity layer 33 is formed on the surface of the semiconductor substrate 23 divided into a plurality of island regions by the grooves 24 and 27. The pit line 22 is the semiconductor substrate 2
It is formed on an insulating layer 34 deposited over the entire surface of the substrate 3, and is in contact with the N-type impurity 123 through a contact hole.

Next, a manufacturing process of a semiconductor memory device having such a structure will be explained. First, as shown in FIG. 4, RI is applied to the semiconductor substrate 23.
After forming the groove 24 using E, an impurity layer 25 for preventing field inversion is formed at least at the bottom of the groove 24. Then, an insulating layer 26 is formed by embedding a bond inside this 21i24.

Next, as shown in FIG. 5A, a film such as an oxide film 41 having an etching ratio with respect to the substrate 23 is etched on the semiconductor substrate 23.
Then, a film such as polycrystalline silicon @42 having an etching ratio with that of the insulating layer 26 buried inside the trench 24 and a film such as oxide M43 having an etching ratio with that of the substrate 23 are sequentially deposited. And these deposited layers 41,42o and 4
3 is etched by RIE to form a groove pattern in a direction perpendicular to 11i24.

Next, as shown in FIG. 5(B), using these deposited 1i 141.42 and 43 as a mask, the substrate 23 is
is etched to a predetermined depth. The depth of the opening step 27a formed by this etching becomes the channel length of the transfer transistor to be formed later. Further, it is necessary to determine the thickness of the oxide film 43 in advance so that the oxide film 43 is not etched away when forming the opening step 27a. Since there is an etching ratio between the semiconductor substrate 23 and the insulating layer 26 buried inside the previously formed l1I24, the surface of the semiconductor substrate 23 at the intersection of the opening step 27a and the groove 24 is insulated [ 126 remain. The remaining insulation 11126 is then etched to the same depth as the opening step 27a. Next, a film having an etching ratio with respect to the substrate 23, such as an oxide film 44, is deposited only on the side wall of the opening step 27a, and using the oxide film 44 and the oxide film 41 as a mask, a groove 21 having a width narrower than that of the opening step 27a is formed. . The width of this groove 27 is controlled by the thickness of the oxide film 44 in the lateral direction. At the bottom of this groove 27, there is a hole [!] for preventing field reversal. 1 layer 31,
N-type impurity j on the side wall of groove 21! 928 respectively. Next, as already explained in FIG.
A polycrystalline silicon layer 30 containing impurities is buried inside through oxide 129. Next, after removing the oxide 1144 and forming oxide R32 on the opening step 27a, a polycrystalline silicon layer containing impurities is formed along the opening step 27a to form a word layer that will become the gate electrode of the transfer transistor. [Form 121. Then, N is applied to the surface of the island region on the semiconductor substrate 23 partitioned by 1I24 and 27.
Type impurity 1llI33 is formed, and insulation 1i34 is formed on the entire surface.
By forming the bit line 22 so as to contact this impurity layer 33 through a contact hole after forming the semiconductor memory shown in FIGS.
can be manufactured.

[Effects of the Invention] As described above, according to the present invention, each island fJ formed in an array by the first and second grooves provided in the semiconductor substrate
Transfer transistors and storage capacitors are formed on the sidewalls of the area. Therefore, the area occupied by the memory cells is reduced and higher density is possible, and the gate electrode of the transfer transistor is formed in the wide opening step, and the capacitor electrode is formed inside the groove. Therefore, semiconductor memory devices can be manufactured with higher yield.

[Brief explanation of the drawing]

1 is a diagram showing a plane pattern for explaining a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the semiconductor memory device along the line The figure is a cross-sectional view showing the semiconductor memory device along the line m-m of the first factor, FIG. 4 is a diagram explaining the manufacturing process of the cross-section of the semiconductor memory device shown in FIG. ) to (C) are the third
The reason for explaining the manufacturing process of the cross section of the semiconductor memory device shown in the figure, and FIG. 6 is the reason for explaining the conventional semiconductor memory device. 21...Word line, 22...Bit line, 23...
Semiconductor substrate, 24, 27,... groove, 25, 31...
Impurity layer for preventing field inversion, 28.33... Impurity layer, 29.32... Oxide film, 30... Conductive layer. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 (s) Figure 5

Claims (1)

[Claims] A plurality of first electrodes formed in a semiconductor substrate and having an insulating material embedded therein.
a plurality of second grooves formed in the semiconductor substrate so as to be perpendicular to the first grooves and each having a wide opening step; A surface conductive layer formed on the surface of the island region on the semiconductor substrate and forming a connection hole for signal extraction of the memory cell, and a surface conductive layer formed on both side walls of the second groove on the substrate side. a capacitor electrode layer; another capacitor electrode buried inside the second groove with an insulating film interposed therebetween so as to face the electrode layer; and a capacitor electrode formed along the opening step of the second groove; A word line serving as a gate electrode of a transfer transistor is coupled to the electrode layer and the surface conductive layer, respectively, and a word line is wired perpendicularly to the word line and connected to the surface conductive layer of each island region. What is claimed is: 1. A semiconductor memory device comprising a plurality of bit lines.