JP2805702B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory D-RAM having a switching transistor and a capacitor for storing information. According to the present invention, in a semiconductor memory device, particularly a D-RAM, a memory capacitor is formed on each lower side wall of a plurality of columnar protrusions formed on a semiconductor substrate, and a switching transistor is formed on an upper portion of the columnar protrusion. Memory cells are arranged in a row and a column direction orthogonal to each other in a close-packed arrangement, and a word line is derived for a cell arranged in the diagonal direction with the shortest distance. To enable the configuration of a dead bit line (Folded Bit Line). 2. Description of the Related Art A D-RAM device is disclosed in, for example, Japanese Patent Publication No. 60-19596 and Japanese Patent Publication No. 60-19597. This D-RAM device, in particular, a D-RAM device having a so-called folded bit line configuration, has a pair of bit lines B that run parallel in a predetermined direction as shown in FIG. And the bit lines B
And a memory cell M comprising a transistor Q and a memory capacitor C for information between adjacent different word lines W arranged so as to extend in a direction intersecting these.
Is connected. D indicates a dummy cell, AP indicates an active pull-up circuit, PC indicates a precharge circuit, and CO indicates a column output circuit. In order to increase the degree of integration of the memory cell M in such a D-RAM, a memory capacitor C formed together with a switching transistor Q of an insulated gate field effect transistor (MIS-Tr) as shown in FIG. An arrangement configured as a capacitor has been proposed. This trench capacitor type D-RAM is provided on a main surface of a semiconductor substrate (1) while maintaining a desired interval as desired.
A switching transistor Q in which a drain region (2) and a drain / source region (3) are selectively formed, and a gate electrode (5) made of, for example, polysilicon is formed between the two via a gate insulating film (4). MIS-Tr as are formed, which groove (6) on the main surface of the semiconductor substrate (1) adjacent to the formed, the groove (6) of the inner peripheral surface, for example, SiO ₂
An insulating film (dielectric film) (7) made of an oxide film is formed thereon, and a capacitor electrode (8) made of, for example, a low-resistance or impurity-doped polycrystalline silicon layer is formed in a groove (6) thereon. Is applied, and a capacitor having an MIS structure with an inversion layer is formed mainly in the groove (6) of the substrate (1). (9) is an insulating film such as SiO ₂ formed by thermal oxidation on the surface of the capacitor electrode (8) and on the drain / source region (3).
Reference numeral 1) denotes a metal electrode or a wiring layer derived from terminals from the source / drain region (2) and the capacitor electrode (8). In such a trench capacitor type D-RAM,
The capacitor has a trench-type configuration, which can form a large capacity in a small occupied area, and thus has the advantage of promoting high integration (see Japanese Patent Publication No. 59-48547). Further, Japanese Patent Application Laid-Open No. 60-23506 discloses an invention in a trench capacitor type D-RAM in which the material of the capacitor insulating film and that of the gate insulating film are made different to further improve the integration density. . [Problems to be Solved by the Invention] According to the above-described trench capacitor type D-RAM, it is possible to form a large-capacity portion in a small occupied area and improve the high integration density. Even with this configuration, a sufficiently high integration density cannot be achieved by adopting a configuration in which the switching transistor Q (MIS-Tr) and the capacitor C are arranged side by side. In the present invention, each memory cell is formed in a columnar projection formed on a semiconductor substrate so as to reduce the occupied area of the memory cell, and despite this configuration, the folded bit line configuration is used to reduce the occupied area. Provided is a semiconductor memory device that can be formed without increasing the size. [Means for Solving the Problem] As described with reference to FIG. 3, the present invention has a plurality of pairs of bit lines B and In a D-RAM device in which a memory cell M including a capacitor C and a switching transistor Q is connected between every other word line,
FIG. 2 shows a layout pattern diagram, and FIG. 2-L shows a perspective view with a part of the cross section shown in FIG. 2 -L. , Columnar projections (22) are arranged and formed at the intersections of the respective rows X and columns Y. A capacitor C having an MIS structure in which a capacitor electrode (35) is attached to the lower side wall of each columnar projection (22) via an insulating film (dielectric film) (27) is formed.
A source / drain region (29) consisting of a region into which impurities are introduced is formed on the top, that is, on the top, and a gate electrode (32) is formed on the upper side wall of these columnar projections (22) via a gate insulating film (30). A switching transistor Q having a MIS transistor configuration is formed, and a memory cell M is formed for each columnar projection (22). And the impurity introduction region of these columnar projections (22),
In other words, the source / drain region (29) is connected to the bit line B and the folded bit line. In particular, the columnar projections (22) which obliquely intersect the directions of the rows X and columns Y and are adjacent to each other at the shortest distance. ) Common bit line B
And to That is, when the interval between each row X and the interval between each column Y are the same, 45 °
A common conductive layer (34) of Al or the like extended in this direction with respect to the columnar protrusions (22) arranged on a straight line intersecting with
Next, the respective regions (29) are in ohmic contact with each other, and the adjacent pair of conductive layers (34) is referred to as a bit line B. By connecting these conductive layers (34), that is, the gate electrodes (32) of the memory cells M related to the columnar projections (22) arranged on a line substantially perpendicular to the extending direction of the bit lines B and the bit lines B, respectively, they are connected to each other. Is derived. [Operation] As described above, according to the present invention, the switching transistor Q and the capacitor C are arranged in the height direction of the columnar protrusion (22), that is, in the thickness direction of the semiconductor substrate (21). The area occupied by the substrate (21) on the plate surface can be reduced, and the columnar projections (22) are arranged at the intersections of the rows X and the columns Y, that is, in a so-called close-packed manner. The size and density of the device can be increased. In addition, the bit line B and the derivation of the columnar projections (22), that is, the memory cells M located on the oblique line with respect to each memory cell M despite the arrangement in the vertical and horizontal directions, that is, the row and column directions, are derived. Therefore, if the word line W is derived for the memory cells M located on a line perpendicular to these lines, a plurality of pairs of the bit lines B and Are connected to different word lines W adjacent to each other, so that the bit lines B and the word lines W are arranged in a linear pattern as shown in FIG. The folded bit line configuration described in the figure can be used. By the way, as shown in FIG. 5, when each memory cell M, that is, the columnar protrusion (22) is arranged on the intersection of each row X and each column Y having a predetermined interval, the folded bit In a line configuration, for example, when deriving the word line W for the memory cells M on a common column, it is necessary to connect adjacent memory cells on the common column to respective ones of the pair of bit lines B and Needs to be a zigzag pattern that wraps around these bit lines B and so as to avoid every other cell M on each row. In this case, the bit lines B and In addition, it is necessary to increase the cell interval on the same column. For this reason, the columnar projections (22) constituting the memory cells M need to be formed in a rectangular pattern. , More slender This leads to problems with accuracy and reliability. Also, as shown in FIG. 6, each memory cell M, that is, the columnar protrusion (22) is formed so that each bit line B and each word line W can be formed linearly.
It is conceivable that the staggered arrangement is used, but in this case, since the arrangement of the columnar projections (22) cannot take the close-packed arrangement, it is not possible to reduce the size and increase the density. Therefore,
In the case of a memory device having such columnar projections (22), a so-called open bit line configuration is adopted regardless of the folded bit line configuration, which causes a problem of noise. However, in the present invention, the columnar projections (22) can be arranged in a close-packed arrangement, and a folded bit line configuration can be adopted. [Example] An example of a memory device according to the present invention will be described. First, as shown in FIG. 2A, for example, a p-type silicon semiconductor substrate (21) is prepared, and a mask layer (25) of, for example, SiO ₂ is entirely formed on one main surface by surface thermal oxidation or the like. Then, the substrate (21) is selectively patterned together with the mask layer (25) by chemical etching, dry etching, or the like to form a plurality of, for example, square island-shaped mask layers (25) and the mask layer (25). ) Below, columnar projections (22) are formed at the intersections of a plurality of columns Y and rows X, and valleys (23) are formed between these projections (22). Then, for example, an impurity of the same conductivity type as that of the substrate (21) is ion-implanted using the mask layer (25) as a mask to form a channel stop region (24B) having a relatively low impurity concentration at the bottom of the valley (23). As shown in FIG. 2B, for example, SiO ₂ is entirely deposited by a chemical vapor deposition method (CVD method) with a required thickness t including the peripheral side wall surface of each columnar projection (22). Then, a mask layer (26) is formed. As shown in FIG. 2C, sidewall etching is performed on the mask layer (26). That is, the mask layer (26) is anisotropically etched, for example, by reactive ion etching RIE, to perform etching corresponding to its thickness t, and to form a mask layer having a thickness t at the bottom center of the valley (23). (26) is removed, a window (26a) is formed here, and etching is stopped in a state where the window (26a) is formed. The side wall (26b) of the mask layer (26) is formed on the peripheral side wall surface of (2). Next, a p-type impurity is ion-implanted using the sidewall (26b) as a mask to selectively form a channel stop region (24A) having a high impurity concentration under the window (26a).
In this manner, the channel stop region (24A) having a high impurity concentration remains without forming the channel stop region (24A) having a high impurity concentration outside the region (24A), that is, at the base-side peripheral portion of the protrusion (22). ) Is formed. Next, as shown in FIG. 2D, the mask layers (26) and (2
5) is removed by etching. As shown in FIG. 2-E, the surface of the substrate (21) including the top peripheral wall surface of the projection (22) and the bottom surface of the valley (23) has a thickness of, for example, 100 mm or more by thermal oxidation or the like. A capacitor insulating film (27) made of a SiO ₂ oxide film is formed. As shown in FIG. 2F, a valley (23) is formed on the substrate (21).
Low resistivity first doped with impurities to bury
CVD of a polycrystalline semiconductor layer such as a polycrystalline silicon layer (28)
It is formed by a method or the like. As shown in FIG. 2-G, the first polycrystalline semiconductor layer (2
8) is etched from its surface by isotropic etching, for example, chemical etching or isotropic RIE, and the first polycrystalline semiconductor layer (28) is formed to a required thickness from the bottom in the valley (23). The polycrystalline semiconductor layer (28) on the top surface of the columnar protrusion (22) and the peripheral side wall portion on the top surface is removed by etching. Further, the first polycrystalline semiconductor layer (28)
The n-type impurity of a conductivity type different from that of the substrate (21) is ion-implanted into the top surface of each of the columnar protrusions (22) from which the impurity has been removed, thereby selectively introducing the impurity introduced region, that is, the source / drain region (29). Form. Next, as shown in FIG. 2H, using the polycrystalline semiconductor layer (28) as a mask, the top surface of the projection (22) on which the polycrystalline semiconductor layer (28) is not formed and the periphery of the top surface. The capacitor insulating film (27) on the surface is removed by etching. Next, as shown in FIG. 2-I, the capacitor insulating film (27)
Is thermally oxidized on the top surface, the peripheral side wall surface, and the surface of the polycrystalline semiconductor layer (28) of the projection (22) exposed to the outside by removing SiO _2.
An insulating film (40) made of an oxide film or the like is formed. As shown in FIG. 2J, a second polycrystalline semiconductor layer, for example, a polycrystalline silicon layer (31) doped with impurities and having a low resistivity is deposited on the insulating film (40) by a CVD method or the like. Form. As shown in FIG. 2K, the second polycrystalline semiconductor layer (31) is subjected to side wall etching and selective etching by photolithography to form a row X adjacent to each other and a column Y adjacent to each other. A plurality of strips having a stripe-like diagonal pattern that wraps the peripheral side surfaces of the projections (22) arranged at the shortest positions in common and forms a wiring portion formed so as to lie along a plane between these projections (22). Then, a gate electrode (32) to be a word line W composed of a part of the second polycrystalline semiconductor layer (31) is formed. The surface of the gate electrode (32), ie, the surface of the word line W is oxidized by thermal oxidation or the like to form an interlayer insulating film (33), and the insulating film (40) is etched on the region (29) of the protrusion (22). The electrode window (40a) is bored. afterwards,
With respect to the projections (22) adjacent to each other in the diagonal direction opposite to the diagonal direction to which the common gate electrode (32) is connected for each columnar projection (22), a common band-shaped conductive layer (34), that is, a bit line B , Is formed. These conductive layers (34)
For example, Al metal is first vapor-deposited on the entire surface, and then formed into a required pattern through a photolithography process. With this configuration, a capacitor made of the first polycrystalline semiconductor layer (28) is provided on a part of the bottom of the valley (23) of the peripheral wall surface of each projection (22) via the capacitor insulating film (27). An electrode (35) is formed and a capacitor C having a so-called MIS structure is formed.
Formed between the capacitor C and the source / drain region (29) formed on the top of each protrusion (22) from the top surface of the protrusion (22) to the peripheral wall surface. A switching transistor Q of a MIS-Tr comprising a part of an insulating film (40), that is, a gate electrode (32) formed via a gate insulating film (30), and a memory having a folded bit line structure A device is obtained. [Effects of the Invention] As described above, according to the memory device of the present invention, the MIS-Tr as the switching transistor Q is formed on the top surface of the columnar projection (22), and the MIS-Tr for the information memory is formed on the bottom side of the surrounding valley. By forming the capacitor C, the total occupied area is reduced and the density is increased, and accordingly, a memory device in which the irradiation probability of α rays is reduced can be configured.
By arranging the memory cells M, that is, the columnar projections (22) at the intersections of the rows X and the columns Y, that is, so-called close-packing, the size and density of the entire device can be increased. In addition, the bit line B and the derivation of the columnar projections (22), that is, the memory cells M located on the oblique line with respect to each memory cell M despite the arrangement in the vertical and horizontal directions, that is, the row and column directions, are derived. If word lines W are derived for memory cells M located on a line orthogonal to these lines, a plurality of pairs of bit lines B and a plurality of memory cells M arranged on a common row X, for example, are obtained. Are connected to different word lines W adjacent to each other, so that the bit lines B and the word lines W are arranged in a linear pattern, respectively. The smaller size and higher density can be achieved by adopting the bit line configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an arrangement pattern diagram of an example of the apparatus of the present invention, FIG.
A to L are enlarged schematic perspective views each showing a part of a main part in each step of an example of a method of manufacturing the device of the present invention, FIG. 3 is a circuit diagram of a D-RAM device, and FIG. FIG. 5 is a schematic sectional view of a trench capacitor type D-RAM cell, and FIGS. 5 and 6 are pattern diagrams of a comparative example. (21) is a semiconductor substrate, (22) is a columnar projection, (23) is a valley, (24) is a channel stop region, (29) is a source / drain region, (32) is a gate electrode, and W is a word line. ,
(34) is a conductive layer or bit line, (30) is a gate insulating film, (27) is a capacitor insulating film, and (35) is a capacitor electrode.

Claims (1)

(57) [Claims] In a semiconductor memory device having a plurality of pairs of bit lines folded in a predetermined direction and running in parallel, a capacitor and a memory cell including a switching transistor are connected between these bit lines and every other word line. A plurality of columnar projections arranged at regular intervals in a row direction and a column direction substantially orthogonal to each other; a capacitor electrode formed on a lower side wall of the columnar projection via an insulating film; and an upper portion of the columnar projection A gate electrode of a switching transistor formed on a side wall around the entire columnar projection with an insulating film interposed therebetween; and the switching transistor of the plurality of columnar projections located at the shortest distance from each other in the row direction and the column direction. A word line connecting the gate electrodes of the first and second rows, and the row direction and the column direction are shortest to each other in an oblique direction. A bit line formed over an upper end of the plurality of columnar projections; and an impurity introduction region formed at an upper end of the plurality of columnar projections over which the bit line extends. A line is connected to the impurity introduction region formed at an upper end of the plurality of columnar protrusions over which the bit line extends. The bit line and the word line are connected to the plurality of columnar protrusions. A semiconductor memory device characterized by intersecting with each other via an insulating film in a direction oblique to the row and column directions.