JPH03225955A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase a charge-storage electrode area, to reduce a cell area and to reduce a chip area by a method wherein a storage electrode is formed to be a hexagon which has a side parallel to a word line and a storage contact is shifted nearly to the bitline direction from the center of the hexagon. CONSTITUTION:A storage electrode 22 is formed to be a hexagon which has a side 22a parallel to the direction of a word line WL; a storage contact 11 is shifted to the direction of a bit line BL from the center of the hexagon. When the storage contact is shifted nearly to the direction of the bit line from the center of the hexagon, both requests to make a cell area smallest and to increase a storage electrode area are satisfied. That is to say, when the storage contact is shifted, the storage electrode area can be increased without increasing the cell area.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, in a DRAM having a folded bit line structure and a capacitor having a hexagonal area, the storage electrode can be increased without increasing the chip area. , with the aim of finding an advantageous layout unique to hexagonal storage electrodes, having folded bit lines, sharing bit line contacts for 2 bits, and having storage electrodes connected to selection transistors via storage contacts. In a semiconductor device consisting of a DRAM, the storage electrode has a hexagonal shape with sides parallel to word lines, and the storage contact is offset from the center of the hexagon approximately in the bit line direction.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a semiconductor device having a large storage electrode area in a storage cell portion of a DRAM having a so-called folded bit line structure.

1 of the currently mainstream 1-transistor, 1-capacitor, 8-inch DRAM
FIG. 15 shows an equivalent circuit for bits.

In the figure, BL is a bit line, WL is a word line, 5 is a source or drain, 7 is a contact between the bit line BL and the source or drain, 11 is a storage contact, 16
2 is a common electrode which is one electrode of the capacitor 20, 21 is a transistor, and 22 is a storage electrode.

As storage capacity increases, DRAM memory cells are required to have a structure with a small cell area (plane area per bit) and a large capacity that can store enough charge for memory retention and readout. As a typical structure, a so-called fin structure is known, which is a modification of the so-called stacked capacitor, in which the back surface of the stacked charge storage electrodes is also used as the capacitor surface. FIG. 16 shows an example of the layout of a memory cell in the case of a memory cell having a fin structure in which a capacitor is formed on a word line and a bit line.

In the figure, a hatched region 13 indicates the spread of a charge storage region having a fin structure, a dotted line indicates a cell region for one bit, and 11 indicates a contact hole through which the storage electrode contacts the semiconductor substrate.

In a DRAM having a folded bit line structure, as shown in FIG. 17, data is transferred to a capacitor 22 via a contact connected to a bit line (BL) 8,
One of the transistors 21 connected to L) 4 was opened, the bit line (BL) 8 connected to the other was set as a reference signal side, and the charge was amplified by a sense amplifier (S/A). Looking at each unit cell, it has a structure in which two word lines and one bit line run over the unit cell. therefore,
Since bit line contacts for two bits can be shared, the cell area can be reduced.

[Prior Art] A structure in which memory cells are arranged in a staggered manner in a MOS type dynamic capacitor is disclosed in, for example, Japanese Patent Laid-Open No. 63-10446.
It is publicly known from Publication No. 6. In FIG. 18, which is a drawing showing this arrangement structure, each reference number is 1: separation area, 2:
Capacitor region, 3a: electrode, 3b, 3c: diffusion layer, 3
Niswitching transistor, 5a, 5b: word line,
6a, 6b bit lines, 4: contact, 10: memory cell.

According to the explanation in this publication, the memory cells 10 are arranged in a staggered pattern, and an isolation region l (indicated by hatching) is formed at the peripheral end of the memory cell so as to surround an inner capacitor region.
Furthermore, a switching transistor with a ring-shaped gate electrode 3a is provided in the capacitor region, and the boundary line between the isolation region 1 and the capacitor region is no longer parallel to the current flow in the channel region of the switching Tr. It is claimed that it is possible to prevent leakage current from occurring along the edges, and also to prevent fluctuations in threshold voltage due to seepage of the isolation impurity diffusion layer from the edges of the isolation region.

In this conventional example, the unit cell is composed of a ring-shaped gate having a bit line contact in the center and a capacitor region surrounding the ring-shaped gate, so that the shape of the unit cell is close to a circle. Furthermore, in the memory cells arranged in a staggered pattern as described above, it is natural that the area can be effectively utilized when the shape of the memory cells is made into a hexagonal shape as shown in FIG.

However, in conventional stacked capacitors, substantially rectangular unit cells are arranged in a lattice pattern, so it was thought that the substrate area could be used more effectively by arranging rectangular capacitors.

[Problems to be Solved by the Invention] The present invention focuses on the relationship between the minimum width according to lithography rules and the effective use of chip area, and devises the optimal shape and arrangement of storage electrodes.

First, we will explain the basic explanation of the minimum width of the Lingraphie law in Chapter 19.
Use the diagram as a reference. In the figure, 31 is a wiring, 32 is a contact window 33 between the lower substrate region and the wiring 31, which is opened after the wiring 31 is formed, and F is the minimum width of lithography. As shown in the figure, the gap between the two wiring lines 31 matches the minimum width of lithography. Where the wiring 31 contacts the contact window 32, the wiring 31 contacts the contact window 32.
It is necessary to provide a margin M1 so that the area is completely buried and the underlying substrate is not exposed. Further, since a wiring other than the wiring 31 enters the contact window 33, it is necessary to provide a margin Mo between the contact window 33 and the wiring 31. Hereinafter, when referring to specific values of Mo and M, M is used. The explanation will be given assuming that =0.6F, M, and =0.5F.

The present inventors compared the cell areas of hexagonal storage electrodes and conventional rectangular storage electrodes.

First, a method of calculating the area of the hexagonal capacitor region shown in FIG. 20 will be explained.

The dimensions in the figure are as follows.

F: Minimum width according to lithography rules (the hexagonal areas arranged in a staggered manner are separated from each other by a distance F in all parts) A: From the center of the hexagonal area to other adjacent hexagonal areas in the left and right direction Distance B to the center of the hexagonal area: Distance θ from the center of the hexagonal area to the vertical symmetry axis of another vertically adjacent hexagonal area; Angle 2ρ of the hypotenuse of the hexagon with respect to the vertical symmetry axis. 21 points on the two vertical symmetry axes (distance A from the horizontal symmetry axis)
/2) Length of the hexagonal area cut by the perpendicular line 201: Length of the hexagonal area cut by the left-right symmetry axis 2-2: Length of the vertical sides of the hexagonal area L+L+°
:Parallel line O point located at the center of the vertical symmetry axis: L+L+'
Intersection L2L2" line between the line and the perpendicular passing through the 21 points: Perpendicular of the hexagon hypotenuse passing through the 0 point A partial view of 1/4 of the hexagon is shown in FIG.

Let P2 be the point where the OL line intersects the hexagonal side. Also, OP to place the hexagonal apex on the left-right symmetry axis at P3.22 point.
Let P4 be the point where the perpendicular to l intersects the left-right symmetry axis.

ρ. = (B/2) -〇P.

From the relationship 1PtOLi = θ, OPz cos θ = F/2, so 2
42 o = B (F/cos θ) is obtained.

From the relationship Q + "Q o + PsP4 i PBP2P4 = θ, we obtain ℃, = 2° + (A/2) tan θ, and similarly, (3) (6) are obtained. Therefore, the hexagonal 1/2 of the area is 81
Then, 51=(β1 +β2)(A) is obtained.

As in Figure 20, the length unit in the left-right symmetrical direction is A, the length unit in the vertical symmetrical direction is B, and rectangular cells are arranged in a staggered manner (
If the cell area of 172 is 82, then S2= (B-F) (A-)
(9) Therefore, the area difference ratio β”(S+ −S2)
/ S2 is B −F cosθ
It is 2.

FIG. 23 shows the relationship between β and θ when β is expressed as a percentage and B=3.1F.

When θ=30°, β becomes maximum.

In the hexagonal capacitor layout shown in Figure 20,
The capacitors are arranged in a staggered pattern. Therefore, we devised a layout in which the storage contacts connected to the selection transistors are also arranged in a staggered manner, and calculated the area.

First, as a subject for comparing the areas of staggered capacitors, a layout in which active regions in which selection transistors are formed are sent diagonally in each direction of bit lines and word lines as shown in FIG. 24 was taken up. In Figure 24, word line (WL) 4
is indicated by a diagonal line upward to the right, and the bit line (BL) 8 is indicated by a downward diagonal line to the right. Storage contacts are shown in the figure with 01 bit line contacts marked with an x and a circle. (The same applies to the drawings described below).

The elements that can be accommodated in the bit line spacing B, their dimensions, and margins are as shown in Figure 25. From this, the bit line spacing is B.
=2(F+Mo). On the other hand, the elements that can be accommodated in the word line spacing and their dimensional margins are as shown in FIG. 26, and the word line spacing is A = f (F + Mo)
(11).

Therefore, the cell area S cell is S cell=
2AX B = 41 guns (F + M, )".

M from the previous assumption. = 0.6F, S cell = 17.7F2.

Next, the specific examples shown in FIGS. 27 and 28 will be discussed as a method of modifying the layout shown in FIG. 24 to arrange storage contacts in a staggered manner to arrange hexagonal storage electrodes. Note that word lines and bit lines are omitted in the figure. In FIG. 27, the elements constituting the unit cell indicated by B" and 2A° are shown in FIG. 29. From FIG. 27 to 2A'
= B', and from Fig. 29, B" = 4F + 2M. and S cell = 2A"XB"' = 27. O
Therefore, in the case of Figure 27, the cell area is approximately 53 mm due to the hexagonal shape of the capacitor.
%, and as a result, the chip area increases.

2 On the other hand, in the hexagonal capacitor of the arrangement example shown in Fig. 28, the area of the unit cell is 2A' x B' as in the case of Fig. 27.
become. The elements constituting this unit cell are shown in FIG. As is clear from the figure, B'=2(F + MO). On the other hand, as can be seen from Figure 31, A' = (22-(1/2)")"2 (F + Mo)
= 1.936(F + M,). Therefore, the cell area S cell is S c
ell=2A' x B' = 7.746(F + M
o) 2=19.8F2. Therefore, in the case of FIG. 28, by making the capacitor hexagonal, the cell area increases by about 12%.

Therefore, the area of the chip cannot be effectively utilized by simply forming the storage electrode into a hexagonal shape as shown in FIGS. 27 and 28. In other words, if a hexagonal storage electrode is used while adopting a layout that narrows the spacing between word lines and bit lines as much as possible, as shown in FIG. 23, β>O and the chip area can be used effectively. can.

Therefore, the present invention has a folded bit line structure,
The present invention aims to find an advantageous layout unique to hexagonal storage electrodes, which allows the storage electrodes to be enlarged without increasing the chip area, in a DRAM in which the capacitors have hexagonal regions.

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of the present invention. In the present invention, the storage electrode 22 is a hexagon with sides 22a parallel to the word line WL (4) direction, and the storage contact 11 is offset from the center of the hexagon in the bit line B L (8) direction. It is characterized by

By the way, the conventional folded bit line structure DRAM
In FIGS. 16 and 24, there are two axes of symmetry in the WL force direction, and the dimension between the axes of symmetry is equal to the word line pitch.

In the layout shown in Figure 16, twice the WL pitch as shown is 2xWL pitch = 4F + 3M.

So, WL pitch= 2F + (3/2)
Mo (12). Substituting M0 = 0.6F, WL pitch = 2.9F. Also, in the layout shown in Figure 24, from equation (11), WL pitch = J"■ (F + M,)
(11). Similarly M. By substituting =0.6F, we get
WL pitch= 1.6 flF 2.77F'
t'aro.

These WL pitches must be equal to the spacing A of the hexagonal symmetry axes.

On the other hand, in the case of the configuration of the present invention (Fig. 1), A = 2F +
M, + d (13) However, d is the deviation of the storage contact position, and if the word line pitch is reduced so that the cell area is minimized, then in the case of Fig. 16, d
>0, and in the case of FIG. 24, d=o.

For example, if M, = 0.3F, A<2.77F-(11
) Since the above condition is satisfied, it is possible to arrange a hexagonal storage electrode with a large area in a cell with a minimum area. In this way, a symmetrical hexagonal shape is possible depending on the values of the margins M0 and Ml.

However, when Ml = 0.5F is substituted into equation (13), Am3F+d (13°)
Since A due to (13°) is larger than either (11) or (12), A = WL pitch cannot be satisfied. In other words, the reason behind equations (11) and (12) is that the word line pitch is narrowed so that the cell area is minimized, but according to the configuration of the present invention, A is larger than the word line pitch. As a result, the requirement of minimizing the cell area cannot be met. However, this case can be solved by making the hexagonal storage electrode asymmetrical in the WL force direction, as shown in FIG.

In the layout of FIG. 2, there is one axis of symmetry in the bit line direction for one storage electrode, and there is no axis of symmetry in the word line direction.

Preferred conditions for increasing the area of the storage electrode in this layout will be described below.

In Fig. 3, we considered the conditions in which the area of the storage electrode is maximized with A, , Am satisfying A''AI+A2 and angles θ and ψ variable.Here, there are the following constraints: AI>A2 and ( 14) Under the formula, the dimensions of the hexagon shown in FIG. 3 change in relation to each other as shown in FIG.

In the figure, β is the increase rate of the storage electrode area compared to 82 in equation (9). When θ=20~10°, ((A,
-A2)/F = 1 to 2.2, β becomes maximum.

The present invention can be applied to a DRAM in which a storage electrode is formed after forming a bit line, as in Example 1 described later, and a DRAM in which a bit line is formed after forming a storage electrode. An example of a cross-sectional view of the latter DRAM is shown in FIG. In the figure, 30 is an SL, 31 is a channel stop oxide film, 32 is a field oxide film, 34 is an oxide film, 45 is a capacitor insulating film, and 49 is a cell plate. In the DRAM whose structure is shown in FIG. 7, it is necessary to make an opening (51) in the cell plate 49 for bit line contact. Further, as shown in FIG. 7, an auxiliary electrode 50 is formed to facilitate bit line contact. Conventionally,
The shapes of the cell plate opening in FIG. 6, the cell plate opening in FIG. 7, and the auxiliary electrode were determined as shown in FIGS. 8 and 9, respectively, and it was thought that this would maximize the capacitor area. However, the present inventor S found that by making the cell plate opening and the auxiliary electrode circular or a polygon larger than a hexagon, the area of the capacitor can be increased compared to the conventional one.

FIG. 10 shows a cell plate opening 51 and a storage electrode 22, which have a new layout compared to FIGS. 6 and 8 according to the present invention. When each of these components is designed to the minimum based on lithography regulations, 2A=5.8F B=3F C=1.8F fl =2A −C−F/2=3.5F. Note that the circle of the cell plate opening 51 is the same as that of the conventional square cell plate 5.
It is assumed that it is inscribed in 1゛. The area of the storage electrode 22 is determined based on the relationship with each parameter shown in FIG. 4 and the necessary margin between the electrode 22 and the cell plate opening 51.

Considering these margins, the following formula: % formula %) (15) (16) ) (17) (18) In the above formula, Mo, M, are converted to F based on the above assumptions, and A, B, C , β are converted to F as described above, and W2. The six unknowns are Wl, ψ, θ, x, and Wo. Since these have the constraint conditions of four equations (15) to (18), two degrees of freedom remain. Therefore, for example, θ and ψ can be set to maximize the storage area.

The area S of the hexagonal storage electrode is 5=(WI+WO)X+(W2+wo)(ff
-x).

On the other hand, the area S'' of the conventional rectangular storage electrode is S''-
12 (B-F).

Substituting B=3F and l2=3.5F into S′, we get S′
=7F2 is obtained. For example, by setting ψ・22.6° and θ=30' and solving equations (15) to (18), we obtain Wo, 1.741F W, = 1.210F W2 = 0.5θIF X = 0.920F. , Substituting these into S gives S=8.499F2
becomes.

Therefore, β=(S-S')/S=0.214. This means that according to the present invention, the area of the storage electrode is 21.
This shows an increase of 4%. In other words, in the conventional rectangular cell plate opening, the area indicated by 52 (FIG. 10) is not utilized for the storage electrode 7. As shown in Example 1 below, when the conventional cell plate opening is left square and the asymmetric hexagonal capacitor of the present invention is applied, β===0.061, so the cell plate opening is changed to In the case of Figure 10, which is circular, add 15
% improvement can be achieved.

It is clear that the same effect can be obtained even if the cell plate opening has a hexagonal or larger polygon that circumscribes the circle.

In the layout of FIG. 9, the storage electrode area can be further increased by making the bit line contact auxiliary electrode 50 also circular or polygonal inscribed in the conventional square.

A specific example is shown in FIG. ψ, θ similar to Fig. 10
, 2A, B, C, β values: S=6.4F2. β=0
．． 104 is obtained. In this case, by making the cell plate opening and the auxiliary electrode circular, it is possible to increase the area of the storage capacitor electrode by about 4%.

The configuration of the present invention has been explained above based on mathematical formulas, but these formulas are the result of extremely precise logical development, and it is also possible to explain using simpler approximations. The effects of the present invention can be summarized by directly reading the area of the figure. Further, the present invention can be applied to any DRAM having a folded bit line structure. The example is as described above, but in addition to the above, it can also be applied to a known DRAM in which 2-bit storage contacts sharing a bit line contact are opposite to each other across the bit line connected to the bit line contact. is also possible.

[Operation] The invention according to claim 1 satisfies both the requirements for minimizing the cell area and increasing the area of the storage electrode by shifting the storage contact from the center of the hexagon approximately in the direction of the bit line. That is, by the above-mentioned shift, it is possible to increase the cell area as shown in FIGS. 27 and 28 (and to increase the storage electrode area as shown in FIG. 23).

The invention according to claim 2 provides a parameter AI such that β>0 as shown in FIG. 4 by making the hexagonal storage electrode asymmetrical in the word line direction.

A2. Since θ and ψ can be selected and a large alignment margin (MO, M,) can be secured, the yield can be increased or the area of the storage electrode can be further increased.

According to the third aspect of the invention, the cell area can be reduced by sharing storage contacts for two bits.

The invention as set forth in claims 4 and 5 effectively utilizes the area between the cell plate opening and the storage electrode as the storage electrode. That is, in the inventions of claims 1 to 3, in which the storage electrode is hexagonal, the area of the storage electrode can be increased by specifying the shapes of the cell plate and the auxiliary electrode.

Hereinafter, the present invention will be explained in detail with reference to Examples.

[Example] Example 1 The DRAM with the layout shown in FIG.
asymmetric) incorporating hexagonal storage electrodes.

FIG. 12 shows a diagram in which the diagonal lines 3 of the word lines and bit lines in FIG. 24 are deleted and the storage electrodes 25 are hatched.

From formula (11), A] (F + MO) = 2.77F On the other hand, if d = 0 in formula (13), 2F + above A1
21L÷d=3F.

B=2(F+M,)=3.2F FIG. 13 shows the storage electrode 22, the storage contact 7, and the spacing B. In a triangular bed with B as the hypotenuse, D
Since there is a condition of ≧2 (F+M l ), θ≦cos-' [2(F + M+)/B ], so by substituting the values of Mo and IL, θ≦20.4°
becomes. In other words, if the conditions for minimizing the cell area are set to B and D, θ → 30° is desirable from Fig. 23, but θ
An upper limit value of ≦=20.4° (<30°) is determined.

If θ=20.4', A+"3.27F, A2
=2.27F and ψ=29.3° are obtained from Fig. 4, respectively, and then β = 0.056 from the same figure. At this time, the deviation of the storage contact from the center of the hexagon is 1.1F. Therefore, in this example, the area increased by 5.6%.

In this example, in the conventional manufacturing method, D
Manufacture RAM. (See Figure 5).

After forming a field oxide film 32, a channel stop diffusion layer 31, a word line 35 which also serves as a gate electrode of a selection transistor, and a source/drain diffusion layer 5 on a semiconductor substrate 30, a bit line contact hole 37 in an interlayer insulating film 34 is formed.
5iaN4 on top of which the bit line 8 was formed through
A film 39.5iC1+ film 40 is subsequently grown (FIG. 5(a)). Next, as shown in FIG. 5(b), a contact hole 41 passing through the 5in2 film 40.5isN+ film 39 and the interlayer insulating film 34 is opened, and then a polycrystalline silicon film 42 is grown. After etching the polycrystalline silicon 42 into the pattern of the storage electrode 22 (FIG. 2), the exposed SiO□ film 40 is removed with hydrofluoric acid to form a gap 44 under the storage electrode, and the polycrystalline silicon 42
into a fin shape (see Figure 5(c)). Note that 42' is an adjacent storage electrode. Then, a capacitor insulating film 45 and a common electrode film 46 are successively grown to complete the capacitor portion of the fin structure (see FIG. 5(d)).
.

Example 2 When the storage contacts were laid out in a direction opposite to that in Example 1 from the center of the hexagon in the bit line direction (see FIG. 14), Example 1
Similar results were obtained.

Note that other examples have already been mentioned in the section [Means for solving the problem]. Furthermore, all the patterns in the above description will be used in the actually manufactured semiconductor device.
Positional deviations may occur due to manufacturing variations, or deformations specific to the manufacturing method may occur.

Such deviations and modifications are well known and do not impose any limitations on the scope of the present invention.

[Effects of the Invention] As explained above, the following effects are achieved without any manufacturing problems.

Since the area of the charge storage electrode can be increased, the cell area can be reduced (and the chip area can be reduced. Alternatively, the side surface area can be reduced, allowing the thickness of the charge storage electrode to be reduced. This makes manufacturing easier.Also, the number of charge storage electrodes can be reduced.
Manufacturing process can be shortened. Alternatively, the capacitor insulating film can be made thicker, improving reliability. Alternatively, since the accumulated charge can be increased, various operating margins can be increased.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a drawing showing the shape of the storage electrode asymmetrical in the word line direction, Fig. 3 is a drawing showing the parameters determining the shape of the asymmetric hexagonal storage electrode, Fig. 4 is a graph showing the relationship of the parameters in FIG. 3, FIGS. 5(a) to (d) show the steps in Example 1,
(a) shows the film stacking process, (b) shows the storage contact hole forming process, (c) shows the SiO□ etching process, and (d) shows the common electrode forming process. 7 Figure 6 shows the claim. DRAM corresponding to one embodiment of the invention of item 4
A sectional view of FIG. 7 is a DRAM corresponding to an embodiment of the invention of claim 5.
8 is a diagram showing the shape of the storage electrode and plate opening of the DRAM of FIG. 6 in a conventional example, FIG. 9 is a diagram similar to FIG. 8 of the DRAM of FIG. 7, and FIG. FIG. 11 is a diagram similar to FIG. 9 for an embodiment of the invention of claim 5; FIG. 12 is a diagram of each DRAM element in embodiment 1; Figure 13 is a diagram for determining the angle θ of the sides of a hexagon, Figure 14 is a diagram similar to Figure 12 in Example 2, and Figure 15 is an equivalent circuit for 1 bit of DRAM. 8 FIG. 16 is a diagram showing a planar layout of a folded bit line DRAM, FIG. 17 is a diagram explaining an equivalent circuit of a folded bit line DRAM, and FIG. 18 is a diagram illustrating a known folded bit line structure DRAM. Figure 19 is a diagram showing the planar layout of the components; Figure 19 is an explanatory diagram of the minimum width and alignment margin of the Sogera-Fie law; Figure 20 is a diagram showing the layout and specifications of the hexagonal storage electrode; Figure 21 is Figure 20. FIG. 22 is a diagram showing the layout of a rectangular storage electrode. FIG. 23 is a graph showing the relationship between the angle θ between hexagonal sides and the area increase rate (β) of the storage electrode. FIG. 24 is a diagram showing the planar layout of a DRAM with a folded bit line structure. FIG. 25 is a diagram explaining the calculation of the bit line direction spacing (B) in FIG. 24. FIG. 26 is a diagram showing the word line spacing in FIG. 24. Figure 27 and Figure 28 are diagrams illustrating the layout in which hexagonal storage electrodes are incorporated into a modified version of Figure 24. Figure 29 is the bit line spacing in Figure 27. (Bo) A diagram explaining the calculation of the word line spacing (A'"), FIG. 30 is a diagram explaining the calculation of the bit line spacing in FIG. 28. FIG. 31 is a diagram explaining the calculation of the word line spacing in FIG. 28. BL-bit line, WL-word line, 5-source or drain, 7-contact between bit line BL and source, 2
1-Transistor, 16-Common electrode which is one electrode of capacitor 20, 20-Capacitor, 22-Storage electrode M(J')-'7 C Angle of hole horse-shaped a e) Bundle 'Nuzu Diagram 13 Fig. 15 Fig. 14 Fig. 1 is turned on and off, 7DRAM power plane monthly re-reading aft Fig. 16 Saitoriichi Temporary - LCD't Motosen City! ! 17 Figure b 6 Unmt is Koshishi': Ntofjd% LDRAM 1
7) 1st bar 1P diagram out 18th diagram series F slow "'...shoreline spacing 25th diagram L4, public, JP-A-3 225955 (18) ■2hX, 2 (F+MO)

Claims (1)

[Claims] 1. A DRAM having a folded bit line, sharing a bit line contact for two bits, and having a storage electrode connected to a selection transistor via a storage contact.
A semiconductor device characterized in that the storage electrode has a hexagonal shape with sides parallel to the word line, and the storage contact is offset from the center of the hexagon substantially in the bit line direction. . 2. the hexagon has an axis of symmetry parallel to the bit line direction;
2. The semiconductor device according to claim 1, having no axis of symmetry parallel to the word line direction. 3. The semiconductor device according to claim 1 or 2, wherein the two bit storage contacts sharing the bit line contact are opposite to each other across the bit line connected to the bit line contact. 4. Any one of claims 1 to 3, wherein the bit line extends above the storage electrode, and the cell plate has an opening in a circular or polygonal shape of hexagon or more at the bit line contact portion. 1. Semiconductor device described in Section 1. 5. The semiconductor device according to claim 4, wherein a bit line contact auxiliary electrode is interposed between the bit line and the semiconductor substrate, and the shape of the auxiliary electrode is a circle or a polygon of hexagon or more.