JPH01233792A - Method of forming conductive medium of thin film substrate - Google Patents
Method of forming conductive medium of thin film substrateInfo
- Publication number
- JPH01233792A JPH01233792A JP6014188A JP6014188A JPH01233792A JP H01233792 A JPH01233792 A JP H01233792A JP 6014188 A JP6014188 A JP 6014188A JP 6014188 A JP6014188 A JP 6014188A JP H01233792 A JPH01233792 A JP H01233792A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide
- conductive medium
- copper
- thin film
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 title claims abstract description 21
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 239000004642 Polyimide Substances 0.000 claims abstract description 27
- 229920001721 polyimide Polymers 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000009499 grossing Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052802 copper Inorganic materials 0.000 abstract description 16
- 239000010949 copper Substances 0.000 abstract description 16
- 238000007747 plating Methods 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 239000000919 ceramic Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
薄膜型のセラミック多Ｎ基板の導電媒体部形成方法に関
し、
薄膜の微細化を保ち、ＶＩＡ （導電媒体部）面の凹凸
を防いで信頼性を高めることを目的とし、基板上に導体
層を形成する工程と、その工程以前に導電媒体部を形成
する予定位置に導体でなるスタンドを予め形成する工程
と、それら導体層及び導電媒体部をポリイミドでコーテ
ィングする工程とポリイミド面の平滑化及びエツチング
により前記スタンドの面とポリイミドの面とをほぼ同一
面にする工程とを有するように構成する。[Detailed Description of the Invention] [Summary] Regarding a method for forming a conductive medium portion of a thin-film type ceramic multi-N substrate, the present invention relates to a method for forming a conductive medium portion of a thin-film type ceramic multi-N substrate, and to improve reliability by maintaining fineness of the thin film and preventing irregularities on the surface of the VIA (conductive medium portion). For the purpose of and a step of smoothing and etching the polyimide surface to make the surface of the stand and the polyimide surface substantially flush.
本発明は、薄膜型のセラミック多層基板の厚電媒体部形
成方法に関する。The present invention relates to a method for forming a thick electrical medium portion of a thin-film type ceramic multilayer substrate.
コンピュータの内部等で使用されるセラミック多層基板
には、厚膜型と薄膜型とがある。厚膜型はグリーンシー
トにペーストを印刷し、それらを積層して焼成したもの
で、基板の堅牢性に勝れているが、回路の微細化と処理
速度に不満が残り、里方、薄膜型はポリイミドを絶縁層
にして多層化を図ったもので、ポリイミドの誘電性が高
いことやプロセス上もスパッタ等で微細化が容易である
など高速化の面で優れている。、
汎用コンピュータの性能向上のためには、クロックサイ
クルの短縮が必要であり、この意味で、ＬＳＩ間の遅延
時間を最小にする高密度実装技術の重要性は増すばかり
である。その実現に有力な手段の１つとして、セラミッ
ク基板をベースにした実装方式があり、特に微細配線を
可能とする薄膜型の配線基板が注目されている。Ceramic multilayer substrates used inside computers and the like include thick-film types and thin-film types. The thick film type is made by printing paste on green sheets, stacking them and firing them, and the board has excellent robustness, but there are still dissatisfied with the miniaturization of the circuit and the processing speed. This is a multi-layer structure using polyimide as an insulating layer, and is superior in terms of speed because polyimide has high dielectric properties and can be easily miniaturized by sputtering or other processes. In order to improve the performance of general-purpose computers, it is necessary to shorten the clock cycle, and in this sense, the importance of high-density packaging technology that minimizes the delay time between LSIs is increasing. One promising means for realizing this is a mounting method based on ceramic substrates, and thin-film wiring boards that enable fine wiring are attracting particular attention.
薄膜基板の製造に際しては、基板の上下両面を電気的に
導通させる導電媒体部（以下、ＶＩＡと呼称する）の形
成が重要かつ微妙な課題を抱えている。When manufacturing thin film substrates, forming a conductive medium portion (hereinafter referred to as VIA) that electrically connects the upper and lower surfaces of the substrate is an important and delicate issue.
第２図は、従来のセラミック薄膜基板のＶＩＡ形成方法
の一例を示す工程図である。プロセスは、まず同図（ａ
）に示す如く、ベースセラミック基＃１ｉ２１にｔｒＩ
２２のスパッタメッキが行われ、次に図（ｂ）に示す如
（、所定部分２３ヘエツチングされたのち、図（ｃ）に
示す如く、全面にポリイミド２４がコーティングされる
。続いて図（ｄ）に示す如く、ポリイミド層２４の所定
部分２５ヘエツチングされる。このエツチングは、感光
性の方法でもよいし、ドライ又はウェットで化学的に行
ってもよい。特に、インピーダンスの整合などでポリイ
ミドの厚さを増したい場合には、−度に露光することが
不可能なため、ＩＯμ程度で２〜３回に分けたポリイミ
ドの塗布を行い、図（ｅ）に示す如く、更に銅２６のス
パッタコーティングを行い、図＜ｆ＞に示す如く、所定
部分２７へのエツチングを行って、これらを繰返すこと
により第３図に示す断面図の如き製品を得る。FIG. 2 is a process diagram showing an example of a conventional method for forming a VIA on a ceramic thin film substrate. The process begins in the same figure (a
), trI was added to the base ceramic group #1i21.
Then, as shown in Figure (b), a predetermined portion 23 is etched, and then the entire surface is coated with polyimide 24 as shown in Figure (c). As shown in FIG. 2, a predetermined portion 25 of the polyimide layer 24 is etched. This etching may be performed by a photosensitive method or by dry or wet chemical etching. In particular, the thickness of the polyimide is If you want to increase the amount of light, it is impossible to expose to light at -degrees, so apply polyimide in two or three times at about IOμ, and then apply sputter coating of copper 26 as shown in Figure (e). Then, as shown in Figure <f>, a predetermined portion 27 is etched, and by repeating these steps, a product as shown in the sectional view shown in Figure 3 is obtained.
しかしながら、上記従来の形成方法では、上下の配線を
接続するためのＶＩＡ部の表面に凹凸が形成される。特
に基板の特性インピーダンス整合の必要性からポリイミ
ドの厚さを厚くしたい場合には、ポリイミドのエツチン
グやスパッタによる銅の回り込みが不十分になり、ＶＩ
Ａ形成が困難になる。ＶＩＡの径寸法が各層同一では、
ずれた場合に電気的導通が得られなくなるので、第３図
に示す如く、１層目のポリイミド層３１におけるＶＩＡ
の直径ｄｉが例えば５０μであれば、２層目のポリイミ
ド層３２におけるＶＩＡの直径ｄ２は８０μであり、３
層目の直径は１００μであるという具合に大きくなり、
薄膜の利点である微細化は失われ、面の凹凸も激しくな
り、多層焼付けに限度を生じる。工程も増し、またＶＩ
Ａ部分の段差が大きくなって、ＶＩＡのコーナ部分の銅
に応力が集中し易く、クランク発生の恐れが大きくなる
。However, in the conventional forming method described above, irregularities are formed on the surface of the VIA section for connecting the upper and lower wirings. In particular, when it is desired to increase the thickness of polyimide due to the need for matching the characteristic impedance of the substrate, copper wrap-around due to etching or sputtering of the polyimide will be insufficient, and the VI
A becomes difficult to form. If the diameter of the VIA is the same for each layer,
If the VIA in the first polyimide layer 31 is misaligned, as shown in FIG.
For example, if the diameter di of the VIA is 50μ, the diameter d2 of the VIA in the second polyimide layer 32 is 80μ, and 3
The diameter of the layer increases to 100μ,
The advantage of thin film, which is miniaturization, is lost, and the surface becomes more uneven, putting a limit on multilayer printing. The number of processes has increased, and VI
The step difference in the A section becomes large, and stress tends to concentrate on the copper at the corner of the VIA, increasing the risk of crank occurrence.
本発明は、このような問題を解決して、薄膜の微細化を
保ち、ＶＩＡ面の凹凸を防いで偉績性を高めた薄膜基板
のＶＩＡ形成方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a method for forming a VIA on a thin film substrate, which maintains fineness of the thin film, prevents irregularities on the surface of the VIA, and improves performance.
本発明において、上記の課題を解決し、目的を達成する
ための手段は、積層された複数の導体層とそれら導体層
の層間を電気的に接続する導電媒体部とを備えて形成さ
れる薄膜基板の導電媒体部形成方法において、基板上に
導体層を形成する工程と、その工程以前に導電媒体部を
形成する予定位置に導体で成るスタットを予め形成する
工程と、それら導体層及び導電媒体部をポリイミドでコ
ーティングする工程と、ポリイミド面の平滑化及びエツ
チングにより前記スタットの面とポリイミドの面とをほ
ぼ同一面にする工程とを有する薄膜基板の導電媒体部形
成方法によるものとする。In the present invention, means for solving the above-mentioned problems and achieving the objects is a thin film formed of a plurality of laminated conductor layers and a conductive medium portion that electrically connects between the conductor layers. A method for forming a conductive medium portion of a substrate includes a step of forming a conductive layer on a substrate, a step of previously forming a stud made of a conductor at a planned position where a conductive medium portion is to be formed, and the conductive layer and the conductive medium. The present invention is based on a method for forming a conductive medium portion of a thin film substrate, which includes a step of coating the portion with polyimide, and a step of smoothing and etching the polyimide surface to make the surface of the stud and the polyimide surface substantially flush with each other.
ポリイミドの厚さを厚くしたい場合に、従来の方法は複
数回に分けてポリイミドをスピンコードし、′各層を別
々にスパッタしていたが、本発明では、下方の導体層を
形成する際に、次の導体層との電気的接続を得るＶＩＡ
部分を予めスタット状に形成しておくものである。When it is desired to increase the thickness of polyimide, the conventional method involves spin-coding the polyimide in multiple steps and sputtering each layer separately, but in the present invention, when forming the lower conductor layer, VIA to obtain electrical connection with the next conductor layer
The part is formed in advance into a stud shape.
以下、図面を参照して、本発明の実施例を詳細に説明す
る。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は、本発明の一実施例の工程図である。FIG. 1 is a process diagram of an embodiment of the present invention.
同図において、薄膜基板の形成は図０〜図■の順で行わ
れる。In the figure, the formation of the thin film substrate is performed in the order shown in FIGS.
■基板１上に銅２をスパッタメツキする。■Sputter plating copper 2 on substrate 1.
■パッド位置にエツチングレジストとしての機能を備え
たレジストメタル３を形成する。(2) A resist metal 3 having a function as an etching resist is formed at the pad position.
■スタットメツキ用に、メツキレジスト４を塗布する。■Apply plating resist 4 for stud plating.
■銅スタツド５を形成し、銅及びレジストメタル上にメ
ツキ６を行う（この部分がＶＩＡとなる。）。(2) Copper studs 5 are formed and plating 6 is performed on the copper and resist metal (this part becomes the VIA).
■銅２をエツチングする。■Etch copper 2.
■ポリイミド７をコートする。■Coat with polyimide 7.
■プレス等により、表面を平滑化する。■Smooth the surface using a press, etc.
■エツチングにより、ポリイミド７の面と銅スタンド５
の面がほぼ同一面上になるようにする。■By etching, the surface of polyimide 7 and the copper stand 5 are
so that the two sides are almost on the same plane.
このように、本実施例によれば、スタットの形で予めＶ
ＩＡが形成されているので、導体層毎にずれる恐れもな
く、またＶＩＡ頂面の形成は１回だけで、これに対応さ
せてポリイミドの平滑化を行うことができるので、凹凸
面の少ない高品質の基板を形成することができる。In this way, according to this embodiment, V is set in advance in the form of a stat.
Since the IA is formed, there is no risk of misalignment from one conductor layer to another, and the top surface of the VIA is formed only once, and the polyimide can be smoothed accordingly, making it possible to create a high surface with less uneven surfaces. A high quality substrate can be formed.
上記のプロセスは、あくまで本発明の一実施例であって
、これに限定されるものではない。The above process is just one example of the present invention, and is not limited thereto.
また、メタル形成は、各メタル間やポリイミドとの密着
強度を保証するため実際には複雑であるが、上記の説明
では概念のみを示しである。In addition, metal formation is actually complicated in order to ensure adhesion strength between each metal and with polyimide, but the above explanation only shows the concept.
以上、説明したとおり、本発明によれば、薄膜の微細化
を保ち、ＶＩＡ面の凹凸を防いで信頼性を高めた薄膜基
板のＶＩＡ形成方法を提供することができる。As described above, according to the present invention, it is possible to provide a method for forming a VIA on a thin film substrate, which maintains the miniaturization of the thin film, prevents irregularities on the VIA surface, and improves reliability.
第１図は本発明の一実施例の工程図、
第２図は従来例の工程図、
第３図は従来例の製品の断面図である。
１；基板、
２；銅、
３；レジストメタル、
４：メンキレジスト、
５；銅スタンド、
６；メツキ、
７；ポリイミド。
代理人 弁理士 井 桁 貞 −（代表者）（ａ）
（ｂ） （ｃ）
（ｄ） （ｅ）
（ｆ）健釆例の工程図
第２図
第３図FIG. 1 is a process diagram of an embodiment of the present invention, FIG. 2 is a process diagram of a conventional example, and FIG. 3 is a sectional view of a conventional product. 1: Substrate, 2: Copper, 3: Resist metal, 4: Copper resist, 5: Copper stand, 6: Plating, 7: Polyimide. Agent Patent Attorney Sada Igata - (Representative) (a)
(b) (c)
(d) (e)
(f) Process diagram of the example of a well-produced tank, Figure 2, Figure 3
Claims (1)
に接続する導電媒体部とを備えて形成される薄膜基板の
導電媒体部形成方法において、基板（１）上に導体層を
形成する工程と、 その工程以前に導電媒体部を形成する予定位置に導体で
成るスタット（５）を予め形成する工程と、 それら導体層及び導電媒体部をポリイミド（７）でコー
ティングする工程と、 ポリイミド（７）面の平滑化及びエッチングにより前記
スタット（５）の面とポリイミド（７）の面とをほぼ同
一面にする工程とを有することを特徴とする薄膜基板の
導電媒体部形成方法。[Scope of Claims] A method for forming a conductive medium portion of a thin film substrate comprising a plurality of laminated conductor layers and a conductive medium portion electrically connecting the conductive layers, the method comprising: a step of forming a conductive layer on the conductor layer, a step of previously forming a stud (5) made of a conductor at a planned position where a conductive medium portion is to be formed, and coating the conductive layer and the conductive medium portion with polyimide (7). and a step of smoothing and etching the surface of the polyimide (7) to make the surface of the stud (5) and the surface of the polyimide (7) substantially the same plane. Part formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6014188A JPH01233792A (en) | 1988-03-14 | 1988-03-14 | Method of forming conductive medium of thin film substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6014188A JPH01233792A (en) | 1988-03-14 | 1988-03-14 | Method of forming conductive medium of thin film substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01233792A true JPH01233792A (en) | 1989-09-19 |
Family
ID=13133567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6014188A Pending JPH01233792A (en) | 1988-03-14 | 1988-03-14 | Method of forming conductive medium of thin film substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01233792A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0360188A (en) * | 1989-07-27 | 1991-03-15 | Bull Sa | Method of forming multilayer wiring network of connection board with high density integrated circuit |
-
1988
- 1988-03-14 JP JP6014188A patent/JPH01233792A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0360188A (en) * | 1989-07-27 | 1991-03-15 | Bull Sa | Method of forming multilayer wiring network of connection board with high density integrated circuit |
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