JPH03196695A - Manufacture of multilayer thin film circuit substrate - Google Patents

Abstract

PURPOSE:To prevent a circuit formation layer from peeling off an insulating substrate by forming a conductor pattern and an insulator by a bias sputter method of a fixed voltage or below and by constituting a wiring layer having an expansion force balancing with a contraction force of an insulating layer. CONSTITUTION:After an insulating layer 2 is formed between a wiring layer 13 and an insulating substrate 1, an inner stress generates in a direction A and the layer 2 contracts. Therefore, if a conductor pattern 13-1 and an insulator 13-2 of the wiring layer 13 are formed by a bias sputter method applying a fixed negative voltage, an inner stress generates in the formed conductor pattern 13-1 and the insulator 13-2 in an expansion direction, and an expansion force generates in an opposite direction of contraction force of the insulating layer 2, that is, in a direction B and balances with a contraction force of the insulating layer 2 in each wiring layer 13. Thereby, inner stress between the insulating layer 2 and the wiring layer 13 balances, thereby preventing a circuit formation layer from peeling off an insulating substrate.

Description

[Detailed Description of the Invention] [Summary] Regarding the manufacturing method of multilayer thin film circuit boards widely used in the construction of various electronic devices, the internal stresses of the insulating layer and wiring layer of each layer are balanced and the circuit forming layer is insulated. A method for manufacturing a multilayer thin film circuit board in which an insulating layer of a constant thickness and a wiring layer having a conductive pattern are sequentially formed on the circuit forming surface of an insulating base, with the aim of providing a method for manufacturing a multilayer thin film circuit board that does not peel off from the base. Either the conductor pattern and the insulator are formed by a bias sputtering method at a constant voltage or lower to form the wiring layer having an expansion force balanced with the contraction force of the insulating layer, or the conductor pattern is formed by a plating method with a large expansion force. A wiring layer having an expansion force balanced with the contraction force of the insulating layer is formed.

r Industrial Application Field] The present invention relates to a method for manufacturing a multilayer thin film circuit board that is widely used in the construction of various electronic devices.

Recently, multilayer thin film circuit boards used in large computers and communication equipment are required to increase circuit size and speed.
Conductive patterns formed on insulating substrates are becoming finer and denser in each layer, and require multilayering. Therefore, an insulating layer of a constant thickness and a wiring layer forming a conductor pattern are successively formed and laminated on the pattern-forming surface side of the insulating substrate. However, since the polyimide resin used for the insulating layer has internal stress in the direction of contraction, the laminated thin film layers tend to shrink and peel off at the interface on each side end surface of the insulating substrate, and the insulating layer of each layer tends to shrink. There is a need for a new method for manufacturing multilayer thin film circuit boards in which the internal stress of the wiring layers is balanced and the thin film layers do not shrink.

[Prior Art] In the conventional method for manufacturing a multilayer thin film circuit board, as shown in the side cross-sectional view of FIG.
A first layer is formed by forming an insulating layer 2 made of polyimide resin with a thickness of ~40 μm, and providing a wiring layer 3 with a thickness of about 5 to 20 μm made of a conductive pattern 3-1 and an insulator 3-2 on the upper surface of the insulating layer 2. By sequentially overlapping the insulating layer 2 and the wiring layer 3, a multilayer thin film circuit layer is formed on the main surface side of the insulating substrate l.

[Problems to be Solved by the Invention] The problem with the conventional method of manufacturing a multilayer thin film circuit board described above is that the thin film circuit layer laminated on the circuit forming surface side of the insulating substrate 1 as shown in FIG. Each of the insulating layers 2 is made of polyimide resin and has internal stress in the direction of contraction of the polyimide resin, which acts in the direction of contraction of the laminated thin film circuit layer, that is, in the six directions of arrows, and causes the contraction. A problem arises in that the force causes peeling at the interface between the insulating layer 2 and the insulating base l at the end surface of the circuit board.

In view of the above-mentioned problems, the present invention aims to provide a method for manufacturing a multilayer thin film circuit board in which the internal stresses of the insulating layer and wiring layer of each layer are balanced and the circuit forming layer does not peel off from the insulating base.

(Means for Solving the Problems) As shown in FIG.
In the multilayer thin film circuit board in which 3 and 3 are sequentially formed, the 41-body pattern 13-1 and the insulator 13-2 are formed by bias sputtering at a constant voltage or less, so that an expansion force balanced with the contraction force of the insulating layer 2 is applied. Alternatively, the conductor pattern 13-1 is formed by a plating method with a large expansion force to form the wiring layer 13 having an expansion force balanced with the contraction force of the insulating layer 2. .

As shown in FIG. Balances the contractile force. Furthermore, even if only the conductor pattern 13-1 is formed using a plating method that generates an internal stress in the opposite direction to the internal stress of the insulating layer 2, each wiring layer 13 can be formed into a thin film circuit by balancing the contraction force of the insulating layer 2. Since the internal stress in the forming portion is reduced, the respective forces generated in the laminated insulating layer 2 and wiring layer 13 are canceled, making it possible to prevent separation from the insulating base.

[For production]

In the present invention, as shown in FIG. 1, each insulating layer 2 made of polyimide resin formed between each wiring layer 13 is
After formation, internal stress occurs in the direction of arrow A and shrinks, so the conductor pattern 131 and insulator 13-2 of the wiring layer 13 are formed by bias sputtering with a constant negative voltage applied as shown in FIG. Accordingly, the conductor pattern 13-1 and the insulator 13 formed [Example] The present invention will be described in detail below based on the example shown in the drawings.

FIG. 1 shows a side sectional view for explaining the present invention, and in the figure, the same members as in FIG. 3 are given the same symbols.

The method for manufacturing a multilayer thin film circuit board of the present invention includes an insulating substrate 10
As shown in FIG. 2, a constant negative voltage is applied to the upper surface of the insulating layer 2 made of polyimide resin with a thickness of approximately 10 to 40 μm, which is coated on the entire circuit forming surface side. A wiring layer 13 consisting of a conductive pattern 13-1 of approximately 5 to 20 μm and an insulator 13-2 having an expansion stress balanced with the contraction stress of As a result, a multilayer thin film circuit layer is formed on the main surface side of the insulating substrate l.

In addition, by adjusting plating conditions 1, such as liquid concentration, current density, plating temperature, additives, etc., and forming the conductor pattern 13-1 of the wiring layer by copper plating, the internal stress of the insulating layer 2 can be reduced. A wiring layer 13 is formed in which internal stress occurs in the opposite direction.

As a result, as shown in FIG. 1, the laminated insulating layer 2 and wiring layer 13 have internal stresses that are mutually balanced and cancel each other out, so that Since the stress is small, peeling of the thin film circuit forming portion from the insulating substrate 1 can be prevented.

[Effects of the Invention] As is clear from the above description, according to the present invention, the internal stress of the insulating layer and the wiring layer is balanced by an extremely simple manufacturing method, thereby reducing the internal stress of the thin film circuit forming part and improving insulation. It is possible to provide a method for manufacturing a multilayer thin film circuit board, which has advantages such as being able to prevent peeling from the base 1 and can be expected to significantly improve reliability.

[Brief explanation of drawings]

FIG. 1 is a side sectional view explaining the present invention in detail, FIG. 2 is a side sectional view explaining the operation, FIG. 3 is a side sectional view showing a multilayer thin film circuit board, and FIG. 4 is a side sectional view showing problems. be. In the figure, 1 is an insulating base, 2 is an insulating layer, 13 is a wiring layer, 13-1 is a conductive pattern, 13-2 is an insulator, -1 A A← Fig. 2 1) -T, 1'+'°J'l'T6 [Omiko Figure 4

Claims (2)

[Claims] (1) A method for manufacturing a multilayer thin film circuit board in which an insulating layer (2) of a constant thickness and a wiring layer (13) having a conductive pattern are sequentially formed on the circuit forming surface of the insulating substrate (1), comprising: -1) and the insulator (13-2) are formed by bias sputtering at a constant voltage or lower, and the wiring layer (13-2) has an expansion force balanced with the contraction force of the insulating layer (2).
13) A method for manufacturing a multilayer thin film circuit board, comprising: (2) The one-piece pattern (13-1) is formed by a plating method with a large expansion force to form a wiring layer (13) having an expansion force balanced with the contraction force of the insulating layer (2). A method for manufacturing a multilayer thin film circuit board according to item 1.