JPH01129488A - Circuit substrate and manufacture thereof - Google Patents
Circuit substrate and manufacture thereofInfo
- Publication number
- JPH01129488A JPH01129488A JP28811687A JP28811687A JPH01129488A JP H01129488 A JPH01129488 A JP H01129488A JP 28811687 A JP28811687 A JP 28811687A JP 28811687 A JP28811687 A JP 28811687A JP H01129488 A JPH01129488 A JP H01129488A
- Authority
- JP
- Japan
- Prior art keywords
- conductor film
- film
- substrate
- conductor
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims abstract description 46
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 238000004544 sputter deposition Methods 0.000 abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体素子等の回路素子を実装するための回
路基板に係り、特にその配線パターンの構造と製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a circuit board for mounting circuit elements such as semiconductor elements, and particularly to the structure and manufacturing method of its wiring pattern.
（従来の技術）
半導体素子等を実装する回路基板上の配線は、素子の小
型化に対応し、また実装密度の向上を図るために、微細
かつ高密度であることが要求されている。このため回路
基板の導体配線は、印刷法による厚膜から蒸着法やスパ
ッタ法による薄膜へと発展して来ている。一方ではまた
、回路基板自身の集積化が進められ、スルーホールを利
用した多層回路基板等が実用化されている。また最近で
は、回路基板の表面、裏面の他、側面にも導体膜を形成
する３次元的な実装法が数多く試みられている。基板の
側面に導体パターンを形成する場合のポイントは、表面
（または裏面）の導体パターンとのコンタクトを如何に
してとるか、という点にある。(Prior Art) Wiring on a circuit board on which semiconductor elements and the like are mounted is required to be fine and high-density in order to cope with the miniaturization of the elements and to improve the packaging density. For this reason, conductor wiring for circuit boards has evolved from thick films produced by printing methods to thin films produced by vapor deposition or sputtering methods. On the other hand, the integration of circuit boards themselves is progressing, and multilayer circuit boards using through holes are being put into practical use. Recently, many three-dimensional mounting methods have been attempted in which conductive films are formed not only on the front and back surfaces of circuit boards, but also on the side surfaces. The key point when forming a conductor pattern on the side surface of a substrate is how to make contact with the conductor pattern on the front (or back) surface.
第２図（ａ）〜（ｃ）は、従来の３次元回路基板の製造
法の一例である。第２図（ａ）に示すように、ガラス、
セラミックスなどのような絶縁性基板２１の表面と側面
のエツジ部を削り落として適当な角度の傾斜面２２を形
成する。傾斜面２２は、平面でなく所定の曲率を持つ曲
面でもよい。FIGS. 2(a) to 2(c) show an example of a conventional method for manufacturing a three-dimensional circuit board. As shown in FIG. 2(a), glass,
The edges of the front and side surfaces of an insulating substrate 21 made of ceramics or the like are ground down to form sloped surfaces 22 with appropriate angles. The inclined surface 22 may not be a flat surface but may be a curved surface having a predetermined curvature.
次いで第２図（ｂ）に示すように、基板表面と側面に一
度に、または数回に分けて蒸着、スパッタなどの薄膜形
成法により導体膜２３を形成する。Next, as shown in FIG. 2(b), a conductor film 23 is formed on the surface and side surfaces of the substrate at once or in several steps by a thin film forming method such as vapor deposition or sputtering.
斜め方向からの蒸着、スパッタを利用することにより、
導体膜２３は基板表面からエツジ部の傾斜面を通って側
面まで連続的に形成される。そしてリソグラフィ技術に
より、表面に配線パターン２Ｂ、、２３２．・・・を形
成する。この方法によれば、基板エツジ部に予め傾斜面
２２を形成しているために、基板表面の配線と側面の導
体膜との電気的接続が自動的にとれることになる。By using vapor deposition and sputtering from an oblique direction,
The conductive film 23 is formed continuously from the substrate surface to the side surface through the sloped surface of the edge portion. Then, using lithography technology, wiring patterns 2B, 232 . ... to form. According to this method, since the inclined surface 22 is formed in advance at the edge portion of the substrate, electrical connection between the wiring on the surface of the substrate and the conductive film on the side surface can be automatically established.
しかしこの従来法では、表面と側面のエツジ部に傾斜面
を形成しているとはいえ、薄膜導体で表面と側面の電気
的接続を十分な信頼性をもってとることは難しい。また
エツジを落とさなければならず、斜め方向からの蒸着を
行わなければならない等、工程的に複雑で、コスト高に
なり、量産にも向かない。基板側面の導体膜をバターニ
ングしたい場合には、リソグラフィ技術の適用が非常に
困難である。However, in this conventional method, although sloped surfaces are formed at the edges of the front and side surfaces, it is difficult to establish an electrical connection between the front and side surfaces with sufficient reliability using a thin film conductor. In addition, the process is complicated, as the edges must be removed and the deposition must be performed from an oblique direction, resulting in high costs and is not suitable for mass production. When it is desired to pattern the conductor film on the side surface of the substrate, it is very difficult to apply lithography technology.
（発明が解決しようとする問題点）
以上のように従来の薄膜技術を用いた３次元回路基板は
、製造工程が複雑で信頼性も低く、また基板側面のパタ
ーン形成が難しい、といった問題があった。(Problems to be Solved by the Invention) As mentioned above, three-dimensional circuit boards using conventional thin film technology have problems such as complicated manufacturing processes, low reliability, and difficulty in forming patterns on the sides of the board. Ta.
本発明は、この様な問題を解決した回路基板およびその
製造方法を提供することを目的とする。An object of the present invention is to provide a circuit board that solves these problems and a method for manufacturing the same.
［発明の構成コ
（問題点を解決するための手段）
本発明にかかる回路基板は、絶縁性基板の側面には厚膜
による導体膜が形成され、表面には側面の導体膜の端面
に一部が接触するように薄膜による配線パターンが形成
されていることを特徴とする。[Configuration of the Invention (Means for Solving Problems) The circuit board according to the present invention has a thick conductive film formed on the side surface of an insulating substrate, and a thick conductive film formed on the surface of the insulating substrate. A thin film wiring pattern is formed so that the parts are in contact with each other.
この様な回路基板を形成する本発明の方法は、まず絶縁
性基板の側面に印刷法等の厚膜技術により導体膜を形成
し、次いで基板表面に蒸着法、スパッタ法等の薄膜技術
とりソグラフィ技術によって、配線パターンを形成する
。これにより基板表面の配線パターンは、基板側面の導
体膜の基板表面に終端する端面に一部コンタクトする状
態となり、３次元的回路基板が得られる。The method of the present invention for forming such a circuit board involves first forming a conductive film on the side surface of an insulating substrate using a thick film technique such as printing, and then applying a thin film technique such as vapor deposition or sputtering to the surface of the substrate. Wiring patterns are formed using technology. As a result, the wiring pattern on the surface of the substrate comes into contact with the end surface of the conductor film on the side surface of the substrate, which terminates on the surface of the substrate, and a three-dimensional circuit board is obtained.
（作用）
本発明によれば、基板側面の導体膜を厚膜により形成す
るため、その基板表面に終端する端面に比較的大きい面
積を確保することができる。従って従来のように基板の
エツジを削り落とすことなく、また斜め方向の蒸着やス
パッタを行うことなく、表面の薄膜配線パターンを側面
の導体膜に電気的にコンタクトさせることができる。こ
の結果、簡単な工程で安価に、しかも信頼性の高い３次
元回路基板を得ることができる。(Function) According to the present invention, since the conductor film on the side surface of the substrate is formed as a thick film, a relatively large area can be secured at the end surface terminating on the surface of the substrate. Therefore, the thin film wiring pattern on the front surface can be brought into electrical contact with the conductor film on the side surface without cutting off the edges of the substrate or performing diagonal vapor deposition or sputtering as in the conventional method. As a result, a highly reliable three-dimensional circuit board can be obtained through simple steps and at low cost.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図（ａ）〜（ｃ）は本発明の一実施例の回路基板製
造工程を示す。第１図（ａ）に示すように、ガラスやセ
ラミックスなどの絶縁性基板１１の側面に、銀ペースト
を数１０μｍ厚で印刷し、焼付けて導体膜１２を形成す
る。スリクーン印刷法を用いれば、側面の導体膜１２は
容品に所定パターンに形成することができる。この基板
側面の導体膜１２の基板表面に出る端面１３は、幅が数
１０μｍとなる。次に第１図（ｂ）に示すように、基板
１１の表面全面に、蒸着法またはスパッタ法により金等
の導体膜１４を形成する。この表面の導体膜１４は、側
面の導体膜１２の端面１３にコンタクトする。このコン
タクトが良好であるためには、側面の導体膜１２の端面
１３が、その面位置が基板表面と一致してしがちある程
度以上の面積（幅）を有し、かつ平滑であることが必要
である。そのため、導体膜１２の膜厚は最低限１０μｍ
程度とし、また必要ならば、予め端面１３を研磨して平
滑化する工程をいれる。この後、基板表面の導体膜１４
を通常のりソグラフィ技術によりバターニングして、第
１図（Ｃ）に示すように、側面の導体膜１３と電気的に
つながる配線パターン１４１，１４４．・・・を形成す
る。基板１１の裏面にも必要に応じて薄膜配線パターン
を形成する。FIGS. 1(a) to 1(c) show the manufacturing process of a circuit board according to an embodiment of the present invention. As shown in FIG. 1(a), a conductive film 12 is formed by printing silver paste to a thickness of several tens of micrometers on the side surface of an insulating substrate 11 made of glass, ceramics, etc. and baking it. By using the screen printing method, the conductor film 12 on the side surface can be formed in a predetermined pattern on the container. The end surface 13 of the conductor film 12 on the side surface of the substrate that appears on the substrate surface has a width of several tens of μm. Next, as shown in FIG. 1(b), a conductor film 14 of gold or the like is formed over the entire surface of the substrate 11 by vapor deposition or sputtering. The conductor film 14 on the front surface contacts the end surface 13 of the conductor film 12 on the side surface. In order for this contact to be good, the end surface 13 of the side conductor film 12 must have an area (width) of at least a certain level where the surface position tends to coincide with the substrate surface, and must be smooth. It is. Therefore, the thickness of the conductor film 12 is at least 10 μm.
If necessary, a step of polishing and smoothing the end face 13 may be performed in advance. After this, the conductor film 14 on the substrate surface
are patterned using normal gluing lithography technology to form wiring patterns 141, 144, . ... to form. A thin film wiring pattern is also formed on the back surface of the substrate 11 if necessary.
こう１７てこの実施例によれば、基板のエツジを削ると
いう工程も要らず、斜め蒸着という工程も要らず、簡単
に３次元回路基板を得ることができる。側面の導体膜の
膜厚がある程度以上あれば、表面の配線パターンと側面
の導体膜の電気的コンタクトは十分良好にとれ、信頼性
の高いものが得られる。According to this embodiment, a three-dimensional circuit board can be easily obtained without the need for a step of cutting the edges of the substrate or a step of oblique vapor deposition. If the thickness of the conductive film on the side surface is above a certain level, electrical contact between the wiring pattern on the surface and the conductive film on the side surface can be made sufficiently good, and a highly reliable product can be obtained.
本発明は上記実施例に限られるものではない。The present invention is not limited to the above embodiments.
例えば基板は、ガラスやセラミックスの他、ガラスエポ
キシなど、あらゆる絶縁性の基板を用いることができる
。また表面の薄膜形成法は、蒸着やスパッタの他、ＣＶ
Ｄ法等でもよい。側面の厚膜の形成法も、印刷法に限ら
れず、必要な膜厚が得られる方法であればよい。For example, the substrate can be any insulating substrate such as glass, ceramics, glass epoxy, etc. In addition, methods for forming thin films on the surface include vapor deposition, sputtering, and CVD.
D method etc. may also be used. The method for forming the thick film on the side surface is not limited to the printing method, and any method that can obtain the required film thickness may be used.
その池水発明はその趣旨を逸脱しない範囲で柾々変形し
て実施することができる。The pond water invention can be practiced with various modifications without departing from its spirit.
［発明の効果〕
以上述べたように、本発明による回路基板は、信頼性の
高い３次元回路基板となる。また本発明の方法によれば
、信頼性の高い３次元回路基板を簡単な工程で安価に実
現することができる。[Effects of the Invention] As described above, the circuit board according to the present invention becomes a highly reliable three-dimensional circuit board. Further, according to the method of the present invention, a highly reliable three-dimensional circuit board can be realized at low cost through simple steps.
（ｅ）は従来の回路基板の製造工程を示す斜視図である
。
］−１・・・絶縁性基板、１２・・・導体膜（厚膜）、
１３・・・端面、１４・・・導体膜（薄膜）、１４１゜
１４２・・・配線パターン。
出願人代理人 弁理士 鈴江武彦(e) is a perspective view showing a conventional circuit board manufacturing process. ]-1... Insulating substrate, 12... Conductor film (thick film),
13... End face, 14... Conductor film (thin film), 141°142... Wiring pattern. Applicant's agent Patent attorney Takehiko Suzue
Claims (2)
された回路基板において、側面には厚膜による導体膜が
形成され、表面には薄膜による配線パターンがその一部
を前記側面の導体膜の端面に接触させて形成されている
ことを特徴とする回路基板。(1) In a circuit board in which wiring is formed from the surface to the side surface of an insulating substrate, a thick conductive film is formed on the side surface, and a thin film wiring pattern is formed on the surface, with a portion of the wiring pattern extending from the side surface. A circuit board characterized in that it is formed in contact with an end surface of a conductor film.
、この後表面に前記側面の導体膜の端面に接続される薄
膜による配線パターンを形成することを特徴とする回路
基板の製造方法。(2) A method for manufacturing a circuit board, comprising forming a thick conductor film on the side surface of an insulating substrate, and then forming a thin film wiring pattern on the surface to be connected to the end surface of the conductor film on the side surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28811687A JPH01129488A (en) | 1987-11-13 | 1987-11-13 | Circuit substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28811687A JPH01129488A (en) | 1987-11-13 | 1987-11-13 | Circuit substrate and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01129488A true JPH01129488A (en) | 1989-05-22 |
Family
ID=17726012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28811687A Pending JPH01129488A (en) | 1987-11-13 | 1987-11-13 | Circuit substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01129488A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021188271A1 (en) * | 2020-03-17 | 2021-09-23 | Corning Incorporated | Electronic apparatus |
-
1987
- 1987-11-13 JP JP28811687A patent/JPH01129488A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021188271A1 (en) * | 2020-03-17 | 2021-09-23 | Corning Incorporated | Electronic apparatus |
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