JPH01232855A - Communication system - Google Patents

Abstract

PURPOSE:To omit a communication initializing line not used in a normal operation by jointly using the communication initializing line and the communication control line between communication equipments. CONSTITUTION:If a communication initializing signal is not sent to a request signal line 16, since a port P2 reaches an L level, a slave CPU 20 sends a request signal from a port P1. On the other hand, with the communication initializing signal sent to the signal line 16, since the level of the signal line 16 reaches the L level, a transistor 26 acting like an input buffer is turned off and the port P2 reaches an H level. Thus, the Q output of a FF 40 reaches an L level, interruption to the CPU 20 is generated and the CPU 20 executes the initializing processing of the communication part.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to a plurality of central processing systems, for example.
The present invention relates to a communication method between units (hereinafter referred to as CPUs), and particularly to a recovery method in the event of a communication error.

Conventional technology FIG. 5 is a block diagram of a conventional communication system.

When the slave CPU 20 wants to transmit data to the master CPU l0, the slave CPU 20 sends a request signal from the boat P22 to the line i1, and
u io receives the request signal at boat P12. If master cputo can receive, boat PIO
sends a receivable signal to line 12 from the slave CP.
U20 receives the receivable signal from boat P20.

After completing the above procedure, the slave CPU 20 will transmit data from the boat P21 to the line e3.

When the master CPU 10 recognizes the reception of all data, it transmits an acknowledge signal to the slave CPU 20, and data transmission and reception between the mask CPU 10 and the slave CPU 20 is completed.

However, when the communication program of the slave CPU 20 stops being executed for some reason, that is, when the slave CPU 20 falls into a software loop process or goes out of control, the master CPU 10 uses a communication command to execute the slave CPU 20. In such a case, when it becomes impossible to initialize the master CPtJ
10 needs to send an initialization signal from the boat P13 via the line 14 to the boat P23 of the slave CPtJ20 to forcibly initialize the slave CPU20.

Usually, an external interrupt terminal is used as the port P23.

Problems to be Solved by the Invention As described above, when an abnormality occurs in the communication program of the slave CPtJ20, the dedicated line e4 is required to initialize the slave CPU20.

In addition, the initialization dedicated line 14 is used in extremely rare cases such as when there is a communication error, and the wiring is unnecessary when the power is on.

Means for Solving the Problems The present invention is a communication method that starts transmission by outputting a communication request signal between one communication device and the other communication device via a single signal line, wherein one-way communication The communication system is characterized in that the device includes a holding means for holding a communication request signal when the communication request signal is output from the other communication device, and the one-way communication device is initialized by the output of the holding means. .

According to the present invention, when starting communication from one communication device to another communication device, one communication device outputs a transmission request signal to the other communication device via a single line. After the other communication device receives this communication request signal, the one communication device initiates the desired communication.

On the other hand, when the other communication device outputs a communication request signal to the single line to the one communication device, the holding means of the one communication device holds the signal.

On the other hand, the communication device is initialized by this holding means output. This makes it possible to forcibly initialize the one-way communication device even when there is a software error, and furthermore, it is possible to omit a dedicated signal line for transferring the command to initialize the one-way communication device, greatly simplifying the configuration. can be converted into

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the present invention. The data transfer procedure from the slave CPU 20, which is one communication device, to the master CPU 10, which is the other communication device, is performed according to the communication program of the slave CPU 20 shown in FIG. explain. When the slave CPU 20 needs to transfer data to the master CPULO, the slave CPU 20 determines whether a communication initialization signal is present on the request signal line 16, which is a single signal line (step 5PI). That is, slave CPU 20 determines the voltage level of boat P2.

If a communication initialization signal is sent onto the request signal line 16, the request signal line 16 goes to the "L" level, and the transistor 26, which functions as an input buffer, is turned off. Therefore, the collector terminal voltage of the transistor 26 becomes approximately the same potential as the power supply terminal 28 connected to the pull-up resistor 27, and the boat P2 becomes the "Ho" level.

Conversely, if the communication initialization signal is not sent onto the request signal line 16, the transistor 26 is turned on and the port P2 becomes "L" level.

If there is no communication initialization signal on the request signal line 16, the slave CPU 20 sends a request signal from the boat P1 (step 5P2).

The signal is transmitted to master CPU10 via transistor 22, diode 23, request signal line 16 and input buffer 11. Upon accepting the request signal from the slave CPU 20, the master CPU 10 sends an inquiry signal to the slave CPU/\\. That is, master CPU10, buffer 52, reception ready signal 18
, the inquiry signal is transmitted via the buffer 54.

The slave CPU 20 waits for the inquiry signal to be transmitted from the master CPU 10 (step 5P3),
Upon receiving the interrogation signal, the slave CPU 20 connects the mask CPU 10'\buffer 53 and signal line 17.
, the data is transmitted via the buffer 51 (step 5P4).

When mask CPU10 receives all data, slave C
PU20 hair removal signal A CK receivable signal 1
Send on 8. The slave CPU 20 waits for reception of the acknowledge signal ACK (step 5P5), and upon acceptance, performs a communication program termination procedure (step 5P6). In this way, master CPU10 and slave C
Data transmission between the PU 20 and the request signal line 16
controlled by.

Next, the initial communication fhi will be explained using FIG. FIG. 4 (1) shows the signal waveform on the request signal line 16,
The figure (2) shows the voltage waveform of the positive terminal of the capacitor 32,
In the same figure (3) is the D of the flip-flop 40 which is the holding means.
Input waveform, same 12! <4) is the Q of flip frog 40
Output waveform, that is, external interrupt input of slave CPU 20 (
NMi). From master CPU10, Figure 4 (1)
Suppose that a pulse with a time width T1 shown by is sent out.

The t pulse passes through the request signal line 16 and turns off the transistor 26 of the input buffer. As a result, the logic output of the inverter 29, in other words, one input of the NOR circuit 30 becomes "L" level. Assuming that the boat P1 of the slave CPU 20 is normally at the “L” level, NO
The output of the R circuit 30 becomes H" level. Therefore, the capacitor 32 of the integrating circuit composed of the resistor 31 and the capacitor 32 is charged, and the potential rises as shown in the voltage waveform of FIG. 4 (2). .

The output of this integrating circuit, that is, the positive terminal of capacitor 32, is connected to the non-inverting input terminal of comparator 37 and to comparator 38.
is connected to the inverting input terminal of

The voltage value at the non-inverting input terminal of the comparator 37 is
5 and the voltage value determined by the ratio of the resistor 36, that is, the 411th
If the voltage value T h of m(2) is lower than 1, the output is at the "HI" level, and if it is higher, the output is at the "H" level. Therefore, as shown in Figure 4 (2), the master CPU 1
When the time width of the pulse from 0 is as short as T1, the integrated voltage at the positive terminal of the capacitor 32 is lower than the comparison voltage T h 1 of the comparator 37, so the output voltage of the comparator 37 does not change. Maintain “L” level.

Next, assume that a communication initialization signal with a time width T2 as shown in FIG. 4(1) is sent out from the mask CPU. As described above, the integration operation starts at the same time as the falling edge of the pulse, and when the integrated voltage rises and exceeds the comparison voltage T h 1,
As shown in FIG. 4 (3), the output of the comparator 37 is "H"
level. When the communication initialization signal from the mask CPU 10 ends, the flip-flop 40 takes in the rising edge of the signal as a latch signal from the outputs of the two inverting circuits, and holds the data on the D input terminal of the flip-flop 40.

Since the Q output of the flip-flop 40 is an inverted value of the input data, it is output from the master CP as shown in FIG. 4 (4).
At the same time as the communication initialization signal from Ul0 rises, Q
The output becomes "L" level.

The Q output is transmitted to the external interrupt (NMi) terminal of the slave CPU 20, and the slave CPU 20 starts external interrupt processing.

That is, as shown in FIG. 3, initialization processing of the communication section of the slave CPU is executed (step IP1). After transmitting the communication initialization signal, master CPU10 transmits a pulse having a time width T3 as shown in FIG. 4(1).

This is for resetting the Q output of the flip-flop 40 to "H" level. Let's explain its operation.

As shown in No. 4111 (2>), the integration operation starts at the same time as the pulse is sent out, and the integrated voltage at the positive terminal of the capacitor 32 rises. If it exceeds, the output of the comparator 37 becomes '
becomes H” level.Furthermore, the integrated voltage increases and comparator 3
8, the inverting input voltage becomes higher than the non-inverting input voltage of the comparator 38, so the output voltage of the comparator 38 becomes "L" level.

That is, the D input terminal of the flip-flop 40 is “L°
° level. In this state, when the pulse from the master CPU10 ends, the flip-flop 40 catches the rising edge of the pulse and latches the D input data. Therefore, the Q output of the flip-flop 40 is
) changes to the “H” level.

As shown in Figure 4 (2), after the start of integration, the integrated voltage is T
The time it takes to reach h 1 is Ts, and the integrated voltage is T h
Let T be the time it takes to reach 2. Mask CPU
If the signal pulse width from 10 is T, then T (T s
...If it is (1), it is not determined to be a communication initialization signal, and no external interrupt signal is generated to the slave CPU 20.

And T s Ku T Ku T 0
... (2), it is determined to be a communication initialization signal and an external interrupt signal is generated. Furthermore, if T > T R (3), similarly to the first equation above, it is not determined to be a communication initialization signal, and no external interrupt signal is generated.

In this embodiment, an integrator circuit and a comparator are used as means for measuring the pulse width, but other means may be used, for example, by calculating the AND of the signal pulse wave from the master CPU10 and the continuous pulse wave generated by the oscillation circuit. Alternatively, a counter circuit may be used to count continuous pulse waves among the signal pulse waves to be timed.

Effects of the Invention As described above, according to the present invention, by sharing the communication control line and the communication initialization line between communication devices, the communication initialization line that is not used during normal operation can be omitted, and the communication Even when there is an abnormality in communication between devices, communication can be restored to normal 1M without performing operations such as turning off the power.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, 2I is a communication control flowchart, 3121 is a communication initialization flowchart, FIG. 4 is a timing chart for explaining the circuit operation shown in FIG. FIG. 5 is a block diagram for explaining the prior art. 21.24, 25, 27, 31, 34, 35°36.3
9...Resistor, 22.26...Transistor, 2
...Inverting circuit, 30...NOR circuit, 32...Capacitor, 37.38...Comparator, 40...Flip-flop agent Patent attorney Keiichi Nishikyo Part 2rA Figure 3 4 [4 5] figure

Claims (1)

[Claims] A communication method in which a communication request signal is output and transmission is started between one communication device and the other communication device via a single signal line, wherein one communication device is connected to the other communication device. 1. A communication method, comprising: a holding means for holding a communication request signal when the communication request signal is output from the device, and the one-way communication device is initialized by the output of the holding means.