JP2001148719A - Data reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate reception error due to noise that the output signal RCV of a comparator for reception for a signal in the differential format of a USB has in an EOP period. SOLUTION: The comparator 5 for reception is connected to 1st and 2nd signal lines 3a and 3b connected to a USB connector 1. A receive signal correcting circuit 11 is provided at the output stage of this comparator 5. This correcting circuit 11 is composed of 1st and 2nd noise removing circuits 6 and 7 composed of Schmitt trigger circuits connected to the 1st and 2nd signal lines 3a and 3b, a NOR gate 15, and an OR gate 16. The outputs of the noise removing circuits 6 and 7 are sent to the NOR gate 15. The comparator 5 is connected to one input terminal of the OR gate 16 and the NOR gate 15 is connected to the other input terminal. In an EOP period, the output of the OR gate 16 is held at high level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data receiving apparatus suitable for an interface of a USB device connected to a personal computer.

[0002]

2. Description of the Related Art As is well known, USB (Universal Serial Bus) is a serial data transmission line, and has two signal lines and two signal lines.
Power lines. FIG. 1 shows an example of a conventional USB transmitting / receiving circuit 2 connected to a USB connector 1. From a USB connector 1 connected to a USB cable (not shown), first and second signal lines 3a and 3b for serially transmitting data and first and second power supplies for power supply. Lines 4a and 4b are derived. The transmitting and receiving circuit 2 includes first and second noise removing circuits 6 and 7 each including a comparator 5 and a Schmitt trigger circuit.
And a transmission signal forming circuit 8.

The first and second signal lines 3a and 3b are for serially transmitting data by differential first and second signals. The positive signal line and the second signal line 3b can be called reversed-phase or negative signal lines. That is, the PACK before t4 in FIG. 2 is connected to the first signal line 3a.
The binary normal phase signal shown in FIG. 2A is transmitted in the main data block section indicated as ET, and the second signal line 3b is connected to the second signal line 3b.
As shown in FIG. 2B, a signal having the opposite phase to the signal shown in FIG. 2A is transmitted. In the EOP (End of Packet) section consisting of a 2-bit period (2Tb) from t4 to t6 in FIG. 2 indicating the end of a packet composed of a plurality of bits, the same low-level (L) EOP data The data (additional data) is transmitted to the first and second signal lines 3a and 3b.

The comparator 5 has a positive input terminal connected to the first signal line 3a and a negative input terminal connected to the second signal line 3b, and the potential of the positive input terminal is negative. When the potential is higher than the potential of the terminal, t0 to t2 and t3 to t4 in FIG.
To output a high-level voltage (first voltage level), and conversely, output a low-level voltage (second voltage level) when the potential of the positive input terminal is lower than the potential of the negative input terminal. Is formed. The output of the comparator 5 is used as a received signal RCV as a USB interface circuit (not shown).
Sent to

The first and second noise elimination circuits 6 and 7 each comprising a Schmitt trigger circuit having hysteresis have a first
And the second and third signal lines 3a and 3b.
When the voltage level of the signal lines 3a and 3b is higher than a predetermined level, a high level voltage is output, and when the voltage level is lower than the predetermined level, a low level voltage is output. The first and second noise elimination circuits 6 and 7 composed of a Schmitt trigger circuit are equivalently shown in FIG.
As shown in FIG. 2, a first comparator 61a, a first reference voltage source 6a, a second comparator 61b,
, And a flip-flop 70. When the input voltage of the positive input terminal of the first comparator 61a is higher than the first reference voltage Vt1, the first comparator 61a generates a high-level output voltage. The input voltage of the negative input terminal of the second comparator 61b is equal to the first input voltage.
When the second comparator 61b is lower than the second reference voltage Vt2 which is set lower than the reference voltage Vt1, the second comparator 61b generates a low-level output voltage. The output of the first comparator 61a is connected to the S input terminal of the flip-flop 70, and the output of the second comparator 61b is connected to the R input terminal of the flip-flop 70. As a result, as shown in FIG. 13A, when the voltage of the input signal gradually increases from a low voltage, when the voltage of the input signal exceeds the first reference voltage Vt1, FIG.
A high level output voltage is generated as shown in FIG. And
Once the high level is reached, when the voltage of the input signal gradually decreases from the high voltage, the first reference voltage Vt1
When the voltage falls below the lower second reference voltage Vt2, a low-level output voltage is generated. The outputs of the first and second noise elimination circuits 6 and 7 are connected to the first in the interface circuit.
And the state of the signals on the second signal lines 3a and 3b.

The transmission circuit 8 creates differential transmission data based on the signal from the USB interface circuit and sends it to the first and second signal lines 3a and 3b.

[0007]

The transmitting and receiving circuit 2
In a computer system in which a floppy disk drive (FDD) is connected via a USB interface circuit and a floppy disk control circuit (FDC), a USB signal reception error may occur.
This reception error occurs in the EOP section as shown in FIG. Originally, the same level voltage should not be applied to the two input terminals of the saturation type differential amplifier (comparator), and if the voltage applied to each of the two input terminals is the same level, the potential difference Since there is almost no noise, a slight potential difference is generated only by noise on the signal line. For a saturation amplifier, even a small potential difference has a large effect, and the output sometimes becomes H or L depending on the case and is not preferable. As a result, the output of the comparator 5 becomes an undefined state in which it becomes high level or low level between t4 and t6 shown by hatching in FIG. 2C, so that the EOP and the main data are output. It becomes impossible to distinguish. In short, the output of the comparator 5 is in the EOP interval t4 to t
6 becomes unstable and a reception error occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a receiving apparatus capable of accurately receiving a main data block composed of a differential signal and additional data composed of the same phase signal.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems and to achieve the above object, the present invention provides a main data block comprising an array of a plurality of binary data and the main data block. First and second signal lines for serially transmitting additional data indicating the predetermined state, and a pair of differential input terminals connected to the first and second signal lines, A comparator for outputting a signal representing a difference between the first signal of the first signal line and the second signal of the second signal line, wherein the signal is transmitted when the main data block is transmitted. The first and second signals are in anti-phase relationship with each other, and when transmitting the additional data, the
A data receiving apparatus in which a first signal and a second signal are in phase relationship with each other and have substantially the same potential, and are high when the outputs of the first and second signal lines are simultaneously in the same output voltage state. A first logic circuit for outputting a level voltage and outputting a low level voltage when the outputs of the first and second signal lines are in different output voltage states, the comparator, and the first logic circuit; And the output of the comparator and the first
Output a signal indicating the logical sum with the output of the logic circuit of the second
And a data receiving device wherein the output of the second logic circuit is used as received data.

It is desirable that the first logic circuit be a NOR gate and the second logic circuit be a logical sum circuit. Further, the first logic circuit is an OR type NOR gate, and the second logic circuit is composed of two OR gates.
It is desirable to use a type NOR gate. In addition, the output of the second signal line can be inverted by an inverter, and the output of the phase-inverted output and the output of the differential amplifier circuit can be input to the OR circuit. Claim 5
As shown in (1), a level shift function can be added to the OR circuit connected to the comparator. Claim 6
As shown in (1), the additional data can be set to logic 1, the first logic circuit can be an AND circuit, and the second logic circuit can be an OR circuit. It is desirable that a noise removing circuit be provided as described in claim 7.

[0011]

According to the present invention, the first and second signals of the first and second signal lines or the second signal of the second signal line and the output of the receiving comparator are output. Therefore, the reception output of the additional data, which is originally an unstable output, can be stabilized, and the reception error can be prevented. Further, according to the third aspect of the present invention, since the first and second logic circuits are configured by the same type of NOR gate, this configuration is facilitated. According to the fifth aspect of the invention, the level shift and the correction of the received signal can be easily achieved.

[0012]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.

[0013]

[First Embodiment] First, the US of the first embodiment shown in FIG.
The USB external storage device 10 including the B interface and the floppy disk drive will be described. However, the connector 1, the first and second signal lines 3a and 3b, the first and second power supply lines 4a and 4b, the comparator 5, the first and second noise removal circuits 6, 7 in FIG. The transmitting circuit 8 is the same as that shown in FIG. 1 with the same reference numerals, and a description thereof will be omitted.

The USB external storage device 10 according to the present embodiment includes a connector 1, a transmission / reception circuit 2a, a USB interface circuit 12, a floppy disk controller, that is, an FDC1.
3 and a floppy disk drive or FDD 14.

A received signal correction circuit 11 according to the present invention is provided at an output stage of a comparator 5 comprising a saturation type differential amplifier having the same configuration as that of FIG. This correction circuit 11
Are first and second noise elimination circuits 6, 7 comprising a Schmitt trigger circuit having hysteresis and first and second noise elimination circuits.
Logic circuits 15 and 16. First logic circuit 15
Is composed of an AND type NOR gate, one input terminal of which is connected to the first noise elimination circuit 6, and the other input terminal of which is connected to the second noise elimination circuit 7. The second logic circuit 16 comprises an OR gate, that is, an OR circuit, one input terminal of which is connected to the output terminal of the receiving comparator 5, and the other input terminal of which is the output terminal of the first logic circuit 15. It is connected to the.

The USB interface circuit 12 is connected to the second logic circuit 16 of the correction circuit, the first and second noise removal circuits 6 and 7, and the transmission circuit 8. FDC1
3 is connected between the USB interface circuit 12 and the FDD 14. The USB interface circuit 1
2 and the FDC can be one integrated circuit.

The USB interface circuit 12 has a line 17 for transmitting a binary signal generally indicated by VMO and a line 18 for transmitting a binary signal generally indicated by VPO.
And transmission line 8 for transmitting an output enable control signal, generally indicated by OE #, and transfer rate control line 20, generally indicated by SPEED.
It is connected to the. It should be noted that another signal (not shown) is also input to the transmission circuit 8. When the output enable control signal line 19 is at a low level, the transmission circuit 8 is in a transmittable state, sends binary data to the signal lines 3a, 3b, and is in a transmission prohibited state when the line 19 is at a high level.

Next, the operation of the received signal correction circuit 11 of FIG. 3 will be described with reference to FIG. FIG. 4A is the same as FIG. 2A and FIG. 2B for the first and second signal lines 3a and 3b in FIG.
Assuming that the binary positive-phase signal (first signal) and the binary negative-phase signal (second signal) shown in (B) are input, the output signal RCV of the receiving comparator 5 is shown in FIG. FIG. 4C is the same as FIG. 4C. The received signal RCV is the first signal during the period from t1 to t4 when the first signal and the second signal are in opposite phases (different voltage levels), that is, during the period when the packet as the main data block is transmitted. Is the same as However, the RCV of the received signal is compared during the period from t4 to t6 when the first signal and the second signal are in phase (same voltage level), that is, during the period when EOP is transmitted as additional data. Since the input signals at the time of amplification are at the same voltage level, there is almost no potential difference. Comparison amplifier or comparator
Since the amplifier 5 is a saturated amplifier, even a slight potential difference is reflected on the output signal. This slight potential difference occurs due to the layout of the printed pattern on the circuit board, external noise, and the like, and as a result, it becomes sensitive to noise. Therefore, during the period from t4 to t6, the reception signal R
The CV is sometimes at a high level and sometimes at a low level, and is extremely unstable as shown by hatching in FIG. 4C. The signal V from which noise has been removed through the first and second noise removal circuits 6 and 7 each comprising a Schmitt trigger
P and VM are first logic circuits 15 composed of NOR gates.
Is input to The first logic circuit 15 outputs the high-level output signal shown in FIG. 4F only during the period from t4 to t6 when both the output signals VP and VM of the first and second noise removal circuits 6 and 7 are simultaneously at low level. Occurs. The second logic circuit 16 composed of an OR gate is high as shown in FIG. 4 (G) when one or both of the signal of FIG. 4 (C) and the signal of FIG. 4 (F) are at a high level. Output level. During the main data transmission period of the packet before t4 in FIG. 4, the output of the first logic circuit 15 does not interfere with the transmission of the received signal in FIG. T in FIG.
Since the output of the first logic circuit 15 is continuously at the high level during the EPO period from 4 to t6, the output of the second logic circuit 16 is also continuously at the high level as shown in FIG. Become. As a result, at the output of the second logic circuit 16, FIG.
The indefinite period of the received signal RCV in (C) is masked, and EP
The O period remains at a high level. Therefore, data reception errors can be prevented. The USB interface circuit 12
Determines that the output of the second logic circuit 16 is EOP data, that is, additional data, when the output of the second logic circuit 16 continuously becomes high during the 2-bit EOP period. The USB interface circuit 12 also uses the outputs of the first and second noise elimination circuits 6, 7 consisting of a Schmitt trigger circuit. Therefore,
The correction circuit 11 of the present embodiment has a configuration in which the first and second noise removal circuits 6 and 7 which are also used in the conventional circuit are used, and the circuit configuration is simplified.

[0019]

Second Embodiment Next, a receiving circuit according to a second embodiment will be described with reference to FIG. However, in FIG. 5 and FIGS. 6 to 11 to be described later, parts common to FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted.

The received signal correcting circuit 11a in the receiving circuit shown in FIG. 5 includes first and second noise removing circuits 6 and 7 similar to FIG. 3 and a NOR gate 1 as a first logic circuit 15.
5a, and the first and second NOR gates 16a and 16b of the second logic circuit 16. The first and second noise elimination circuits 6 and 7 are the same as those indicated by the same reference numerals in FIG. The NOR gate 15a of the first logic circuit 15 is OR
It is an OR gate type having a configuration in which the output of the gate is inverted, and operates with the same logic as the NOR gate of the AND gate type having two inputs inverted in FIG. One input terminal of the first OR gate type NOR gate 16a of the second logic circuit 16 is connected to the receiving comparator 5, and the other input terminal is connected to the NOR gate 15a of the first logic circuit 15. It is connected. The output of the first OR gate type NOR gate 16a is connected to two input terminals of the second OR gate type NOR gate 16b. Therefore, the combination of the first and second NOR gates 16a and 16b forms an OR circuit,
It operates similarly to FIG. In FIG. 5, three ORs of the same format
Since the first and second logic circuits 15 and 16 are configured by the gate type NOR gates 15a, 16a and 16b, the configuration of the logic circuits 15 and 16 is facilitated.

The first and second noise removing circuits 6 in FIG.
First and second delay circuits 21 and 22 are connected between the interface circuit 7 and the interface circuit 12. First delay circuit 2
Reference numeral 1 denotes a series circuit of two inverters (NOT circuits) 21a and 21b. The second delay circuit 22 is composed of a series circuit of two inverters 22a and 22b. First and second
The delay time of the delay circuits 21 and 22 is the second logic circuit 16
Is almost the same as the delay time. As a result, the delay time of the RCV, VP, and VM signals given to the interface circuit 12 can be kept the same, and their synchronization can be kept good.

The receiving circuit of FIG. 5 has the same effects as those of the receiving circuit of FIG. 3 and also has the special effects of the circuit of FIG.

[0023]

Third Embodiment A received signal correction circuit 11b according to a third embodiment shown in FIG. 6 includes a noise removal circuit 7 and an inverter (N
OT circuit) 31 and OR gate 32 as an OR circuit
Consisting of The noise removing circuit 7 removes noise of the second signal on the second signal line 3b to form a VM signal as in FIG. The inverter 31 is a noise removal circuit 7
The output of is inverted. One input terminal of the OR gate 32 is connected to the receiving comparator 5, and the other input terminal is connected to the inverter 31.

The output of the inverter 31 shown in FIG.
4E is obtained by inverting the phase of the VM signal.
The waveform is the same as (G). Therefore, the output of the OR gate 32 becomes an OR output of the waveform of FIG. 4A and the waveform of FIG. 4G, and the noise of the received signal RCV is removed by the output of the inverter 31. Therefore, the receiving circuit of FIG. 6 has the same operation and effect as the receiving circuit of FIG.

[0025]

Fourth Embodiment A received signal correction circuit 11c according to a fourth embodiment shown in FIG.
, An OR gate 41, an OR circuit 42 having a level shift function, and a pull-up resistor 73. The first and second noise removing circuits 6 and 7 are the same as those denoted by the same reference numerals in FIG. 3 and output the VP signal and the VM signal shown in FIGS. Since the two input terminals of the NOR gate 41 are connected to the first and second noise elimination circuits 6 and 7, the output terminal has the same waveform as that of FIG. Can be One input terminal 42a of the OR circuit 42 having a buffer circuit configuration is connected to the receiving comparator 5, the other input terminal 42b is connected to the NOR gate 41, and the pull-up resistor 43 is connected to the OR circuit 4.
2 and the positive power supply terminal 47.

The OR circuit 42 comprises first and second inverters 44 and 45 and a transistor 46 as a switch element, as shown in principle in FIG. The two inverters 44, 45 are connected in series to the RCV signal line. The transistor 46 is connected between the output terminal of the first inverter 44 and the ground, and its base is connected to the input terminal 42b. FIG. 9 shows the first inverter 44.
When the RCV signal shown in FIG.
The signal of (B) is obtained. Since the output of the NOR gate 41 is kept low as shown in FIG. 9C during the main data transmission before the time t4 in FIG.
From FIG. 5, a signal corresponding to FIG. 9B is obtained as shown in FIG. 9D, and this is level-shifted by the voltage of the power supply terminal 47. During the EOP period from t4 to t6, the NOR gate 4
1 becomes high level, and the input of the second inverter 45 is forcibly made low level.
As shown in (D), the level becomes high, and a signal from which noise has been removed can be obtained as in the first embodiment. The fourth embodiment has the same effects as the first embodiment, and the buffer or level shift circuit and the logic circuit share the same circuit element, so that the circuit configuration is simplified. It has the effect of.

[0027]

Fifth Embodiment A receiving circuit according to a fifth embodiment shown in FIG. 10 has first and second signal lines 3a and 3b connected to the receiving circuit shown in FIG.
As shown in (B), a reception signal correction circuit 11d for dealing with a case where a high level signal is transmitted during the EOP period t4 to t6 is provided. This reception signal correction circuit 11d has an AND gate 51 as a first logic circuit and an OR gate 52 as a second logic circuit. First of AND gate 51
And the second input terminal are connected to the first and second noise removing circuits 6 and 7, respectively. One input terminal of the OR gate 52 is connected to the receiving comparator 5, and the other input terminal is connected to the AND gate 51.

As shown in FIG. 11 (F), the output of the AND gate 51 is maintained at a low level during the main data transmission period before t4, and is maintained at a high level during the EOP period from t4 to t6. The OR gate 52 is connected to the RCV signal of FIG.
It becomes an OR signal with the output signal of the AND gate 51 of 1 (F), and changes as shown in FIG. FIG.
The signal in (G) is the same as the signal in FIG. Therefore, according to the fifth embodiment, similarly to the first embodiment, a received signal from which noise has been removed can be obtained.

[0029]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Instead of configuring the noise removing circuits 6 and 7 with Schmitt trigger circuits, they can be configured with buffer amplifiers having threshold values. In this case, noise below the threshold is removed. (2) The correction circuits 11 to 11d can be integrally formed in the IC of the USB interface circuit 12. (3) The first logic circuit 15 in FIG. 3 can be a NOR gate formed to invert the output of the OR gate. (4) In the receiving circuits of FIGS. 3, 6, 7, and 10, the output signals V of the first and second noise removing circuits 6, 7 are also used.
A line that performs the same function as the delay circuits 21 and 22 in FIG. 5 can be provided on a line that sends P and VM to the USB interface circuit 12. (5) The present invention can be applied to an external storage device other than a floppy disk drive device and a receiving circuit in various peripheral devices connected to USB.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a conventional USB transmission / reception device.

FIG. 2 is a waveform diagram showing a voltage state of each part in FIG.

FIG. 3 is a block diagram illustrating a USB external storage device according to the first embodiment of this invention.

FIG. 4 is a waveform chart showing voltage states of respective parts in FIG.

FIG. 5 is a block diagram illustrating a receiving circuit according to a second embodiment.

FIG. 6 is a block diagram illustrating a receiving circuit according to a third embodiment.

FIG. 7 is a block diagram illustrating a receiving circuit according to a fourth embodiment.

FIG. 8 is a block diagram showing the OR circuit of FIG. 7;

FIG. 9 is a waveform chart showing voltage states of respective parts in FIG.

FIG. 10 is a block diagram illustrating a receiving circuit according to a fifth embodiment.

FIG. 11 is a waveform chart showing voltage states of respective parts in FIG.

FIG. 12 is a circuit diagram illustrating a noise removal circuit in principle.

FIG. 13 is a waveform diagram showing the input voltage and the output voltage of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 USB connector 2a Transmission / reception circuit 3a, 3b 1st and 2nd signal line 5 Reception comparator 6, 7 1st and 2nd noise removal circuit 8 Transmission circuit 11 Received signal correction circuit 15 1st logic circuit 16 Second logic circuit

Claims (7)

[Claims] 1. A first and a second serial transmission of a main data block comprising an array of a plurality of binary data and additional data indicating a predetermined state of the main data block. And a pair of differential input terminals connected to the first and second signal lines, wherein a first signal of the first signal line and the second signal
And a comparator for outputting a signal having a difference from the second signal of the first signal line, wherein the first and second signals have an anti-phase relationship with each other during transmission of the main data block. A data receiver in which the first and second signals are in phase with each other and have substantially the same potential when transmitting the additional data; Outputting a high-level voltage when the outputs are simultaneously in the same output voltage state;
A first logic circuit that outputs a low-level voltage when the outputs of the signal lines are in different output voltage states, and the comparator is connected to the first logic circuit;
A second logic circuit for outputting a signal indicating a logical sum of an output of the comparator and an output of the first logic circuit, wherein an output of the second logic circuit is used as reception data A data receiving device characterized by the above-mentioned. 2. The additional data according to claim 1, wherein said first and second signals are low-level voltages indicating logic 0, and said first logic circuit is a NOR gate. 2. The data according to claim 1, wherein the second logic circuit is an OR circuit connected to the comparator and the NOR gate.
Receiver. 3. The NOR gate of the first logic circuit is an OR gate.
An OR type NOR gate for inverting the output of the OR gate, wherein the OR circuit as the second logic circuit is connected to the comparator and the NOR gate of the first logic circuit. The first OR type NOR gate and two input terminals are connected to the first OR type.
Of the second OR type connected to the NOR gate of the second OR type
3. The data according to claim 2, comprising an R gate.
Receiver. 4. A main data comprising an array of a plurality of binary data.
Data block, first and second signal lines for serially transmitting additional data indicating a predetermined state of the main data block, and a pair connected to the first and second signal lines. And a comparator for outputting a signal representing a difference between a first signal of the first signal line and a second signal of the second signal line in the same phase as the first signal. When transmitting the main data block, the first and second signals have a reverse phase relationship to each other, and when transmitting the additional data,
A data receiving device in which the first and second signals are in phase with each other and have substantially the same potential; and an inverter connected to the second signal line; and a comparator. A data OR device having an OR circuit connected to the inverter, wherein an output of the OR circuit is used as received data. 5. The data receiving apparatus according to claim 2, wherein said OR circuit has a level shift circuit for setting an output level different from said input level. 6. The additional data sets the first and second signals to a high-level voltage indicating a logical 1; the first logic circuit is an AND circuit; 2. The data receiving device according to claim 1, wherein the second logic circuit is an OR circuit. 7. The semiconductor device according to claim 1, further comprising first and second noise removing circuits between said first and second signal lines and said first logic circuit. The data receiving device as described in the above.