JPH01232808A - Voltage amplifier with low voltage current limit - Google Patents

Voltage amplifier with low voltage current limit

Info

Publication number
JPH01232808A
JPH01232808A JP63058275A JP5827588A JPH01232808A JP H01232808 A JPH01232808 A JP H01232808A JP 63058275 A JP63058275 A JP 63058275A JP 5827588 A JP5827588 A JP 5827588A JP H01232808 A JPH01232808 A JP H01232808A
Authority
JP
Japan
Prior art keywords
current
base
transistor
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63058275A
Other languages
Japanese (ja)
Inventor
Akira Kageyama
章 影山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP63058275A priority Critical patent/JPH01232808A/en
Publication of JPH01232808A publication Critical patent/JPH01232808A/en
Pending legal-status Critical Current

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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To set an optical voltage amplification factor and to limit optionally its output current at the same time by connecting a base of a 2nd transistor(TR) to the base of a 1st TR so as to regulate the operation of the 1st TR by the 2nd TR when an output current of a differential amplifier circuit reaches a prescribed value or over. CONSTITUTION:The circuit is constituted by connecting a base of a TR Q6 to a base of a TR Q5, connecting a collector of the TR Q6 to a current source 3 and also to a base of a TR Q7, and connecting an emitter of the TR Q7 to a base of the TR Q5. Through the constitution above, the voltage amplification factor of an open loop is set higher by the TR Q5. Moreover, the sink current is limited by a current of a current source 2 and the source current is limited by a current of the current source 3. That is, with a current over a current 2I2 flowing to the collector of the TR Q6, the base potential of the TR Q5 rises to limit the output current. Thus, both the source and sink output currents are limited in this circuit by using the current I2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、低電圧で動作ししかも電流制限機能が付加さ
れた電圧増幅回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage amplification circuit that operates at low voltage and is additionally provided with a current limiting function.

〔従来の技術〕[Conventional technology]

第3図に従来の低電圧動作の電圧増幅回路を示す。この
回路は、トランジスタQ1、Q2からなる差動増幅回路
で構成され、トランジスタQ3、Q4からなるカレント
ミラー回路を負荷として具備する。1は電流■1の電流
源である。
FIG. 3 shows a conventional voltage amplifier circuit operating at a low voltage. This circuit is composed of a differential amplifier circuit made up of transistors Q1 and Q2, and has a current mirror circuit made up of transistors Q3 and Q4 as a load. 1 is a current source of current ■1.

この回路における出力電流は、シンク、ソースともに電
流11により制限することができる。しかし、入出力間
の電圧増幅度が低く、またその電圧増幅度が負荷と電流
1.により決定されるため、任意の電圧増幅度や電流1
+を設定することが困難である。
The output current in this circuit can be limited by the current 11 for both the sink and source. However, the voltage amplification degree between input and output is low, and the voltage amplification degree is 1. Therefore, any voltage amplification degree or current 1
It is difficult to set +.

第4図に示す回路はこの点を考慮したものであり、出力
側にトランジスタQ5を加えて電圧増幅度を充分高くし
たものである。2は電流■2の電流源、Cは位相補償用
コンデンサである。
The circuit shown in FIG. 4 takes this point into consideration, and adds a transistor Q5 to the output side to make the voltage amplification sufficiently high. 2 is a current source of current 2, and C is a phase compensation capacitor.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この回路では、シンク電流は電流■2により制限するこ
とができるが、ソース電流はトランジスタQ5の電流増
幅率と電流■1を乗じたものとなり、任意の値をとるこ
とは掻めて困難である。
In this circuit, the sink current can be limited by the current ■2, but the source current is the product of the current amplification factor of the transistor Q5 and the current ■1, and it is extremely difficult to take an arbitrary value. .

本発明の目的は、任意の電圧増幅度を設定でき、同時に
任意に出力電流を制限することもできるようにすること
である。
An object of the present invention is to be able to set an arbitrary voltage amplification degree and at the same time to arbitrarily limit the output current.

〔課題を解決するための手段〕[Means to solve the problem]

このために本発明は、差動増幅回路の出力側にコレクタ
接地の第1のトランジスタを接続し、該第1のトランジ
スタのコレクタ側に定電流源を接続した電圧増幅回路に
おいて、 上記第1のトランジスタのベースに第2のトランジスタ
のベースを接続して5、上記差動増幅回路の出力電流が
所定値以上となることにより上記第2のトランジスタに
より上記第1のトランジスタの動作を規制するようにし
た。
For this purpose, the present invention provides a voltage amplification circuit in which a first transistor with a common collector is connected to the output side of the differential amplification circuit, and a constant current source is connected to the collector side of the first transistor. A base of a second transistor is connected to a base of the transistor, and when the output current of the differential amplifier circuit exceeds a predetermined value, the second transistor regulates the operation of the first transistor. did.

〔実施例〕〔Example〕

以下、本発明の実施例につ、いて説明する。第1図はそ
の一実施例の電圧増幅回路を示す図である。
Examples of the present invention will be described below. FIG. 1 is a diagram showing a voltage amplifying circuit according to one embodiment.

本実施例では、第4図におけるトランジスタQ5のベー
スにトランジスタQ6のベースを接続し、そのトランジ
スタQ6のコレクタを電流212の電流源3に接続する
と共にトランジスタQ7のベースに接続して、そのトラ
ンジスタQ7のエミッタをトランジスタQ5のベースに
接続したものである。
In this embodiment, the base of the transistor Q6 is connected to the base of the transistor Q5 in FIG. The emitter of is connected to the base of transistor Q5.

この回路では、トランジスタQ5によりオープンループ
の電圧増幅度を充分高く設定することがきる。また、シ
ンク電流は電流源2の電流により制限することができ、
ソース電流は、電流源3の電流により制限することがで
きる。即ち、トランジスタQ6のコレクタに電流2IZ
以上の電流が流れるとトランジスタQ7のエミッタ電位
が上昇してトランジスタQ5のベース電位を持ち上げ、
出力電流を制限する。以上のようにこの回路では、電流
I2により出力電流をソース、シンク共に制限すること
ができる。
In this circuit, the open loop voltage amplification degree can be set sufficiently high by the transistor Q5. In addition, the sink current can be limited by the current of current source 2,
The source current can be limited by the current of the current source 3. That is, a current 2IZ is applied to the collector of the transistor Q6.
When the above current flows, the emitter potential of transistor Q7 rises, raising the base potential of transistor Q5,
Limit the output current. As described above, in this circuit, both the source and sink output currents can be limited by the current I2.

第2図(al〜(C)は第1図に示した回路、つまりオ
ーブンループの電圧増幅度を充分高くした回路を単一の
電圧増幅器Aとして、帰還量の適宜設定により任意の電
圧増幅度を実現できるようにした増幅回路を構成した図
である。供給電圧は0.9vで動作可能としている。
Figure 2 (al to (C)) shows the circuit shown in Figure 1, that is, the circuit in which the voltage amplification degree of the oven loop is sufficiently high, as a single voltage amplifier A, and any voltage amplification degree can be set by appropriately setting the feedback amount. 1 is a diagram configuring an amplifier circuit that can realize the following.It is possible to operate with a supply voltage of 0.9V.

(a)はバッファ回路として構成したもので、入力電圧
Viと同一の電圧が負荷抵抗RLによらず出力される。
(a) is configured as a buffer circuit, and the same voltage as the input voltage Vi is output regardless of the load resistance RL.

(′b)は反転増幅器とし構成したもので、入力電圧V
iの位相が反転して出力する。電圧増幅度は帰還ループ
の抵抗Ra、Rbにより設定される。(C)は正転増幅
器として構成したもので、電圧増幅度は同様に帰還ルー
プの抵抗RC% Rdにより設定される。
('b) is configured as an inverting amplifier, and the input voltage V
The phase of i is inverted and output. The voltage amplification degree is set by the feedback loop resistors Ra and Rb. (C) is configured as a non-rotating amplifier, and the voltage amplification degree is similarly set by the resistance RC% Rd of the feedback loop.

このように、低電圧で演算増幅回路とほぼ同様に使用す
ることができ、また電流Itにより出力電流制限も可能
となる。また供給電圧が出力電圧に制限を与えない範囲
に負荷抵抗RLを比較的小さくすれば、その負荷抵抗R
Lと電流■2とにより、出力電圧制限をも行うことがで
きる。
In this way, it can be used almost in the same way as an operational amplifier circuit at a low voltage, and output current can also be limited by the current It. Also, if the load resistance RL is made relatively small within a range where the supply voltage does not limit the output voltage, then the load resistance R
Output voltage can also be limited by L and current (2).

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、出力電流制限が可能とな
り、電圧増幅度も帰還量の設定により任意に設定するこ
とがきるようになる。
As described above, according to the present invention, it is possible to limit the output current, and the degree of voltage amplification can also be arbitrarily set by setting the amount of feedback.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の電圧増幅回路の回路図、第
2図18)〜(e)は第1図の回路を使用した各種回路
の回路図、第3図及び第4図は従来の電圧増幅回路の回
路図である。 代理人 弁理士 長 尾 常 明
Figure 1 is a circuit diagram of a voltage amplification circuit according to an embodiment of the present invention, Figure 2 18) to (e) are circuit diagrams of various circuits using the circuit of Figure 1, and Figures 3 and 4 are circuit diagrams of various circuits using the circuit of Figure 1. FIG. 2 is a circuit diagram of a conventional voltage amplification circuit. Agent Patent Attorney Tsuneaki Nagao

Claims (1)

【特許請求の範囲】[Claims] (1)、差動増幅回路の出力側にコレクタ接地の第1の
トランジスタを接続し、該第1のトランジスタのコレク
タ側に定電流源を接続した電圧増幅回路において、 上記第1のトランジスタのベースに第2のトランジスタ
のベースを接続して、上記差動増幅回路の出力電流が所
定値以上となることにより上記第2のトランジスタによ
り上記第1のトランジスタの動作を規制するようにした
ことを特徴とする低電圧電流制限電圧増幅回路。
(1) In a voltage amplification circuit in which a first transistor with a common collector is connected to the output side of the differential amplification circuit, and a constant current source is connected to the collector side of the first transistor, the base of the first transistor is A base of a second transistor is connected to the differential amplifier circuit, and when the output current of the differential amplifier circuit exceeds a predetermined value, the second transistor regulates the operation of the first transistor. A low voltage and current limiting voltage amplification circuit.
JP63058275A 1988-03-14 1988-03-14 Voltage amplifier with low voltage current limit Pending JPH01232808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63058275A JPH01232808A (en) 1988-03-14 1988-03-14 Voltage amplifier with low voltage current limit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63058275A JPH01232808A (en) 1988-03-14 1988-03-14 Voltage amplifier with low voltage current limit

Publications (1)

Publication Number Publication Date
JPH01232808A true JPH01232808A (en) 1989-09-18

Family

ID=13079636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63058275A Pending JPH01232808A (en) 1988-03-14 1988-03-14 Voltage amplifier with low voltage current limit

Country Status (1)

Country Link
JP (1) JPH01232808A (en)

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