JPH02153624A - Invertor circuit - Google Patents

Invertor circuit

Info

Publication number
JPH02153624A
JPH02153624A JP63308094A JP30809488A JPH02153624A JP H02153624 A JPH02153624 A JP H02153624A JP 63308094 A JP63308094 A JP 63308094A JP 30809488 A JP30809488 A JP 30809488A JP H02153624 A JPH02153624 A JP H02153624A
Authority
JP
Japan
Prior art keywords
input voltage
base current
transistor
inverter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63308094A
Other languages
Japanese (ja)
Inventor
Mikio Hikino
幹夫 引野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63308094A priority Critical patent/JPH02153624A/en
Publication of JPH02153624A publication Critical patent/JPH02153624A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00376—Modifications for compensating variations of temperature, supply voltage or other physical parameters in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the over-driving of a transistor and to obtain a satisfactory switching characteristic along a wide input voltage range by providing a base current limitation circuit which makes a base current constant when an input voltage value is higher than a prescribed set value. CONSTITUTION:The base current limitation circuit 4 consists of base current limitation resistances R2 and R3 and base current limitation transistors Q2 and Q3. When an input voltage V1 is 'H', the base current IBI of the transistor Q1 can be limited to the prescribed value which does not depend on the input voltage V1 along the wide input voltage range. Thus, the satisfactory switching characteristic can be obtained in the wide input voltage range since the transistor Q1 is prevented from being over-driven.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体集積回路内で使用されるインバータ回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inverter circuit used within a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

従来、半導体集積回路内で使用されるインバータ回路と
しては第４図に示す回路があった。Conventionally, there has been a circuit shown in FIG. 4 as an inverter circuit used in a semiconductor integrated circuit.

第４図において、１はインバータ入力端子、２は電圧基
準端子、３はインバータ出力端子、５は電源端子、Ｒ１
は入力抵抗、Ｒ４は出力抵抗、Ｑ。In Fig. 4, 1 is an inverter input terminal, 2 is a voltage reference terminal, 3 is an inverter output terminal, 5 is a power supply terminal, and R1
is the input resistance, R4 is the output resistance, and Q.

はインバータ用トランジスタである。is an inverter transistor.

第３図は第４図の動作信号波形を示しており、ｖｌはイ
ンバータ入力端子１へ印加される入力電圧、Ｖコはイン
バータ出力端子３に出力される出力電圧である。FIG. 3 shows the operating signal waveform of FIG. 4, where vl is the input voltage applied to the inverter input terminal 1, and Vco is the output voltage output to the inverter output terminal 3.

以上のように構成されたインバータ回路において、イン
バータ入力端子ｌに入力電圧ｖ１を入力すると、入力電
圧Ｖ、が“Ｌ”（例えばＯＶ）の時トランジスタＱ、は
ＯＦ’Ｆ状態であり、■、は′Ｈｓとなる。In the inverter circuit configured as described above, when input voltage v1 is input to the inverter input terminal l, when the input voltage V is "L" (for example, OV), the transistor Q is in the OFF state; becomes 'Hs.

次に入力電圧Ｖ、を“Ｈ″　（例えば１０ｖ）にすると
、時間ｔ１の遅延の後出力電圧■、はＬ″（約ＯＶ）に
なる、さらに、入力電圧■、を“Ｌ”にすると、時間ｔ
、の遅延の後出力電圧Ｖ、は“Ｈ′になりインバータと
して動作する。Next, when the input voltage V is set to "H" (for example, 10 V), the output voltage (■) becomes L" (approximately OV) after a delay of time t1. Furthermore, when the input voltage (V) is set to "L", time t
After the delay of , the output voltage V becomes "H" and operates as an inverter.

（発明が解決しようとする課題） 従来のインバータ回路は以上のように構成されていたの
で、入力電圧Ｖ、が“Ｈ”のとき、トランジスタＱ、の
ベース・エミッタ間電圧をｖｌＩ。(Problems to be Solved by the Invention) Since the conventional inverter circuit is configured as described above, when the input voltage V is "H", the base-emitter voltage of the transistor Q is vlI.

ベース電流■、とすると、次（１１式が成り立つ。Assuming that the base current is ■, the following (Equation 11) holds true.

トランジスタＱ１のコレクタ電流をＩＣ１％　ｈｙｔｈ
　１！＋ 倍程度が望ましい。The collector current of transistor Q1 is IC1%hyth
1! + It is desirable to have about twice as much.

しかし、このインバータ回路では入力電圧■１が高過ぎ
て、■、が必要以上に大きくなり過ぎると、ベース電流
のオーバードライブになり、遅延時間ｔ２が大きくなる
結果、スイッチング特性が悪くなるという欠点があった
。However, in this inverter circuit, if the input voltage (1) is too high and (2) becomes too large than necessary, the base current will be overdriven, the delay time t2 will increase, and the switching characteristics will deteriorate. there were.

この発明は上記のような従来の欠点をなくすためになさ
れたもので、広い入力電圧範囲において、良好なスイッ
チング特性を持つインバータ回路を得ることを目的とす
る。This invention was made to eliminate the above-mentioned conventional drawbacks, and aims to provide an inverter circuit with good switching characteristics over a wide input voltage range.

〔課題を解決するための手段〕 この発明に係るインバータ回路は入力電圧値がある設定
以上ではベース電流を定電流化するベース電流制限回路
を設けたものである。[Means for Solving the Problems] The inverter circuit according to the present invention is provided with a base current limiting circuit that makes the base current constant when the input voltage value exceeds a certain setting.

〔作用〕[Effect]

この発明におけるベース電流制限回路は入力電圧がある
設定値以上ではベース電流が制限されて定電流となり、
トランジスタのオーバードライブを防止できるので、広
い入力電圧範囲に沿って良好なスイッチング特性が得ら
れる。In the base current limiting circuit according to the present invention, when the input voltage exceeds a certain set value, the base current is limited and becomes a constant current.
Since overdriving of the transistor can be prevented, good switching characteristics can be obtained over a wide input voltage range.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例によるインバータ回路の回路図
を示し、図において、符号１〜３５とＲ１，Ｒａおよび
Ｑｌは前記従来のものの同一である０図中、４はベース
電流制限回路である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a circuit diagram of an inverter circuit according to an embodiment of the present invention, and in the figure, numerals 1 to 35 and R1, Ra, and Ql are the same as those of the conventional one. 0 In the figure, 4 is a base current limiting circuit. .

Ｒｇ　、Ｒ３はベース電流制限用抵抗、Ｑｌ　、Ｑｓは
ベース電流制限用トランジスタであり、これらによりベ
ース電流制限回路４が構成されている。Rg and R3 are base current limiting resistors, Ql and Qs are base current limiting transistors, and a base current limiting circuit 4 is constituted by these.

このインバータ回路の動作信号波形は前記従来のものと
同じ（第３図で示される。The operating signal waveform of this inverter circuit is the same as that of the conventional circuit (as shown in FIG. 3).

次に動作について説明する。Next, the operation will be explained.

トランジスタＱ１のベース電流１ｍｌがどのように制限
されるかを示す、ベース電流１ｍｌは入力電圧Ｖ１が“
Ｈ”の時、次（２）式で表わされる。Showing how 1 ml of base current of transistor Q1 is limited, 1 ml of base current is limited when input voltage V1 is “
H'', it is expressed by the following equation (2).

Ｒ１＋Ｒコ 従って、ベース電流は１ｍｌは入力電圧ｖ１がおＲｇ　
　　　　　　　　　Ｒ３ ここでは、トランジスタＱよとＱ、は同一特性であり、
ベース電流は無視できるものとしている。Therefore, the base current is 1ml when the input voltage v1 is Rg.
R3 Here, transistors Q and Q have the same characteristics,
The base current is assumed to be negligible.

さらに、Ｒ＋　　”Ｒａ　　Ｖｓｔ＋　＝Ｖｍｔｔ　と
仮定すると、前記＋２１．１３１式より次（４）式が導
出される。Furthermore, assuming that R+ ``Ra Vst+ =Vmtt, the following equation (4) is derived from the above equation +21.131.

Ｒ８ ただし、トランジスタＱ□、Ｑ３が非導通である■１電
圧範囲では、前記（２）式においてＩｃ１＝０として次
（５）式で表わされる。R8 However, in the ■1 voltage range where the transistors Q□ and Q3 are non-conducting, the following equation (5) is expressed with Ic1=0 in the above equation (2).

この入力電圧ｖ１の概略範囲は 電圧■１に依存するが、入力電圧ｖＩがおよそＲ５ ず、定電流となる。The approximate range of this input voltage v1 is Although it depends on the voltage ■1, the input voltage vI is approximately R5 Therefore, the current becomes constant.

以上のようにこの実施例では入力端子■、がＨ”の時、
広い入力電圧範囲に沿ってトランジスタＱ１のベース電
流Ｉ□を入力端子ｖ１に依存しない値の一定値に制限で
き、オーバードライブが防止できる。As mentioned above, in this embodiment, when the input terminal ■, is H'',
The base current I□ of the transistor Q1 can be limited to a constant value independent of the input terminal v1 over a wide input voltage range, and overdrive can be prevented.

第２図はこの発明の他の実施例を示す回路図で、第１図
のベース電流制限抵抗Ｒ３の代わりに定電流値１．を設
定する定電流値Ｉ０を設けている。FIG. 2 is a circuit diagram showing another embodiment of the present invention, in which the base current limiting resistor R3 of FIG. 1 is replaced with a constant current value of 1. A constant current value I0 is provided for setting.

従って、入力電圧ｖ１が“Ｈ”の時、およそ、Ｒ１１゜
＋Ｖ、。を越えるとベース電流■、は１．に制限される
。従って、第１図のベース電流Ｉｌｌ制Ｒ３ し、第２図の場合は１゜に持たせた温度特性を持つこと
になる。Therefore, when the input voltage v1 is "H", approximately R11°+V. When the base current exceeds 1. limited to. Therefore, the base current Ill control R3 shown in FIG. 1 has a temperature characteristic of 1° in the case shown in FIG.

なお、上記実施例では抵抗をＲ＋　＝Ｒ１とし、さらに
トランジスタＱｔ　、　　Ｑｓ　のカレントミラーの電
流比を１対ｌとして説明したが、これらを変えても同等
の効果が達せられる。In the above embodiment, the resistance is set to R+ = R1, and the current ratio of the current mirror of the transistors Qt and Qs is set to 1:l, but the same effect can be achieved even if these changes are made.

このように、トランジスタＱ、がオーバードライブされ
ることがなくなるので、広い入力電圧範囲で良好なスイ
ッチング特性が得られる。In this way, the transistor Q is not overdriven, so good switching characteristics can be obtained over a wide input voltage range.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、入力電圧がある値を越
すとインバータとして働く主トランジスタのベース電流
を制限してオーバードライブを防ぐようにしたので、広
い入力電圧範囲で良好なスイッチング特性が得られる効
果がある。As described above, according to the present invention, when the input voltage exceeds a certain value, the base current of the main transistor acting as an inverter is limited to prevent overdrive, so good switching characteristics can be obtained over a wide input voltage range. It has the effect of

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例を示すインバータ回路の回
路図、第２図はこの発明の他の実施例を示すインバータ
回路の回路図、第３図はインバータ回路の動作４４号波
形を示す図、第４図は従来のインバータ回路の回路図で
ある。 図中、１・・・インバータ入力端子、２・・・電圧基準
端子、３・・・インバータ出力端子、４・・・ベース電
流制限回路、Ｒ１・・・インバータ入力抵抗、Ｑ、・・
・インパーク用トランジスタ、Ｉｏ・・・定電流回路。 なお、図中、同一符号は同一、または相当部分を示す。 代理人　　　　大　　岩　　増　　雄 手続補正書（自発） 墨籟ｒ１゛　　年２　イ２　日２ ３、補正をする者 代表者 士 Ｉじ１ 岐 守 哉 ５、　補正の対象 明細書の特許請求の範囲の欄、および発明の詳細な説明
の欄。 ６、　補正の内容 （１）明細書の特許請求の範囲全別紙のとおり訂正する
。 （２）明細書の第２頁第１２行に「トランジスタＱ３は
」とあるの全「トランジスタＱ１は」に訂正する。 （３）明細書の第６頁下から第４行に「設定する定電流
値Ｉｏ」とあるのを「設定する定電流源！。」に訂正す
る。 ７、　添付書類の目録 （１）訂正後の特許請求の範囲を記載した書面１通 以上 特許請求の範囲 インバータ入力端子とベースが抵抗で接続され、エミッ
タが電圧基準端子に接続され、コレクタがインバータ出
力端子に接続されたトランジスタと。 前記インバータ出力端子と前記電圧基準端子間１こ接続
され、インバータ入力電圧が設定値以上では、から成る
ことを特徴とするインバータ回路。Fig. 1 is a circuit diagram of an inverter circuit showing one embodiment of the present invention, Fig. 2 is a circuit diagram of an inverter circuit showing another embodiment of the invention, and Fig. 3 shows the operation No. 44 waveform of the inverter circuit. 4 are circuit diagrams of conventional inverter circuits. In the figure, 1... Inverter input terminal, 2... Voltage reference terminal, 3... Inverter output terminal, 4... Base current limiting circuit, R1... Inverter input resistance, Q,...
- Impark transistor, Io...constant current circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Procedural Amendment Written Procedural Amendment (Voluntary) Written by R1゛ Year 2 Year 2 Day 2 Day 2 3, Representative of the person making the amendment column, and a column for a detailed description of the invention. 6. Contents of the amendment (1) The entire scope of the claims in the description will be corrected as shown in the appendix. (2) In the 12th line of page 2 of the specification, the phrase "transistor Q3" is corrected to "transistor Q1." (3) In the fourth line from the bottom of page 6 of the specification, the phrase "constant current value Io to be set" is corrected to "constant current source to be set!". 7. List of attached documents (1) One or more documents stating the amended scope of claims.ClaimsThe inverter input terminal and base are connected by a resistor, the emitter is connected to a voltage reference terminal, and the collector is an inverter. with a transistor connected to the output terminal. An inverter circuit, characterized in that the inverter output terminal and the voltage reference terminal are connected to each other, and the inverter input voltage is equal to or higher than a set value.

Claims (1)

【特許請求の範囲】[Claims] インバータ入力端子とベースが抵抗で接続され、エミッ
タが電圧基準端子に接続され、コレクタがインバータ出
力端子に接続されたトランジスタと、前記インバータ入
力端子と前記電圧基準端子間に接続され、インバータ入
力電圧が設定値以上になったことを検出して入力電圧に
依存した電流を前記トランジスタのベースに出力するベ
ース電流制限回路とから成ることを特徴とするインバー
タ回路。A transistor is connected between the inverter input terminal and the voltage reference terminal, the transistor having a base connected to an inverter input terminal through a resistor, an emitter connected to a voltage reference terminal, and a collector connected to an inverter output terminal; An inverter circuit comprising a base current limiting circuit which detects that the input voltage has exceeded a set value and outputs a current depending on the input voltage to the base of the transistor.
JP63308094A 1988-12-05 1988-12-05 Invertor circuit Pending JPH02153624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63308094A JPH02153624A (en) 1988-12-05 1988-12-05 Invertor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63308094A JPH02153624A (en) 1988-12-05 1988-12-05 Invertor circuit

Publications (1)

Publication Number Publication Date
JPH02153624A true JPH02153624A (en) 1990-06-13

Family

ID=17976793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63308094A Pending JPH02153624A (en) 1988-12-05 1988-12-05 Invertor circuit

Country Status (1)

Country Link
JP (1) JPH02153624A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645890A2 (en) * 1993-09-24 1995-03-29 Nec Corporation BiCMOS logic circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645890A2 (en) * 1993-09-24 1995-03-29 Nec Corporation BiCMOS logic circuit
EP0645890A3 (en) * 1993-09-24 1996-01-17 Nec Corp BiCMOS logic circuit.

Similar Documents

Publication Publication Date Title
US4350904A (en) Current source with modified temperature coefficient
US4951003A (en) Differential transconductance circuit
CA1155924A (en) Electrically variable impedance circuit with feedback compensationn
US4950976A (en) Current variation reduction for mosfet current sources
JPH02153624A (en) Invertor circuit
US4766367A (en) Current mirror with unity gain buffer
JPH03113613A (en) Wide dynamic range current source circuit
JPS6167307A (en) Differential amplifier
JPH0448812A (en) Ramp waveform generating circuit
KR890012444A (en) Amplifier
JPS62250713A (en) Variable delay cirucit
JPS61144907A (en) Semiconductor circuit device
JPS60134506A (en) Differential amplifier
JPH01232808A (en) Voltage amplifier with low voltage current limit
JPH01183914A (en) Current change-over switch circuit
JPS58119014A (en) Power source device
JPH02162837A (en) Semiconductor integrated circuit
JPS6016127A (en) Current limiting circuit
JPH06104714A (en) Output circuit for semiconductor integrated circuit
JPH0553403B2 (en)
JPH0498683A (en) Differential amplifier circuit
JPH0358603A (en) Gain control circuit
JPH0368210A (en) Delay circuit
JPS62165224A (en) Constant current circuit
JPS60144114A (en) Current limiting circuit