JPS62104311A

JPS62104311A - Switch circuit

Info

Publication number: JPS62104311A
Application number: JP24511685A
Authority: JP
Inventors: Shizuo Ida; 井田　静男
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1985-10-31
Filing date: 1985-10-31
Publication date: 1987-05-14

Abstract

PURPOSE:To form a low input current type switch circuit which deals with a low input voltage by constituting a PNP differential amplifying circuit at an input stage by using four PNP transistors (TR) and using it for the transmission of an input voltage, and connecting a current mirror circuit to the differential amplifying circuit when switch control is performed. CONSTITUTION:When a switch circuit control terminal 28 is at 'H', a current flows through the PNP mirror circuit 40 and the differential amplifying circuit 30 operates, so that a voltage which is an high as the voltage (Vin) at an input terminal 6 is developed at an output terminal 7. When the control terminal 28 is at 'L', on the other hand, no current flows through the PNP mirror circuit 40, so the differential amplifying circuit 30 does not operate and the input voltage (Vin) is not outputted. The input voltage, therefore, becomes extremely low and the influence of the load is reduced. Further, the input is transmitted by the PNP differential amplifying circuit composed of TRs 8-11, so the input is transmitted even with a low input voltage including '0'V.

Description

【発明の詳細な説明】〔産業上の利用分野〕本発明は、安定な低入力電流を実現し、なおかつ低入力
電圧を正確に出力に伝達できるスイッチ回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switch circuit that can realize a stable low input current and accurately transmit a low input voltage to an output.

[Conventional technology]

従来のこの種のスイッチ回路の一例を第２図に示す、第
２図において、１，２は入力端子６電圧（Ｖ　ｉｎ）を
出力端子７に伝達するＮＰＮ）ランジスタ、３はこのス
イッチ回路を制御するスイッチングトランジスタ、４は
トランジスタ１．２を動作させるためのバイアス電流制
限抵抗、５はトラインチ回路の制御用信号ａが印加され
る制御用端子、９は電源電圧Ｖｃｃが印加される電源端
子である。An example of a conventional switch circuit of this type is shown in FIG. 2. In FIG. 4 is a bias current limiting resistor for operating the transistor 1.2, 5 is a control terminal to which a control signal a of the trinch circuit is applied, and 9 is a power supply terminal to which a power supply voltage Vcc is applied. be.

次に動作について説明する。この回路は制御用信号ａを
印加することによって入力電圧と同じ電圧が出力端子に
得られるという回路である。また低入力電圧でも伝達可
能な回路である。まず本ス出力電圧Ｖｉｎ、　Ｖｏｕｔ
の関係がＶｉｎ＞Ｖｏｕｔならトランジスタ１０ベース
に抵抗４によって制限される電流が流れて該トランジス
タ１がＯＮＬ、入力電圧を出力端子７に伝える。またＶ
ｉｎ＜Ｖｏｕｔならトランジスタ２のベースに電流が流
れて該トランジスタ２がＯＮをし、入力電圧を出力端子
７に伝達する。Next, the operation will be explained. This circuit is a circuit in which the same voltage as the input voltage can be obtained at the output terminal by applying the control signal a. It is also a circuit that can transmit data even at low input voltages. First, the main output voltage Vin, Vout
If the relationship is Vin>Vout, a current limited by the resistor 4 flows through the base of the transistor 10, and the transistor 1 is ONL, transmitting the input voltage to the output terminal 7. Also V
If in<Vout, a current flows to the base of transistor 2, turning on transistor 2 and transmitting the input voltage to output terminal 7.

一方、本スイッチ回路の制御用端子８が“Ｈ”の場合に
は、スイッチングトランジスタ３がＯＮされ、電源端子
９に接続されている抵抗４に流れる電流はスイッチング
トランジスタ３に流れ、トランジスタ１．２はＯＦＦと
なるので入力電圧Ｖｉｎは出力端子７には伝達されない
。On the other hand, when the control terminal 8 of this switch circuit is "H", the switching transistor 3 is turned on, the current flowing through the resistor 4 connected to the power supply terminal 9 flows to the switching transistor 3, and the transistor 1.2 is turned off, so the input voltage Vin is not transmitted to the output terminal 7.

[Problem that the invention seeks to solve]

ところが、上記従来回路の構成では、入力電流が出力端
子７に接続される負荷により決定されるため、入力電流
がかなり変動し大きくなることもあり、微少電流を要求
されるスイッチ回路には適さないという欠点があった。However, in the conventional circuit configuration described above, the input current is determined by the load connected to the output terminal 7, so the input current fluctuates considerably and can become large, making it unsuitable for switch circuits that require a small current. There was a drawback.

この発明は、上記のような従来のものの問題点を解消す
るためになされたもので、低入力電流形の低入力電圧対
応のスイッチ回路を得ることを目的とする。The present invention was made in order to solve the problems of the conventional ones as described above, and an object of the present invention is to obtain a low input current type switch circuit compatible with low input voltage.

[Means for solving problems]

本発明に係るスイッチ回路は、入力電圧の伝達はＰＮＰ
差動増巾回路構成を使用するとともにスイッチ制御は電
流ミラー回路を上記差動増巾回路に接続して行なうよう
にしたものである。In the switch circuit according to the present invention, the input voltage transmission is PNP.
A differential amplification circuit configuration is used, and switch control is performed by connecting a current mirror circuit to the differential amplification circuit.

[Effect]

本発明においては、入力段にＰＮＰ差動増巾回路を使用
するようにしたので、入力電流が安定。In the present invention, a PNP differential amplifier circuit is used in the input stage, so the input current is stable.

微少となり、さらには、低入力電圧の伝達も可能となる
。Furthermore, it becomes possible to transmit a low input voltage.

〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図は本発明の一実施例によるスイッチ回路を示し、
図において、８〜１１は差動増巾回路３０の入力段を構
成する第１〜第４のＰＮＰ　）ランジスタ、１２．１３
は差動増巾回路３０の負荷を構成するＮＰＮ　）ランジ
スタ、１４．１５はミラー回路４０を構成するＰＮＰ　
）ランジスタ、１６はＰＮＰミラー回路３０の電流１ｏ
を決定する抵抗、１８はスイッチングトランジスタ１７
のベース電流制御用抵抗、１９はアナログ電圧入力端子
、２０は出力端子である。FIG. 1 shows a switch circuit according to an embodiment of the present invention,
In the figure, 8 to 11 are first to fourth PNP transistors constituting the input stage of the differential amplifier circuit 30; 12.13
14.15 is an NPN transistor that constitutes the load of the differential amplifier circuit 30, and 14.15 is a PNP transistor that constitutes the mirror circuit 40.
) transistor, 16 is the current 1o of the PNP mirror circuit 30
18 is a switching transistor 17
19 is an analog voltage input terminal, and 20 is an output terminal.

このように構成された回路において、スイッチ回路制御
端子２８が“Ｈ”の場合には、ＰＮＰミラー回路４０に
電流が流れて差動増巾回路３０が動作し、入力端子６電
圧（Ｖｉｎ）に等しい電圧が出力端子７に出力される。In the circuit configured as described above, when the switch circuit control terminal 28 is "H", current flows through the PNP mirror circuit 40, the differential amplification circuit 30 operates, and the input terminal 6 voltage (Vin) increases. Equal voltages are output to the output terminal 7.

また、制御端子２８が“Ｌｌの場合には、ＰＮＰミラー
回路４０には電流が流れないため、差動増１１回路３０
は動作せずこのため、入力電圧（Ｖ　ｉｎ）は出力され
ない。差動増巾回路３０が動作した場合、入力電流は次
式％式％（但しβＰＭＰはＰＮＰ　）ランジスタの直流増巾率で
ある）従って入力電圧は微少となり、負荷に対しても影響を受
けにく（なる、さらにトランジスタ十〜い ◆からなるＰＮＰ差動増巾回路で入力を伝達するためＯ
ｖを含む低入力電圧でも出力に伝達される。Further, when the control terminal 28 is "Ll", no current flows through the PNP mirror circuit 40, so the differential amplifier 11 circuit 30
does not operate, so the input voltage (V in) is not output. When the differential amplifier circuit 30 operates, the input current is calculated using the following formula (%) (where βPMP is the DC amplification factor of the PNP transistor). Therefore, the input voltage becomes very small and is not affected by the load. In addition, since the input is transmitted by a PNP differential amplification circuit consisting of ten transistors,
Even low input voltages, including v, are transferred to the output.

〔Effect of the invention〕

以上のように、本発明に係るスイッチ回路によれば、Ｐ
ＮＰ差動増巾回路を使用することにより、入力端子電圧
を出力端まで伝達するようにしたので、入力電流が微少
となり、なおかつ低入力電圧にも対応でき、負荷による
変動もないものが得られる効果がある。As described above, according to the switch circuit according to the present invention, P
By using an NP differential amplification circuit, the input terminal voltage is transmitted to the output terminal, so the input current is minimal, and it can also handle low input voltages and has no fluctuations due to load. effective.

[Brief explanation of drawings]

第１図は本発明の一実施例によるスイッチ回路を示す図
、第２図は従来のスイッチ回路の一例を示す図である。１２．１３・・・ＮＰＮ　）ランジスタ、４，５，１６
．１８・・・抵抗、６・・・入力端子、７・・・出力端
子、８〜１１・・・第１〜第４のＰＮＰトランジスタ、
３０・・・差動増巾回路、４０・・・電流ミラー回路。７：Ｉ矛広子手続補正書（自発）昭和６１年　１月３１日２、発明の名称スイッチ回路３、補正をする者５、補正の対象明細書の特許請求の範囲の欄、及び発明の詳細な説明の
欄６、補正の内容（１）　　明細書の特許請求の範囲を別紙の通り訂正す
る。（２）　　同第３頁第７〜１０行の「また・・・・・・
伝達する。」を削除する。（３）同第３頁第１１行の「制御用端子８」を「制御用
端子３８」に訂正する。（４）同第５頁第７行の「１９は」を「６は」に訂正す
る。（５）同第５頁第７〜８行の「２０は」を「７は」に訂
正する。以上特許請求の範囲（１）　　ベースにアナログ信号が入力される入力端子
を有する第１のＰＮＰ　）ランジスタのエミッタを第２
のＰＮＰ　）ランジスタのベースに接続し該第２のトラ
ンジスタのエミッタを第３のＰＮＰトランジスタのエミ
ッタに共通接続するとともに該第３のトランジスタのベ
ースと第４のＰＮＰトランジスタのエミッタとを接続し該第４のトランジスタのベースと上記第３のトランジス
タのコレクタとを接続して差動増巾回路を構成し、上記［−のトランジスタの共通エミッタに制御用信号に
よりスイッチング制御される電流ミラー回路を接続し、上記第４のトランジスタのベースに出力端子を接続して
なることを特徴とするスイッチ回路。FIG. 1 is a diagram showing a switch circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a conventional switch circuit. 12.13...NPN) transistor, 4, 5, 16
．． 18...Resistor, 6...Input terminal, 7...Output terminal, 8-11...First to fourth PNP transistors,
30... Differential amplification circuit, 40... Current mirror circuit. 7: I Hiroshi Hiroko procedural amendment (voluntary) January 31, 1985 2, Title of the invention Switch circuit 3, Person making the amendment 5, Claims column of the specification to be amended, and details of the invention Explanation Column 6, Contents of Amendment (1) The scope of claims in the specification is corrected as shown in the attached sheet. (2) On page 3, lines 7-10, “Also...
introduce. ” to be deleted. (3) Correct "control terminal 8" in line 11 of page 3 to "control terminal 38". (4) Correct "19wa" in line 7 of page 5 to "6wa". (5) Correct "20 wa" in lines 7-8 of page 5 to "7 wa". Claims (1) A first PNP whose base has an input terminal into which an analog signal is input;
) connected to the base of the transistor, the emitter of the second transistor is commonly connected to the emitter of the third PNP transistor, and the base of the third transistor is connected to the emitter of the fourth PNP transistor; A differential amplifier circuit is constructed by connecting the base of the transistor No. 4 and the collector of the third transistor, and a current mirror circuit whose switching is controlled by a control signal is connected to the common emitter of the transistor No. 4. , A switch circuit characterized in that an output terminal is connected to the base of the fourth transistor.

Claims

[Claims]

(1) Connect the emitter of the first PNP transistor whose base has an input terminal into which an analog signal is input to the second PN transistor.
The fourth transistor is connected to the base of the P transistor, the emitter of the second transistor is commonly connected to the emitter of the third PNP transistor, and the base of the third transistor is connected to the emitter of the fourth PNP transistor. A differential amplifier circuit is configured by connecting the base of the transistor and the collector of the third transistor, and a current mirror circuit whose switching is controlled by a control signal is connected to the common emitter of the third and fourth transistors. A switch circuit characterized in that the output terminal is connected to the base of the fourth transistor.