JPH0122987B2 - - Google Patents

Info

Publication number
JPH0122987B2
JPH0122987B2 JP56016976A JP1697681A JPH0122987B2 JP H0122987 B2 JPH0122987 B2 JP H0122987B2 JP 56016976 A JP56016976 A JP 56016976A JP 1697681 A JP1697681 A JP 1697681A JP H0122987 B2 JPH0122987 B2 JP H0122987B2
Authority
JP
Japan
Prior art keywords
ceramic plate
board
heat dissipation
metal
solder layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56016976A
Other languages
Japanese (ja)
Other versions
JPS57132332A (en
Inventor
Toshiki Yagihara
Yoichi Nakajima
Masatami Miura
Toshiki Kurosu
Isao Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP1697681A priority Critical patent/JPS57132332A/en
Publication of JPS57132332A publication Critical patent/JPS57132332A/en
Publication of JPH0122987B2 publication Critical patent/JPH0122987B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は、絶縁型半導体装置に係り、絶縁用の
セラミツク板を大きくすることなく、電気的な絶
縁沿面距離を増大した端子構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated semiconductor device, and more particularly to a terminal structure in which an electrical insulation creepage distance is increased without increasing the size of an insulating ceramic plate.

絶縁型半導体装置は、半導体基体を金属放熱基
板上に絶縁しつつ載置し、金属端子によつて半導
体基体と装置外部とを連絡するようにした半導体
装置である。 An insulated semiconductor device is a semiconductor device in which a semiconductor substrate is placed on a metal heat dissipation substrate while being insulated, and the semiconductor substrate is connected to the outside of the device through metal terminals.

第１図に従来の絶縁型半導体装置の一例の要部
構造を示す。 FIG. 1 shows the main structure of an example of a conventional insulated semiconductor device.

第１図において、セラミツク板３の一方の主表
面には半田層２を介して銅等でできた金属放熱基
板１が接着されており、他方の主表面にはメタラ
イズ層４を介して、半田層５によりセラミツク板
３上に載置された半導体基体（図示せず）に電流
を流すためのＬ字形の金属端子６が接着されてい
る。更に半導体基体、メタライズ層、半田層、セ
ラミツク板、金属端子の一部は外部の雰囲気から
保護し損傷を防ぐために樹脂７にてモールドされ
ている。 In FIG. 1, a metal heat dissipating substrate 1 made of copper or the like is bonded to one main surface of a ceramic board 3 via a solder layer 2, and a metal heat dissipating substrate 1 made of copper or the like is bonded to the other main surface via a metallized layer 4. An L-shaped metal terminal 6 for conducting current is glued to a semiconductor body (not shown) placed on the ceramic plate 3 by the layer 5. Further, a portion of the semiconductor substrate, metallized layer, solder layer, ceramic plate, and metal terminals are molded with resin 7 to protect them from the external atmosphere and prevent damage.

絶縁型半導体装置は、本来、セラミツク板３に
より金属放熱基板１と、金属端子６及び半導体基
体とを電気的に絶縁することを特徴としている
が、その絶縁耐圧としては1500V〜2500V程度が
要求される。 An insulated semiconductor device is originally characterized by electrically insulating the metal heat dissipation substrate 1, the metal terminals 6, and the semiconductor substrate by the ceramic plate 3, but its dielectric strength is required to be about 1500V to 2500V. Ru.

前述した絶縁耐力を確保するためにはセラミツ
ク板３と樹脂７との密着を完全にすることが重要
であるが、実際の大量生産時には密着が悪くとも
絶縁耐力を確保できる構造にすることが、不良率
の低減、装置の信頼性を考慮した場合必要であ
る。そこで絶縁耐力を確保するためには、セラミ
ツク板の周辺に配置される金属端子と金属放熱基
板との間の絶縁沿面距離を大きくすることが必要
となるが、第１図で示すように絶縁沿面距離AB
間を大きくするため、従来構造ではセラミツク板
３の外形を大きくする方法が採用されていた。 In order to ensure the aforementioned dielectric strength, it is important to have perfect adhesion between the ceramic plate 3 and the resin 7, but in actual mass production, it is important to create a structure that can ensure dielectric strength even if the adhesion is poor. This is necessary when considering the reduction of defective rate and the reliability of the device. Therefore, in order to ensure dielectric strength, it is necessary to increase the insulation creepage distance between the metal terminals placed around the ceramic board and the metal heat dissipation board. distance AB
In order to increase the gap, in the conventional structure, a method was adopted in which the outer shape of the ceramic plate 3 was increased.

しかしながら近年、パツケージ寸法の小型化及
び金属端子間距離の規格化が進んでいるので、セ
ラミツク板３の寸法を大きくすることは好ましく
ない。 However, in recent years, the size of the package has been reduced and the distance between metal terminals has been standardized, so it is not desirable to increase the size of the ceramic plate 3.

そのために従来の構造では、絶縁沿面距離が犠
牲にされるという欠点を有していた。 Therefore, the conventional structure had the disadvantage that the insulation creepage distance was sacrificed.

本発明は前述した従来技術の欠点を改善し、セ
ラミツク板の大きさを変更せずに絶縁沿面距離を
大きくし絶縁耐力を増大した半導体装置を提供す
ることを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and to provide a semiconductor device in which the insulation creepage distance is increased and the dielectric strength is increased without changing the size of the ceramic plate.

かかる目的を達成する本発明半導体装置の特徴
とするところは、セラミツク板に金属端子を接着
するためのメタライズ層及び半田層の周縁を金属
端子の脚部位置よりセラミツク板の中央部側に位
置せしめ、これによつて金属端子と金属放熱基板
との絶縁沿面距離を大きくした点にある。 The semiconductor device of the present invention that achieves this object is characterized in that the periphery of the metallized layer and the solder layer for bonding the metal terminal to the ceramic plate is located closer to the center of the ceramic plate than the leg of the metal terminal. , thereby increasing the insulation creepage distance between the metal terminal and the metal heat dissipation board.

以下、本発明を実施例として示した第２図によ
り説明する。 The present invention will be explained below with reference to FIG. 2, which shows an example.

図において、１は金属放熱基板、３は金属放熱
基板１上に半田層２を介して載置接着されたセラ
ミツク板、６は全体としてＬ字形を有し、Ｌ字形
の底辺部がセラミツク板３の周辺付近上にメタラ
イズ層４及び半田層５を介して載置接着され、Ｌ
字形の脚部がセラミツク板３の周辺側に位置しセ
ラミツク板３の表面から直角方向に伸び、半導体
基体の電極と電気的に接続され半導体基体に電流
を通電するための金属端子、７は半導体基体、メ
タライズ層、半田層、セラミツク板、金属端子の
一部を被覆する樹脂である。金属端子６はその脚
部の樹脂７の外部における位置を第１図に示す従
来装置を変えることなく、金属端子６の底辺部と
セラミツク板３とを接着するメタライズ層４及び
半田層５をセラミツク板３の中央部側に位置せし
め、換言すれば、メタライズ層４及び半田層５の
外周縁位置を金属端子６の脚部位置よりもセラミ
ツク板３の中央部側に位置せしめ、これによつて
セラミツク板３の外周縁とメタライズ層２の外周
縁とを離間させて絶縁沿面距離AB間を大きくし
ている。また、金属端子６の底辺部と脚部との間
６ａを従来装置より大きい曲率半径で曲げ加工し
てある。これは耐圧低下を防止するためである。
即ち、絶縁沿面距離ABを更に大きくするため
に、メタライズ層４及び半田層５の位置を第２図
より更にセラミツク板３の中央部側に移行して金
属端子６とセラミツク板３との対向個所が長くな
ると樹脂モールドの際に空〓が発生し耐圧の低下
を招くおそれがあるが、６ａ部の曲率半径を大き
くすることによつてこれを防止することができ
る。 In the figure, 1 is a metal heat dissipation board, 3 is a ceramic plate placed and bonded on the metal heat dissipation board 1 through a solder layer 2, and 6 is L-shaped as a whole, and the bottom part of the L-shape is the ceramic plate 3. is placed and bonded on the vicinity of the periphery of the L
The leg portion of the letter shape is located on the peripheral side of the ceramic plate 3 and extends from the surface of the ceramic plate 3 in a perpendicular direction, and is electrically connected to the electrode of the semiconductor substrate to conduct current to the semiconductor substrate. 7 is a metal terminal for semiconductor. It is a resin that covers part of the base, metallized layer, solder layer, ceramic plate, and metal terminal. In the metal terminal 6, the metallized layer 4 and the solder layer 5 bonding the bottom part of the metal terminal 6 and the ceramic plate 3 are bonded to the ceramic plate without changing the external position of the resin 7 of the leg part of the conventional device shown in FIG. In other words, the outer peripheral edges of the metallized layer 4 and the solder layer 5 are positioned closer to the center of the ceramic plate 3 than the leg positions of the metal terminals 6. The outer periphery of the ceramic plate 3 and the outer periphery of the metallized layer 2 are spaced apart to increase the insulation creepage distance AB. Further, the space 6a between the bottom part and the leg part of the metal terminal 6 is bent with a radius of curvature larger than that of the conventional device. This is to prevent a drop in breakdown voltage.
That is, in order to further increase the insulation creepage distance AB, the positions of the metallized layer 4 and the solder layer 5 are moved further toward the center of the ceramic plate 3 than in FIG. If this becomes long, voids may be generated during resin molding, leading to a decrease in pressure resistance, but this can be prevented by increasing the radius of curvature of the portion 6a.

この構造を採用することで、セラミツク板３の
寸法を大きくしたりすることなく、かつ規格等で
定められた金属端子間距離等を変更することな
く、絶縁沿面距離を増大させることができ、半導
体装置の絶縁耐力を大きくすることができる。 By adopting this structure, the insulation creepage distance can be increased without increasing the dimensions of the ceramic plate 3 and without changing the distance between metal terminals specified by standards, etc. The dielectric strength of the device can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の絶縁型半導体装置の要部断面
図、第２図は本発明の一実施例の要部断面図であ
る。 １……金属放熱基板、２，５……半田層、３…
…セラミツク板、４……メタライズ層、６……金
属端子、７……樹脂。 FIG. 1 is a sectional view of a main part of a conventional insulated semiconductor device, and FIG. 2 is a sectional view of a main part of an embodiment of the present invention. 1... Metal heat dissipation board, 2, 5... Solder layer, 3...
...ceramic board, 4...metalized layer, 6...metal terminal, 7...resin.

Claims (1)

【特許請求の範囲】[Claims] １ 金属放熱基板と、金属放熱基板上に載置接着
された電気絶縁性を有するセラミツク板と、セラ
ミツク板上に載置接着された半導体基体と、全体
としてＬ字形を有し、Ｌ字形の底辺部がセラミツ
ク板上にメタライズ層及び半田層を介して載置接
着され、Ｌ字形の脚部がセラミツク板の周辺側に
位置し、半導体基体の電極と電気的に接続され半
導体基板に電流を通電するための金属端子とを具
備するものにおいて、前記メタライズ層及び前記
半田層の周縁を前記金属端子の脚部位置より前記
セラミツク板の中央部側に位置せしめ、これによ
つて前記金属端子と前記金属放熱基板との間の絶
縁沿面距離を大きくしていることを特徴とする半
導体装置。1. A metal heat dissipation board, an electrically insulating ceramic board placed and bonded on the metal heat dissipation board, a semiconductor substrate placed and bonded on the ceramic board, and having an L-shape as a whole, with a base of the L-shape. The L-shaped legs are placed on the ceramic board through a metallized layer and a solder layer, and the L-shaped legs are located on the peripheral side of the ceramic board and are electrically connected to the electrodes of the semiconductor substrate to conduct current to the semiconductor substrate. In the device, the peripheral edges of the metallized layer and the solder layer are located closer to the center of the ceramic plate than the leg portions of the metal terminal, thereby making the metal terminal and the solder layer A semiconductor device characterized by increasing an insulation creepage distance between it and a metal heat dissipation substrate.
JP1697681A 1981-02-09 1981-02-09 Semiconductor device Granted JPS57132332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1697681A JPS57132332A (en) 1981-02-09 1981-02-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1697681A JPS57132332A (en) 1981-02-09 1981-02-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57132332A JPS57132332A (en) 1982-08-16
JPH0122987B2 true JPH0122987B2 (en) 1989-04-28

Family

ID=11931092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1697681A Granted JPS57132332A (en) 1981-02-09 1981-02-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57132332A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS562247B2 (en) * 1976-09-16 1981-01-19

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52130670U (en) * 1976-03-31 1977-10-04
JPS5758781Y2 (en) * 1977-12-26 1982-12-15
JPS6020936Y2 (en) * 1979-06-19 1985-06-22 三菱電機株式会社 semiconductor equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS562247B2 (en) * 1976-09-16 1981-01-19

Also Published As

Publication number Publication date
JPS57132332A (en) 1982-08-16

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