JPH01229520A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To obtain an arbitrary stable clock by separating a frequency dividing circuit to output a clock signal to be compared to be inputted to a phase comparator from a first frequency dividing circuit outputting the arbitrary clock signal. CONSTITUTION:A second dividing circuit 8 to output a clock signal (g) to be compared to be inputted to a phase comparator 2 is separated from a first dividing circuit 7 to output an arbitrary clock signal (f). Consequently, even when the first dividing circuit 7 contains an incidental circuit except a dividing circuit, it is not influenced by the action of the incidental circuit. Thus, the phase comparator does not compares phases wrongly, an oscillator 4 always oscillates a stable clock signal (e) and the arbitrary clock signal (f) can be stably supplied from an output terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock generation circuit including a phase-locked loop used to provide a lock necessary to operate a system such as a digital signal processing system. It is.

2. Description of the Related Art In recent years, as digital circuit technology has progressed, many clock generation circuits have come into use to operate them.

A conventional clock generation circuit will be explained based on FIG.

FIG. 2 is a block diagram of a conventional clock generation circuit.

In FIG. 2, 1 is a reference input terminal, and a reference input signal a inputted from this reference input terminal 1 and a compared clock signal to be described later are inputted to a phase comparator 2, and an output signal of the phase comparator 2 is inputted to the phase comparator 2. C is input to the low-pass filter 3.

The output signal d of the low-pass filter 3 is input to an oscillator 4, and the oscillator 4 is controlled by this output signal d to output a clock signal e. A frequency divider circuit 5 to which this clock signal e is input divides the clock signal e. The clock signal to be compared is outputted to the phase comparator 2 and also outputted to the output terminal 6.

Through the above refinement, the three oscillators 4 compare the phases of the reference input signal a and the compared clock signal, input the output signal C to the low-pass filter 3, and control the oscillator 4 by the output signal d of the low-pass filter 3. A clock signal e having a frequency N times that of the input signal a is oscillated, and this clock signal e is frequency-divided by 1/H in the frequency divider circuit 5 and output from the output terminal 6, and this signal is used as the compared clock signal. It is input to the phase comparator 2 as a signal. By repeating this, a clock signal that is in phase with the reference input signal a input from the reference input terminal 1 will continue to be generated.

In this way, the tarlock generation circuit can be constructed.

Problems to be Solved by the Invention However, in the conventional configuration described above, when the frequency dividing circuit 5 includes an auxiliary circuit other than the frequency dividing circuit, such as a circuit for resetting, when this auxiliary circuit operates, The tally clock signal output from the frequency dividing circuit 5 may not match the tally signal obtained by only dividing the clock signal e output from the oscillator 4, and the clock signal to be compared becomes an incorrect clock signal. In this case, the phase comparator 2 performs an incorrect phase comparison, and the output signal C of the phase comparator 2 incorrectly controls the oscillator 4. Therefore, the oscillator 4 oscillates an incorrect clock signal e, and the output signal C of the phase comparator 2 is output from the output terminal 6. There was a problem in that a predetermined clock signal could not be obtained.

SUMMARY OF THE INVENTION The present invention solves the above problems, and aims to provide a clock generation circuit that can supply a stable clock signal without errors.

Means for Solving the Problems In order to solve the above problems, the present invention provides a phase comparator, a low-pass filter that receives the output signal of the phase comparator, and an oscillator that is controlled by the output signal of the low-pass filter. a first frequency divider circuit that divides the output clock signal of the oscillator and outputs an arbitrary clock signal; and a first frequency divider circuit that divides the output clock signal of the oscillator and outputs an arbitrary clock signal; The second frequency dividing circuit outputs a comparison clock signal.

Effect With the above configuration, the first frequency dividing circuit includes an auxiliary circuit other than the frequency dividing circuit, such as a circuit for resetting, and this auxiliary circuit operates, and the output clock signal of the first frequency dividing circuit is
Even if it does not match the clock signal obtained by only dividing the output clock signal of the oscillator, the compared clock signal whose phase is compared with the reference input signal is frequency-divided by the second frequency dividing circuit and sent to the phase comparator. Since the phase comparator does not perform erroneous phase comparison, the oscillator always oscillates a stable clock signal, and the first frequency divider circuit outputs a stable tarok signal.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of a clock generation circuit showing an embodiment of the present invention, and the same components as those of the conventional example shown in FIG.

In FIG. 1, 7 is a first frequency dividing circuit, which divides the frequency of the clock signal C of the oscillator 4 and outputs an arbitrary clock signal f to the output terminal 6, which is the clock signal e of the oscillator 4.
is also input to the second frequency dividing circuit 8, which divides the frequency of the tarock signal e and outputs the compared clock signal g to the phase comparator 2.

Next, the operation of the clock generation circuit having the above configuration will be explained.

First, the phase comparator 2 compares the phases of the reference input signal a input from the reference input terminal 1 and the compared clock signal g frequency-divided by the second frequency dividing circuit 8, and outputs the output signal C of the phase comparator 2.
Next, the oscillation 84 is controlled by the output signal d of the low-pass filter 3, and the clock signal e output from the oscillator 4 is divided by the first frequency dividing circuit 7 and output from the output terminal 6. At the same time, the clock signal e output from the oscillator 4 is frequency-divided by the second frequency dividing circuit 8 and inputted to the phase comparator 2 as the compared clock signal g. By repeating this, a clock signal f having a phase with the reference input signal a inputted from the reference input terminal 1 can be obtained from the output terminal 6.

In this way, by separating the second frequency divider circuit 8 that outputs the compared clock signal g input to the phase comparator 2 and the first frequency divider circuit 7 that outputs an arbitrary clock signal f,
Even if an auxiliary circuit other than the frequency divider circuit is included in the first frequency divider circuit 7, the operation of this auxiliary circuit will not affect the operation of the auxiliary circuit, so that the phases will not be erroneously compared in the phase comparator 2. , the always stable clock signal e is oscillated by the oscillator 4, and the arbitrary clock signal f is stably output from the output terminal 6.
It is possible to supply more.

Effects of the Invention As described above, according to the present invention, by separating the frequency dividing circuit that outputs the compared clock signal input to the phase comparator from the first frequency dividing circuit that outputs an arbitrary clock signal, Even if ancillary circuits other than the frequency divider circuit in the first frequency divider circuit operate, a stable compared clock signal is output from the second frequency divider circuit, and the oscillator can oscillate a stable clock. It is possible to provide an excellent clock generation circuit that can obtain a stable arbitrary clock signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clock generation circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional clock generation circuit. 1... Reference input terminal, 2... Phase comparator, 3...
Low pass filter, 4... Oscillator, 6... Output terminal, 7... First frequency dividing circuit, 8... Second frequency dividing circuit,
a...Reference input signal, C...Phase ratio? 2 output signal, d: output signal of low-pass filter, e: clock signal of oscillator, f: (output) clock signal, g: clock signal to be compared. Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A phase comparator, a low-pass filter that receives the output signal of the phase comparator, an oscillator controlled by the output signal of the low-pass filter, and an arbitrary clock signal obtained by dividing the output clock signal of the oscillator. and a second frequency dividing circuit that divides the output clock signal of the oscillator and outputs a compared clock signal whose phase is compared with a reference input signal in the phase comparator. clock generation circuit.