JPH04296917A - System clock generating circuit - Google Patents

Abstract

PURPOSE:To obtain a system clock generating circuit where it is unnecessary to raise the frequency of an external clock at the time of the rise of the frequency of a system clock. CONSTITUTION:Inverting amplifiers 11 to 14 connected in odd columns cascade connection constitute a ring oscillator 10, and control inputs 111, 121, 131, and 141 to control the delay times of inverting amplifiers 11 to 14 are provided to control the oscillation frequency. A phase comparator 20 to which the output of the ring oscillator 10 and the external clock are inputted, an LPF 30, and the ring oscillator 10 constitute a PLL, and a prescribed output of inverting amplifiers 11 to 14 of the ring oscillator 10 is obtained as the clock output.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system clock generation circuit used in microcomputers and the like.

0002

2. Description of the Related Art Conventionally, a system clock generation circuit for a microcomputer or the like has been configured as shown in FIG. In FIG. 3, 22 is an external clock, 40 is a frequency dividing circuit, and 50 is a decoder.
The code circuits 51 to 54 are their output clocks.

In this configuration, as shown in FIG. 4, output clocks 51 to 54, which are shifted by one clock from the external clock 22, are obtained from the external clock 22 by a frequency dividing circuit 40 and a decoding circuit 50. The output clocks 51 to 54 are used to operate a system such as a microcomputer.

0004

In the conventional system clock generation circuit described above, as the frequency of the system clock increases, the frequency of the external clock 22 inputted from the outside becomes extremely high. For example, in a system where one cycle is eight clocks, when the system clock is 10 MHz, the external clock 22 needs to be eight times that frequency, that is, 80 MHz.

As described above, in the conventional system clock generation circuit, when the system clock is increased, the external clock 22 becomes extremely high, so there is a problem in that the external clock 22 becomes a cause of unnecessary radiation.

The present invention has been made in view of the drawbacks of the conventional ones, and provides a system clock generation circuit that does not require increasing the external clock frequency even if the system clock frequency increases. The purpose is to

[0007]

[Means for Solving the Problems] A system clock generation circuit according to the present invention configures a ring oscillator by connecting the inputs and outputs of inverting amplifiers connected in odd number stages in series,
By providing a control input to control the delay time of each inverting amplifier, the oscillation frequency of the ring oscillator is controlled by the external input, and the ring oscillator, phase comparator, and low-pass filter perform a PLL (Phase L).
(locked Loop), extract the necessary clock from the output of each inverting amplifier of the ring oscillator,
This is the system clock.

[0008]

[Operation] The system clock generation circuit according to the present invention is
It is only necessary to apply an external clock with the same frequency as the system clock cycle, and a high frequency clock is not required, so unnecessary radiation is significantly improved.

[0009]

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 11 to 14 are inverting amplifiers (inverters), 10 is a ring oscillator in which an odd number of stages of the inverting amplifiers 11 to 14 are connected in series, 20 is a phase comparator, and 30 is a rotor.
A pass filter (hereinafter referred to as LPF), 21 is the output of the ring oscillator 10, 22 is an external clock, and 23 is an error signal output.

Each delay of the inverting amplifiers 11 to 14 is tr
If the number of stages of the inverting amplifiers 11 to 14 is n, the oscillation frequency f0 of the ring oscillator 10 is (n×tr
) becomes -1. This oscillation frequency f0 and external clock 2
2 and a phase comparator 20, and the error signal output 23 is sent to the LPF 30, where the high frequency component of the error signal is removed. The output signal 31 is sent to the inverting amplifier 11~
Control inputs 111 and 12 that control the delay tr of 14
1, ..., 141. The system operates so that the external clock 22 and the output 21 of the ring oscillator 10 are synchronized. Figure 2 shows the synchronized state. external clock 2
2, the output 21 of the ring oscillator 10 is synchronized with the output 21 of the ring oscillator 10, and the outputs 112, 122, . used for

[0011] Therefore, the external clock 22 may have the same period as the system clock, and does not require a high frequency as in the conventional example. Further, by forming the system clock generation circuit of FIG. 1 on the same chip, unnecessary radiation can be further reduced.

In the above embodiment, an odd number of cascaded ring oscillators 10 are used as the VCO, but the same effect can be obtained as long as the VCO can extract a plurality of signals with phase differences.

[0013]

[Effects of the Invention] As explained above, the present invention uses a ring oscillator, a phase comparator, and an LPF to form a so-called PLL and synchronizes it with an external clock to obtain a system clock. It can be the same as the period, eliminating the need for high frequencies, and has the effect of significantly reducing unnecessary radiation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a system clock generation circuit of the present invention.

FIG. 2 is a diagram showing the timing of each part of the system clock generation circuit shown in FIG. 1;

FIG. 3 is a block diagram showing an example of a conventional system clock generation circuit.

FIG. 4 is a diagram showing the timing of each part of the system clock generation circuit shown in FIG. 3;

[Explanation of symbols]

10 Ring oscillator 11 Inverting amplifier 12 Inverting amplifier 13 Inverting amplifier 14 Inverting amplifier 20 Phase comparator 21 Ring oscillator output 22 External clock 23 Error signal output 30 LPF 111 Control input 112 Output 121 Control input 122 Output 131 Control input 132 Output 141 Control input 142 Output

Claims (1)

[Claims] Claim 1: A ring oscillator in which an odd number of stages of inverting amplifiers whose delay time changes depending on the control input are connected in series, and the output of the final stage is connected to the input of the first stage, the output of this ring oscillator and an external clock are input. The output of the low-pass filter is applied to the control input of the inverting amplifier of the ring oscillator, and the output of the low-pass filter is applied to the control input of the inverting amplifier of the ring oscillator. A system clock generation circuit characterized in that an output of an amplifier is used as a clock output.