JPH01228223A - Parallel comparison type analog/digital converter - Google Patents
Parallel comparison type analog/digital converterInfo
- Publication number
- JPH01228223A JPH01228223A JP63054046A JP5404688A JPH01228223A JP H01228223 A JPH01228223 A JP H01228223A JP 63054046 A JP63054046 A JP 63054046A JP 5404688 A JP5404688 A JP 5404688A JP H01228223 A JPH01228223 A JP H01228223A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- reference voltage
- comparators
- divided
- nodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/367—Non-linear conversion
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は、例えば、高速変換が要求される画像処理用
のアナログ・ディジタル変換器（以下、ＡＤＣと略称す
る）として用いて好適な並列比較型ＡＤＣに係り、特に
、その比較器の個数を大幅に減少させることができる並
列比較型ＡＤＣに関するものである。DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" The present invention is suitable for use as an analog-to-digital converter (hereinafter abbreviated as ADC) for image processing that requires high-speed conversion, and is suitable for parallel comparison. The present invention relates to a parallel comparison type ADC, and particularly to a parallel comparison type ADC that can significantly reduce the number of comparators.
「従来の技術」
従来、高速変換が可能なｎビット出力の並列比較型ＡＤ
Ｃは、第２図に示すように構成されていた。この図にお
いて、５は抵抗ｍ Ｒ／２とＲの２種類の抵抗６と７を
複数個直列接続してなる区分基準電圧発生回路であり、
その両端の電圧ＴａとＴｂには、正側基準電圧ＶＲＨと
負側基準電圧ＶＲＬが各々印加され、その中央の電圧Ｔ
ｃには、中心電圧ＶＲＭが印加される。この中心電圧Ｖ
ＲＭは、正側基準電圧ＶＲ■と負側基準電圧ＶＲＬとの
中間電位であり、交流的な零電位に相当する。そして、
区分基準電圧発生回路５の各電圧Ｔａ、Ｔｂ間は、抵抗
６．７．・・・によって２ｎ等分割されており、各抵抗
６，７．・・・の接続点、すなわちｍ’（＝２”−１）
個の基準電圧節点Ｐ、＝Ｐｍ’からは、一定の電圧差を
有するｍ′種類の区分基準電圧■、〜ｖｍ’が各々出力
される。これらの各区分基準電圧Ｖ１〜Ｖｍ’は、比較
５ Ｃ＋〜Ｃｍ”の一方の入力端に各々供給され、また
各比較器０１〜Ｃｍ’の他方の入力端には、入力電圧Ｔ
ｉｎを介して被変換対象となるアナログ入力電圧Ｖｉｎ
が各々供給される。これにより、全ての比較器Ｃ、−Ｃ
ｍ’は、アナログ入力電圧Ｖｉｎと各区分基準電圧■１
〜Ｖｍ’とを各々同時に比較し、その比較結果をエンコ
ーダ８へ供給する。このエンコーダ８は、比較器Ｃ３〜
Ｃｍ’から出力されるｍ°ビットのビットパターンを、
ｎビットのバイナリコードに変換する。以上により、入
力電圧Ｔｉｎに入力されたアナログ入力電圧Ｖｉｎが、
高速でｎビットのディジタル・データに変換され、出力
電圧Ｔｏｕｔから出力される。"Conventional technology" Conventional parallel comparison type AD with n-bit output capable of high-speed conversion
C was constructed as shown in FIG. In this figure, 5 is a divisional reference voltage generation circuit formed by connecting a plurality of two types of resistors 6 and 7 in series, resistors mR/2 and R.
A positive reference voltage VRH and a negative reference voltage VRL are applied to the voltages Ta and Tb at both ends, respectively, and the voltage T at the center thereof is
A center voltage VRM is applied to c. This center voltage V
RM is an intermediate potential between the positive reference voltage VR■ and the negative reference voltage VRL, and corresponds to an AC zero potential. and,
Resistors 6, 7, . . . , each resistor is divided into 2n equal parts by 6, 7, . The connection point of..., i.e. m'(=2"-1)
From the reference voltage nodes P,=Pm', m' types of segmented reference voltages 1, .about.vm' having a constant voltage difference are output, respectively. These divided reference voltages V1 to Vm' are each supplied to one input terminal of the comparators 5 C+ to Cm'', and the input voltage T is supplied to the other input terminal of each comparator 01 to Cm'.
Analog input voltage Vin to be converted via in
are supplied respectively. This allows all comparators C, -C
m' is the analog input voltage Vin and each division reference voltage ■1
.about.Vm' are simultaneously compared, and the comparison results are supplied to the encoder 8. This encoder 8 has comparators C3 to
The bit pattern of m° bits output from Cm' is
Convert to n-bit binary code. As a result of the above, the analog input voltage Vin input to the input voltage Tin is
It is converted into n-bit digital data at high speed and output from the output voltage Tout.
「発明が解決しようとする課題」
ところで、上述した従来のｎビット出力の並列比較型Ａ
ＤＣにおいては、正側基Ｑ電圧ＶＲＩ＋と負側基準電圧
ＶＲＬとの間を２ｎ等分割して区分基準電圧Ｖ、〜Ｖｍ
’を設定していたので、これらの各区分基準電圧Ｖ１〜
Ｖｍ’と同数の２ｎ−１個の比較器が必要であり、出力
ビツト数ｎを増加させようとすると、膨大な数の高精度
比較器を必要とし、またエンコーダ８の構成も非常に複
雑となり、これが、集積化等、製造コストの低減を阻害
する要因となっていた。"Problems to be Solved by the Invention" By the way, the above-mentioned conventional n-bit output parallel comparison type A
In DC, the positive side group Q voltage VRI+ and the negative side reference voltage VRL are equally divided into 2n to create divided reference voltages V, ~Vm.
', so each of these divisional reference voltages V1~
2n-1 comparators, the same number as Vm', are required, and if we try to increase the number of output bits n, we will need an enormous number of high-precision comparators, and the configuration of the encoder 8 will also become extremely complex. This has been a factor hindering reductions in manufacturing costs such as integration.
この発明は、上述した事情に鑑みてなされたもので、比
較器の個数を大幅に減少させることができる並列比較型
ＡＤＣを提供することを目的としている。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a parallel comparison type ADC that can significantly reduce the number of comparators.
「課題を解決するための手段」
この発明は、基準電圧全体を指数スケールで分割すると
共に分割された各基準電圧を各々等分割する電圧節点を
有し、前記各電圧節点において得られる区分基Ｑ電圧を
各々出力する区分基準電圧発生回路と、変換対象として
供給されるアナログ入力電圧と前記各区分基準電圧とを
各々比較する比較器とを具備することを特徴としている
。"Means for Solving the Problems" The present invention has voltage nodes that divide the entire reference voltage on an exponential scale and equally divide each divided reference voltage, and a dividing group Q obtained at each voltage node. It is characterized by comprising a sectional reference voltage generation circuit that outputs each voltage, and a comparator that compares the analog input voltage supplied as a conversion target with each of the sectional reference voltages.
「作用」
基準電圧全体を、従来のように単に等分割するのではな
く、指数スケールで分割し、さらに分割された各基準電
圧を各々等分割し、これにより各区分基準電圧を得るよ
うにしたので、比較器の個数を従来と比較して大幅に減
少させることができる。"Operation" The entire reference voltage is not simply divided equally as in the past, but is divided on an exponential scale, and each divided reference voltage is further divided equally, thereby obtaining each divisional reference voltage. Therefore, the number of comparators can be significantly reduced compared to the conventional method.
「実施例」
以下、図面を参照し、この発明の実施例について説明す
る。"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図はこの発明の一実施例の構成を示す図である。こ
の図において、ｌはＲ−２Ｒラダー抵抗網によって構成
される区分基準電圧発生回路であり、抵抗値Ｒ／２ ’
（ｉは整数）の抵抗２ａを２１個直列接続してなる抵
抗群２と、抵抗値２Ｒの抵抗３とを複数個組み合わせろ
ことによって構成されている。この場合、Ｒ−２Ｒラダ
ー抵抗網によって、電圧ＴａとＴｃに各々印加される正
側基準電圧ＶＲＩ＋と中心電圧Ｖ ＲＭ、および電圧Ｔ
ｂとＴｃに各々印加される負側基準電圧ＶＲＬと中心電
圧ＶＲＭが、２ｊ −（ｊ＝ ｎ −１，ｎ −２，
・・・、ｉ）の指数スケールで分割されており、また各
抵抗群２によって、分割された各基学電圧が各々２１等
分割されている。これにより、上記区分基準電圧発生回
路ｌにおける電圧節点Ｐ Ｉ−Ｐ ’ｍの数ｍは、２
” ｘ （ｎ −ｉ）となる。FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In this figure, l is a segmented reference voltage generation circuit composed of an R-2R ladder resistance network, with a resistance value R/2'
It is constructed by combining a resistor group 2 formed by connecting 21 resistors 2a (i is an integer) in series, and a plurality of resistors 3 having a resistance value of 2R. In this case, the positive side reference voltage VRI+, the center voltage VRM, and the voltage T
The negative side reference voltage VRL and center voltage VRM applied to b and Tc, respectively, are 2j − (j= n −1, n −2,
..., i), and each divided fundamental voltage is divided into 21 equal parts by each resistor group 2. As a result, the number m of voltage nodes P I-P'm in the segmented reference voltage generation circuit l is 2
” x (n − i).
そして、各電圧節点Ｐ１〜Ｐｍから各々出力されたｍ種
類の区分基準電圧Ｖ１〜Ｖｍは、比較器０１〜Ｃｍの一
方の入力端に各々供給され、これにより、全ての比較器
０１〜Ｃｍが、入力電圧Ｔｉｎを介して供給されるアナ
ログ入力電圧Ｖｉｎと各区分基準電圧■１〜Ｖｍとを各
々同時に比較し、その比較結果ヲエンコーダ４へ供給す
る。このエンコーダ４は、比較器Ｃ１〜Ｃｍから出力さ
れるｍビットのビットパターンを、ｎビットのバイナリ
コードに変換し、これにより、入力電圧Ｔｉｎに入力さ
れたアナログ入力電圧Ｖｉｎが、高速でｎビットのディ
ジタル・データに変換され、出力電圧Ｔｏ、ｕｔから出
力される。Then, the m types of divided reference voltages V1 to Vm outputted from the respective voltage nodes P1 to Pm are respectively supplied to one input end of the comparators 01 to Cm, so that all the comparators 01 to Cm , the analog input voltage Vin supplied via the input voltage Tin and each of the divisional reference voltages 1 to Vm are simultaneously compared, and the comparison results are supplied to the encoder 4. This encoder 4 converts the m-bit bit pattern output from the comparators C1 to Cm into an n-bit binary code, and thereby converts the analog input voltage Vin input to the input voltage Tin into an n-bit binary code at high speed. is converted into digital data and output from output voltages To and ut.
ここで、ｎ＝９ビツトで、１＝４（２’＝１６分割）と
した場合における基準電圧節点Ｐ、〜Ｐｍおよび比較器
０１〜Ｃｍの個数ｍについて説明する。Here, the reference voltage nodes P, .about.Pm and the number m of comparators 01.about.Cm in the case where n=9 bits and 1=4 (2'=16 division) will be explained.
まず、９ビツトの２進数では、０〜２．”ｌまでのアナ
ログ値が表現でき、正負の表現にすると、−２５６〜θ
〜＋２５５までのアナログ値が表現でき、また、正負の
アナログ値の内、一方のみを考えると、約２８−１・２
８のアナログ値が表現できることになる。First, in a 9-bit binary number, 0 to 2. Analog values up to l can be expressed, and when expressed as positive and negative, -256 to θ
Analog values up to +255 can be expressed, and if only one of the positive and negative analog values is considered, approximately 28-1.2
This means that 8 analog values can be expressed.
そして、上述した一実施例においては、正側基準電圧Ｖ
ＲＩ＋をアナログ値＋２ ’（−２”−’）に対応させ
、中心電圧ＶＲＭをアナログ値±０に対応させている。In the embodiment described above, the positive side reference voltage V
RI+ corresponds to an analog value +2'(-2''-'), and center voltage VRM corresponds to an analog value ±0.
また、正側基準電圧ＶＲＩ＋をアナログ値２６に対応さ
せると共に、中心電圧ＶＲＭを基準としてアナログ値２
７，２８，２５．２４（−２１）に対応する指数スケー
ルで、電圧節点を設け、さらに、上記各節点間を、＋６
（＝２１＝２’）等分割している。すると、正側での電
圧節点数は、２ ’Ｘ （ｎ −１）−８０となり、正
負両側では、２ ｉ ＋ ｌ Ｘ （ロー１）−１６０
となる。したがって、ｎ＝９ビツトで、ｍ＝４の場合、
括■電圧節点Ｐ１〜Ｐｍおよび比較器ＣＩ〜Ｃｍの個数
ｍは、！６０となる。In addition, the positive side reference voltage VRI+ is made to correspond to the analog value 26, and the analog value 2 is made to correspond to the center voltage VRM.
Voltage nodes are provided on an exponential scale corresponding to 7, 28, 25.24 (-21), and +6
(=21=2') Equally divided. Then, the number of voltage nodes on the positive side becomes 2'X (n -1) - 80, and on both the positive and negative sides, 2 i + l
becomes. Therefore, when n=9 bits and m=4,
Bracket ■The number m of voltage nodes P1 to Pm and comparators CI to Cm is! It will be 60.
同様にして、
ｎ＝９ピントで、ｍ＝５の場合、ｍ＝ ２５６個ｎ＝９
ヒツトで、ｍ＝６の場合、ｍ＝ ３８４個となる。Similarly, if n=9 focus and m=5, m=256 pieces n=9
In humans, if m = 6, then m = 384.
これに対し、従来の９ビツト出力の並列比較型ＡＤＣに
おいては、２’−１＝５１１個の比較器を必要とした訳
であるから、上述した実施例によれば、比較器のｇ数を
大幅に削減することができることになる。On the other hand, in the conventional 9-bit output parallel comparison type ADC, 2'-1=511 comparators are required, so according to the above embodiment, the number of comparators is This will result in a significant reduction.
「発明の効果」
以上説明したように、この発明によれば、基■電圧全体
を、従来のように単に等分割するのではなく、指数スケ
ールで分割し、さらに分割された各基亭電圧を各々等分
割し、これにより各区分基準電圧を得るようにしたので
、比較器の個数を従来と比較して大幅に減少させること
ができ、この結果、小規模の回路構成で出力ビツト数を
増加させることができ、集積度を向上させて製造コスト
の低減を図ることが可能となるという効果が得られ、特
に、指数関数的な特性を有する人間の視感度に関係する
映像信号を取り扱う画像処理回路等に用いて好適である
。"Effects of the Invention" As explained above, according to the present invention, the entire base voltage is not simply divided equally as in the past, but is divided on an exponential scale, and each divided base voltage is Since each section is divided equally and a reference voltage is obtained for each section, the number of comparators can be significantly reduced compared to the conventional method, and as a result, the number of output bits can be increased with a small-scale circuit configuration. This has the effect of improving the degree of integration and reducing manufacturing costs, especially for image processing that handles video signals related to human visibility, which has exponential characteristics. Suitable for use in circuits, etc.
第１図はこの発明の一実施例の構成を示すブロック図、
第２図は従来の並列比較型ＡＤＣの構成を示すブロック
図である。
ｌ・・・・・区分基準電圧発生回路、
２ ・・・抵抗群（抵抗値Ｒ）、
２ａ・・・・・・抵抗（抵抗値Ｒ／２１）、３・ ・・
抵抗（抵抗値２Ｒ）、
Ｐ１〜Ｐｍ・・・・電圧節点、
■、〜Ｖｍ・・・・・・区分基準電圧、Ｃ５〜Ｃｍ・・
比較器。
出願人 ヤ マ ハ 株式会社FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of a conventional parallel comparison type ADC. l...Division reference voltage generation circuit, 2...Resistor group (resistance value R), 2a...Resistor (resistance value R/21), 3...
Resistance (resistance value 2R), P1~Pm... Voltage node, ■, ~Vm... Division reference voltage, C5~Cm...
Comparator. Applicant Yamaha Co., Ltd.
Claims (1)
た各基準電圧を各々等分割する電圧節点を有し、前記各
電圧節点において得られる区分基準電圧を各々出力する
区分基準電圧発生回路と、変換対象として供給されるア
ナログ入力電圧と前記各区分基準電圧とを各々比較する
比較器と、を具備することを特徴とする並列比較型アナ
ログ・ディジタル変換器。A segmented reference voltage generation circuit that divides the entire reference voltage on an exponential scale and has voltage nodes that equally divide each of the divided reference voltages, and outputs segmented reference voltages obtained at each of the voltage nodes, and a conversion target. 1. A parallel comparison type analog-to-digital converter, comprising: a comparator that compares an analog input voltage supplied as an analog input voltage with each of the divided reference voltages.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63054046A JPH0612879B2 (en) | 1988-03-08 | 1988-03-08 | Parallel comparison type analog-digital converter |
| SG1996004578A SG47822A1 (en) | 1988-03-08 | 1989-03-06 | Parallel analog-to-digital converter |
| DE68926719T DE68926719T2 (en) | 1988-03-08 | 1989-03-06 | Parallel analog-digital converter |
| EP89103933A EP0332118B1 (en) | 1988-03-08 | 1989-03-06 | Parallel analog-to-digital converter |
| US07/319,621 US4990917A (en) | 1988-03-08 | 1989-03-07 | Parallel analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63054046A JPH0612879B2 (en) | 1988-03-08 | 1988-03-08 | Parallel comparison type analog-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01228223A true JPH01228223A (en) | 1989-09-12 |
| JPH0612879B2 JPH0612879B2 (en) | 1994-02-16 |
Family
ID=12959661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63054046A Expired - Fee Related JPH0612879B2 (en) | 1988-03-08 | 1988-03-08 | Parallel comparison type analog-digital converter |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4990917A (en) |
| EP (1) | EP0332118B1 (en) |
| JP (1) | JPH0612879B2 (en) |
| DE (1) | DE68926719T2 (en) |
| SG (1) | SG47822A1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4983973A (en) * | 1989-05-22 | 1991-01-08 | Brooktree Corporation | Non-linear analog-to-digital converter |
| JPH042220A (en) * | 1990-04-18 | 1992-01-07 | Mitsubishi Electric Corp | Reference voltage generating circuit |
| US5059978A (en) * | 1990-12-20 | 1991-10-22 | Vlsi Technology, Inc. | Resistor-string digital to analog converters with auxiliary coarse ladders |
| JP3372555B2 (en) * | 1991-06-21 | 2003-02-04 | キヤノン株式会社 | Photoelectric conversion device |
| FR2691026B1 (en) * | 1992-05-07 | 1997-01-03 | Thomson Csf | ANALOG-TO-DIGITAL CONVERTER AND SERVO LOOP USING SUCH A CONVERTER. |
| US5610604A (en) * | 1994-12-07 | 1997-03-11 | Panasonic Technologies, Inc. | Analog to digital converter providing varying digital resolution |
| US5659313A (en) * | 1995-03-31 | 1997-08-19 | Panasonic Technologies, Inc. | System and method for reducing noise during analog to digital conversion |
| KR0174499B1 (en) * | 1995-10-13 | 1999-04-01 | 김광호 | Analog Digital Converter Compensates Input Bias Current of Comparator |
| US5815106A (en) * | 1996-10-09 | 1998-09-29 | International Business Machines Corporation | Split flash analog to digital converter differential driver |
| US5736952A (en) * | 1996-10-09 | 1998-04-07 | International Business Machines Corporation | Current boost for differential flash analog to digital converter driver |
| US6462693B1 (en) * | 2001-06-06 | 2002-10-08 | Agilent Technologies, Inc. | Analog to digital signal conversion method and apparatus |
| US6429799B1 (en) | 2001-07-14 | 2002-08-06 | Agilent Technologies, Inc. | Method and apparatus for analog to digital conversion using time-varying reference signal |
| US6717540B1 (en) * | 2002-10-10 | 2004-04-06 | Agilent Technologies, Inc. | Signal preconditioning for analog-to-digital conversion with timestamps |
| US7271756B2 (en) | 2002-12-04 | 2007-09-18 | Nxp B.V. | Non-linear distribution of voltage steps in flash-type A/D converters |
| JP2007135099A (en) * | 2005-11-11 | 2007-05-31 | Toshiba Corp | Ad converter and image display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1593017A (en) * | 1968-09-11 | 1970-05-25 | ||
| US3688221A (en) * | 1971-03-02 | 1972-08-29 | Krone Gmbh | Two-stage pcm coder with compression characteristic |
| FR2155877B1 (en) * | 1971-10-13 | 1974-05-31 | Anvar | |
| US3736586A (en) * | 1972-03-22 | 1973-05-29 | Sfim | Analogue-to-digital voltage converter |
| JPS58106915A (en) * | 1981-12-21 | 1983-06-25 | Sony Corp | A/d converter |
-
1988
- 1988-03-08 JP JP63054046A patent/JPH0612879B2/en not_active Expired - Fee Related
-
1989
- 1989-03-06 EP EP89103933A patent/EP0332118B1/en not_active Expired - Lifetime
- 1989-03-06 DE DE68926719T patent/DE68926719T2/en not_active Expired - Fee Related
- 1989-03-06 SG SG1996004578A patent/SG47822A1/en unknown
- 1989-03-07 US US07/319,621 patent/US4990917A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0332118A2 (en) | 1989-09-13 |
| SG47822A1 (en) | 1998-04-17 |
| DE68926719T2 (en) | 1996-10-31 |
| EP0332118B1 (en) | 1996-06-26 |
| JPH0612879B2 (en) | 1994-02-16 |
| US4990917A (en) | 1991-02-05 |
| DE68926719D1 (en) | 1996-08-01 |
| EP0332118A3 (en) | 1992-10-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |