JPS63107233A - Analog and digital converting circuit - Google Patents

Abstract

PURPOSE:To perform digital conversion by a very small number of comparing means as compared with resolution by using digital outputs obtained from plural cascaded unit quantizing circuits as high-order digit bits successively. CONSTITUTION:An initial-stage unit quantizing circuit ADC1 quantizes an analog input voltage in eight gradations for a full-scale voltage VFS to obtain digital signals D0 - D2 of three bits by conversion, and a trailing-stage unit quantizing circuit ADC2 uses comparison reference potentials right before and after the analog input voltage level among comparison reference potentials generated by a resistance voltage dividing circuit DR1 included in the initial-stage unit quantizing circuit ADC1 as a relative full scale and quantizes the analog input voltage in four gradations to obtain digital signals D3 and D4 of two bits by conversion. The digital signals D3 and D4 constitute low-order digit bits and thus digital conversion to five bits is performed by 12 comparing circuits.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog-to-digital conversion circuit, and more particularly, to a parallel comparison type analog-to-digital conversion circuit, and for example, the present invention relates to an analog-to-digital conversion circuit and a parallel comparison type analog-to-digital conversion circuit. The present invention relates to a technique that is effective when applied to a signal reading/converting section of a facsimile machine.

[Prior art]

The parallel comparison type analog-to-digital conversion circuit was developed in 1932.
As described in rLsI handbook J'P636 published by Ohmsha on November 30, 1999, comparators are arranged in parallel in the number corresponding to the quantization level, and the analog input voltage and each of these quantization levels are connected in parallel. A digital output is obtained depending on which level the comparator operates.

[Problem that the invention seeks to solve]

By the way, parallel comparison type analog-to-digital conversion circuits are capable of extremely high-speed conversion operations compared to successive approximation type analog-to-digital conversion circuits due to the nature of parallel conversion, but the number of quantization levels (number of gradations) Since a corresponding number of comparators are required, there is a problem in that multi-gradation or high resolution is restricted. That is, in order to increase the number of gradations or increase the resolution, the number of comparators must be significantly increased, which is a constraint from the perspective of space factor, and power consumption increases in proportion to the number of comparators. It ends up. Therefore, according to the inventor's study, when forming an image by realizing intermediate gradation expression or colorization in an image forming apparatus such as a facsimile or a copying machine, it is necessary to read the original information etc. in an analog manner. It has been revealed that when improving the resolution when digitizing data, it becomes difficult to perform high-speed conversion using a parallel comparison type analog-to-digital conversion circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog-to-digital conversion circuit that can convert analog signals into digital signals in parallel using a much smaller number of comparing means than the number of gradations or resolution. be.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a voltage dividing means that divides and outputs the applied voltage at predetermined intervals, a plurality of comparing means that compares each divided voltage output from the voltage dividing means and an analog input signal in parallel, and
A plurality of unit quantization circuits consisting of binary conversion means that obtain digital outputs based on the comparison results of the comparison means convert analog input signals from among the divided voltages formed by the voltage division means included in the unit quantization circuit in the previous stage. The voltage output means outputs the divided voltages immediately before and after the level to the voltage dividing means included in the next stage unit quantization circuit based on the comparison result by the comparison means included in the previous stage unit quantization circuit. They are connected in a subordinate manner.

[For production]

According to the above-mentioned means, the digital output obtained from each of a plurality of unit quantization circuits connected in series is sequentially set as the upper bit, so that the product of the respective numbers of comparison means included in each unit quantization circuit is calculated. The number of tones equal to is obtained,
This achieves parallel analog signal digital conversion using a much smaller number of comparing means than the tltY scale or resolution.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of an analog-to-digital conversion circuit according to the present invention. The analog-to-digital conversion circuit shown in the figure is used in facsimile machines, copying machines, etc., to convert an analog signal, which is a photoelectric conversion signal obtained by optically scanning a document, into a digital signal with a predetermined resolution or number of gradations, although there is no particular limitation. It is something that converts.

The analog-to-digital conversion circuit shown in Figure 1 has a resolution of 5 bits, in other words, it converts an analog input signal into 3 bits.
It performs digitization in two gradations, and is composed of two-stage unit quantization circuits ADC1 and ADC2, although this is not particularly limited.

The first-stage unit quantization circuit AI)C1 divides the full-scale voltage VFS supplied from the input terminals VHI and VLI into approximately 8 equal parts to form a standard judgment level for quantization (hereinafter also simply referred to as quantization level). A resistor voltage divider circuit DR1 that divides the resistor voltage in increments of , and eight comparison circuits C0M1 to C0M1 that compare in parallel each divided voltage as a quantization level output from the resistor voltage divider circuit DRI with the analog input voltage Vi. C0M8 and their comparison circuits C0M1 to C0M
The binary conversion circuit BCI obtains a digital output based on the comparison result of 8.

When an analog input voltage Vj is supplied to the non-inverting input terminals of the comparison circuits C0M1 to C0M8, all comparison circuits to which a comparison reference potential as a quantization level lower than that voltage Vi is supplied output high-level signals. At the same time, all comparison circuits on the opposite side output low level signals. The above-mentioned binary conversion circuit BCI is configured such that its analog input voltage Vi is controlled by a pinary counter shown in the figure, which uses the outputs of the high-level output group and the low-level output group in the comparison circuits C0M1 to C0M8 as carry signals, although this is not particularly limited. is a 3-bit digital signal.

to D2. Furthermore, the binary conversion circuit BC1 is not limited to the configuration using a binary counter, but the boundary between the high level output group and the low level output group in the comparison circuits COMI to C0M8 is determined by a gate circuit (not shown), and based on the boundary, An encoder (not shown) at the latter stage converts the analog input voltage Vi into a 3-bit digital signal. It is also possible to configure the conversion to D2.

The next stage unit quantization circuit ADC2 has input terminals VH2 and VH2 to form a quantization level as a comparison reference potential.
A resistive voltage divider circuit DR2 that divides the input voltage supplied from L2 into four equal parts, and the resistive voltage divider circuit DR2.
Four comparison circuits C0M9 to C0M12 that compare in parallel each divided voltage as a quantization level output from the analog input voltage Vi, and these comparison circuits C0M
9 to C0M12, which obtains a digital output based on the comparison results. When the analog input voltage Vi is supplied to the non-inverting input terminals of the comparison circuits C0M9 to C0M12, all the comparison circuits to which the comparison reference potential as a quantization level lower than the voltage Vi is supplied output high-level signals. At the same time, all comparison circuits on the opposite side output low level signals. The binary conversion circuit BC2 is the binary conversion circuit BC2.
Similarly to I, these comparison circuits C0M9 to C0M1
The analog input voltage Vi is converted into 2-bit digital signals D3 and D4 based on the outputs of the high level output group and the low level output group at 2.

The above-mentioned two-stage unit quantization circuits ADC1 and ADC2 are the resistor voltage divider circuit D included in the previous-stage unit quantization circuit ADC1.
Among the divided voltages as comparison reference voltages formed by RI, the divided voltages before and after the analog input voltage Vi are
Based on the comparison results by the comparator circuits COMI to C0M8, they are cascade-connected via a switch circuit SW as a voltage output means that outputs to the input terminal of a resistor voltage divider circuit DR2 included in the next stage unit quantization circuit ADC2.

The switch circuit SW is an N-channel MO8FETQH as a switch element, which is coupled to the inverting input terminals of the comparison circuits COMI to C0M7 and one input terminal VH2 of the resistor voltage divider circuit DR2, respectively, although it is not particularly limited.
It has N-channel type MO8FETs QL2 to QL8 as switching elements connected to the inverting input terminals of the comparison circuits C0M2 to C0M8 and the other input terminal VL2 of the resistor voltage divider circuit DR2, respectively.

The gate electrodes of the above MO8FETQHI to QH7 and the MO8FETQHI to QH7
The gate electrodes of the 8FETs QL2 to QL8 are coupled so that the inverting input terminal voltages of mutually adjacent comparison circuits can be selectively applied to the input terminals VH2 and VL2 of the resistor voltage divider circuit DR2. That is, the gate electrode of MO5FETQHI and the gate electrode of MOFETQL2 are coupled to each other in such a relationship that they are coupled to each other.

MO8F with gate electrodes connected to each other in this way
ETQH1 to QH7 and MO3FETQL2 to QL8
In order to selectively switch control the comparator circuit CO
Of MI to C0M8, there are 7 stages of 2-input exclusive circuits that receive the output signals of adjacent comparison circuits in parallel.
OR circuits EXORI to EXOR7 are provided, and these exclusive OR circuits EXORI to EXOR7
The output terminals of the respective MOSFET gates f
Combined with Fita. That is, the exclusive OR circuit EXORI (7) output terminal is connected to the gate electrodes of MO8FETQH1 and QL2. Such exclusive OR circuit EXOR
I to EXOR7 output a high level signal when the two outputs are set to high level and low level. Therefore, when the analog input voltage Vi is supplied to the non-inverting input terminals of the comparison circuits COMI to C0M8, all comparison circuits to which the comparison reference potential as a quantization level lower than that voltage Vi are supplied with high-level signals. At the same time, all comparison circuits on the opposite side output low level signals, but at that time, the exclusive OR circuit EX
ORI to EXOR7 are set to high level when they receive a signal output from a pair of comparison circuits located at the boundary between the high level output group and the low level output group in these comparison circuits COMI to C0M8. For example, when the analog input voltage Vi is between the potential of the node A and the potential of the node B of the resistive voltage divider circuit DRI, the comparator circuits C0M4 and C0M4 receive the potentials of the nodes A and B at their inverting input terminals as comparison reference potentials, respectively. The output signal of C0M5 is set to low level and high level, and the output signal of exclusive OR circuit EXOR5 to which these output signals are input is set to high level. As a result, MO8FETQH5 and MO8FETQL6 are controlled to be on, and the next The potentials of nodes A and B are supplied to the input terminals VH2 and VL2 of the resistive voltage divider circuit DR2 of the stage.

Therefore, in that case, the unit quantization circuit ADC2
further connects the potentials of nodes A and B to resistive voltage divider circuit DR2.
The analog input voltage Vi is quantized and converted into 2-bit digital signals D3 and D4 using the respective quantization levels obtained by dividing it into four equal parts as comparison reference potentials.

In this way, the unit quantization circuit ADI at the first stage quantizes the analog input voltage Vi in eight gradations with respect to the full-scale voltage VFS, converts it into 3-bit digital signals D0 to D2, and further converts it into 3-bit digital signals D0 to D2. The quantization circuit ADC2 is a resistor voltage divider circuit DR included in the first stage unit quantization circuit ADC1.
Of the comparison reference potentials formed by I, the comparison reference potentials immediately before and after the analog input voltage level are used as relative full scales, and the analog input voltage is quantized in four gradations to produce a 2-bit digital signal and D4. In the conversion operation in the converting/unit quantization circuit ADC2, the comparison reference potential is the analog input of the comparison reference potential formed by the resistive voltage dividing circuit DRI included in the first stage unit quantization circuit ADC1, as described above. The unit quantization circuit ADC2 is formed into four gradations using the comparison reference potentials immediately before and after the voltage level as a relative full scale.
The digital signals D3 and D4 obtained by are the digital signals obtained by the first stage unit quantization circuit ADC1. As a result, the analog-to-digital conversion circuit of this embodiment converts the analog input voltage Vi into 5 gradations with a total of 32 gradations by the 12 comparison circuits C0M1 to C0M12.
Can be converted into bits digitally.

According to the above embodiment, the following effects can be obtained.

(1) The first-stage unit quantization circuit ADI quantizes the analog input voltage Vi in 8 gradations with respect to the full-scale voltage VFS to generate a 3-bit digital signal. . The analog input voltage Vi is quantized in 4 gradations using the comparison reference potential as a relative full scale, and 2
The digital signal obtained by the unit quantization circuit ADC2 is converted into bit digital signals D3 and D4, and D4 is the digital signal obtained by the first stage unit quantization circuit ADC1. Therefore, the analog-to-digital conversion circuit of this embodiment converts the analog input voltage Vi into the 12 comparison circuits COMI
Through C0M12, it is possible to digitally convert to 5 bits with a total of 32 gradations.

(2) From the above effects, it is possible to obtain a number of gradations equal to the product of the respective numbers of comparison circuits included in each unit quantization circuit ADC1 and ADC2, and thereby, compared to the number of gradations or resolution. Analog signals can be converted to digital in parallel using a much smaller number of comparison circuits.

(3) From the above effects, it is possible to suppress the increase in the number of comparison circuits, thereby realizing multi-gradation or high resolution analog-to-digital conversion circuits using parallel comparison format from the viewpoint of space factor and low power consumption. can do.

(4) Based on the above effects, when image forming devices such as facsimiles and copiers realize intermediate gradation and colorization to form images, document information is read in an analog manner and digitized. When improving the resolution when converting data, a parallel comparison type analog-to-digital conversion circuit can be used to perform the conversion operation at high speed.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the two-stage unit quantization circuit ADC
1 and ADC2 as voltage output means
Although the three-stage unit quantization circuits ADCl to ADC3 are connected in series through W, as shown in FIG.
It is also possible to have a three-stage configuration in which the circuits are successively connected in a cascade via the switch circuits SW1 and SW2 of the stages, or a multi-stage configuration with more stages. In this case, the number of gradations is equal to the product of the respective numbers of comparison circuits included in each unit quantization circuit. In addition, when three or more stages of unit quantization circuits are connected in series, the output of the second stage switch circuit is fed back to the first stage switch circuit, and a new relative full-scale voltage is determined as the second stage switch circuit. If the voltage is applied to the unit quantization circuit of the second stage, the circuit configuration of the third stage and subsequent stages can be substantially replaced by the unit quantization circuit and the switch circuit of the second stage. Further, the voltage dividing means, binary conversion means, and voltage output means are not limited to those in the above embodiment, and their specific configurations can be changed as appropriate.

In the above explanation, the present invention was mainly applied to facsimiles, copying machines, etc. that require high-speed conversion operation and high resolution, which is the field of application in which the present invention is based, but the present invention is not limited thereto. ,analog·
The present invention, which can be applied to various devices requiring digital conversion, can be applied at least to those in which analog signals are converted into digital signals in a parallel comparison format.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a voltage dividing means that divides and outputs the applied voltage at predetermined intervals, a plurality of comparing means that compares each divided voltage output from the voltage dividing means and an analog input signal in parallel, and
A plurality of unit quantization circuits consisting of binary conversion means that obtain digital outputs based on the comparison results of the comparison means convert analog input signals from among the divided voltages formed by the voltage division means included in the unit quantization circuit in the previous stage. Since the divided voltages immediately before and after the level are cascaded via voltage output means that outputs the divided voltages before and after the level to the voltage dividing means included in the next stage unit quantization circuit based on the comparison result by the comparison means, the cascade connection The digital output obtained from each of the plurality of unit quantization circuits is sequentially treated as the upper bit, so that the number of gradations equal to the product of the respective numbers of comparison means included in each unit quantization circuit is obtained. This allows analog signals to be converted to digital in parallel using a much smaller number of comparison means than the number of gray levels or resolution.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of an analog-to-digital conversion circuit according to the present invention, and FIG. 2 is a circuit diagram schematically showing another embodiment of the present invention. ADCl and ADC2...unit quantization circuit, DR1 and DR2...resistance voltage divider circuit, COMI to COM12
...Comparison circuit, BCI and BC2...Binary conversion circuit, SW...Switch circuit, QHI to QH7...
・MOSFET, QL2 to QL8-“°MO8FET
, EXORI to EXOR7-... Exclusive OR circuit, Vi... Analog input voltage, VFS...
...Full scale voltage, D to D4...Digital signal.

Claims (1)

[Scope of Claims] 1. Voltage dividing means that divides and outputs the applied voltage at predetermined intervals, and a plurality of comparing means that compares each divided voltage outputted from the voltage dividing means with an analog input signal in parallel. , and a plurality of unit quantization circuits comprising binary conversion means for obtaining a digital output based on the comparison results by the comparison means,
Of the divided voltages formed by the voltage dividing means included in the unit quantization circuit in the previous stage, a voltage equal to the divided voltages immediately before and after the analog input signal level is applied to the next stage based on the comparison result by the comparing means. An analog-to-digital conversion circuit characterized in that the analog-to-digital conversion circuit is cascade-connected via voltage output means for outputting to voltage dividing means included in a unit quantization circuit. 2. The voltage output means includes a two-input exclusive OR circuit that receives output signals from adjacent comparison means, respectively;
A switch element that enables output of the divided voltage supplied to the comparison means coupled to the input terminal of each exclusive OR circuit based on the output signal of the exclusive OR circuit. The analog-to-digital conversion circuit according to claim 1, characterized in that: