JPH05129953A - A/d conversion circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy of A/D conversion by incrementing a high- order bit component by one bit without increasing the number of resistance elements of a resistance ladder circuit. CONSTITUTION:The output voltage of a multiplexer 2 inputting the divided voltages of all nodes and selecting one of them in a resistance ladder circuit 1 and an analog input voltage 10 are connected to a node 20 via gates 15, 14. The output voltage of a multiplexer 3 inputting divided voltages at nodes n0, n2-n14 of the resistance ladder circuit 1 and selecting one of them and a divided voltage at a node n1 are connected to a node 21 via gates 17, 18. Nodes 20, 21 are connected to a chopper amplifier circuit 5 via capacitors 17, 18, a control circuit 6 generates decode signals 7, 8 for the multiplexers 2, 3 based on the result of an output 23 to decide the divided voltage required for comparison, thereby implementing the A/D conversion through successive approximation by a comparator means 22a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital conversion circuit for converting an analog input voltage into a digital value, and more particularly to an analog-digital conversion circuit incorporated in one chip such as a one-chip microcomputer.

[0002]

2. Description of the Related Art An analog-digital conversion circuit (hereinafter referred to as A-
The analog-to-digital conversion value in the D conversion circuit) corresponds to the number of bits of resolution, and the lowest digit of the bit at this time is called LSB (Least Significant Bit).
Values below this LSB are essentially unrepresentable in the A / D converter circuit, and the resulting error is called the quantization error. Therefore, the values below the LSB are truncated, and the maximum absolute error is 1 LSB. However, there is a method of theoretically reducing the quantization error to ± (1/2) LSB or less by shifting the AD conversion characteristic of the AD conversion circuit by (1/2) LSB.

FIG. 3 shows the A / D conversion characteristic (the A / D conversion code for the analog input voltage Vin) being (1/2) LSB.
Quantization error is ± (1/2) LS by shifting
It is a figure for demonstrating that it becomes below B. In FIG. 3, the horizontal axis represents a value obtained by dividing the analog input voltage Vin by the LSB, that is, the analog input voltage corresponding to 1 LSB is set as one unit. The vertical axis is the AD conversion code for the analog input voltage. Reference numeral 35 denotes an A-D conversion characteristic before (1/2) LSB shift, which is represented by a stepped broken line. 36
Is the AD conversion characteristic after (1/2) LSB shift, and is represented by a stepwise solid line. Reference numeral 37 is a conversion characteristic of an AD conversion circuit having an infinite resolution. In FIG. 3, the quantization error is a deviation from the AD conversion characteristic having infinite resolution.

FIG. 3 shows a range of analog input in which the AD conversion code is "03", and the range is 2.
It is a value larger than 5 LSB and smaller than 3.5 LSB.
In this range, when the analog input is close to 2.5 LSB, the quantization error becomes maximum + (1/2) LSB, and 3.5 LSB.
In the case of, it becomes-(1/2) LSB.

A conventional example for realizing this A-D conversion characteristic will be described with reference to the drawings. In the following description, the connection point is simply called a node. FIG. 4 shows an A-D conversion circuit having a resolution of 8 bits, and in particular, a charge-balanced A-D conversion circuit using the successive approximation conversion system.
It is a conversion circuit. In FIG. 4, 34 is a resistance ladder circuit in which 2 ^N (32 in this case) resistance elements having the same resistance value are connected in series, r1 to r32 are resistance elements constituting the resistance ladder circuit 34, and n0 to n30 are resistances. Ladder circuit 34
, 28, 29 are first and second multiplexers, 4 is a capacitance ladder circuit, 5 is a chopper amplifier circuit,
6 is a control circuit, 30 and 31 are multiplexers 2 respectively
Decode signals input to 8 and 29, 9 and 10 are input terminals for supplying a Vref voltage (reference voltage) and an analog input voltage, and 32 and 33 are multiplexers 2 respectively.
8 and 29 output voltages, 13 voltage at the node n1 of the resistance ladder circuit 34, 14 to 17 gates (switching elements), 18 and 19 capacitors, 20 to 22 nodes, 23 chopper amplifier circuit output, and 24 Gate 14
˜17, 25 is a control signal for controlling the chopper amplifier circuit 5, 26 is an inverter circuit, and 27 is a feedback gate of the chopper amplifier circuit 5.

The resistance elements r1 to r32 are connected in series in that order from GND. An input terminal 9 is provided at the end of the resistance element r32, and the Vref voltage is supplied to the input terminal 9. n0 to n30 represent nodes r1 to r31 in that order from GND. Node n0,
The voltages from n2, n4, ..., N30 are input to multiplexers 28 and 29, respectively. The output 32 of the multiplexer 28 and the analog input voltage supplied to the input terminal 10 are commonly connected to the node 20 via the gates 15 and 14, respectively. The voltage 13 at the node n1 of the resistance ladder circuit 34 and the output 33 of the multiplexer 29 are commonly connected to the node 21 via the gates 16 and 17, respectively. Each terminal of the capacitor 18 is connected to the node 20 and the node 22. Each terminal of the capacitor 19 is connected to the node 21 and the node 22. Node 22
Is output to the chopper amplifier circuit 5, and the output 23 of the chopper amplifier circuit 5 is input to the control circuit 6. The decode signals 30 and 31 are output from the control circuit 6 and are input to the multiplexers 28 and 29, respectively.

The decoded signal 30 is sent to the multiplexer 28 at 16 nodes n0, n2, n4, ..., N30.
It is a 4-bit decode signal (A7 to A4) for decoding the normal voltage. In the multiplexer 29, the decoded signal 31 is transferred to the nodes n0, n2, n4, ...
It is a 4-bit decode signal (A3 to A0) for decoding 16 different voltages of n30. Condenser 18
Has a first predetermined number (1) of weights and capacitor 1
9 has a second predetermined number (1/2 ^{M + 1} ) of weightings.
The capacitors 18 and 19 each have a capacity of 16
With C and C, the capacitor 18 is 16 times the capacity of the capacitor 19.
Double. Further, r1 to r32 all have the same resistance value.

Next, the operation of the circuit shown in FIG. 4 will be described.
When A-D conversion is started, a b7 (MSB) comparison cycle (see FIG. 2) is first entered. When the control signal 24 becomes “H”, the gates 14 and 16 are opened and the gate 15 and
17 is closed. At this time, the potentials of the nodes 20 and 21 become the analog input voltages Vin and Vref / 32, respectively. While the control signal 24 is "H", the control signal 2
5 also becomes “H”, the feedback gate in the chopper amplifier circuit 5 becomes conductive, and the potential of the node 22 is fixed to the bias voltage VB. At this time, the capacitor 18 is charged with a charge of Q1 = 16C × (Vref / 32−VB), and the capacitor 19 is charged with a charge of Q2 = C × (Vin−VB). The total charge amount of the capacitors 18 and 19 is Q = Q1 + Q2.

Next, when the control signal 24 changes from "H" to "L", the gates 14 and 16 are closed and the gates 15 and 1 are closed.
7 is opened. At this time, the potentials of the nodes 20 and 21 become the output voltages of the multiplexers 28 and 29, respectively. In the conversion cycle of b7, the decode signal 30 input to the multiplexer 28 is A7, A6, A5, A4 = 1, 0,
0,0 and the output of the multiplexer 28 is 1000
The voltage ((Vref / 32) × 16 = Vre of the node having a number corresponding to twice the binary value, that is, the node n16.
f / 2). Next, the decode signal 31 input to the multiplexer 29 is A3, A2, A1, A0 = 0, 0,
0, 0, and the output of the multiplexer 29 is 0000
The voltage corresponds to a node (because every other node is input to the multiplexer 29) twice as many as (binary), that is, the voltage (0 V) of the node n0.

When the control signal 24 is "L", the control signal 25
Becomes "L", the feedback gate 27 becomes non-conductive, and the node 22 becomes floating. When the potential of the node 22 at this time is VBD, the capacitor 18 is charged with Q1D = 16C × (Vref / 2−VBD) and the capacitor 19 is charged with Q2D = C × (0-VBD). The total charge amount of the capacitors 18 and 19 is QD = Q1D + Q2D.

Even if the control signal 24 changes from "H" to "L", since the node 22 is in a floating state, there is no charge and output, and Q = QD. That is, the potential change amount of the node 22 is VBD-VB = (1/17) [Vin-{(Vref / 2)-(Vref / 512)}]. That is, in the comparison means 22a, the input terminal 10
From the analog input voltage Vin and the reference voltage (Vref /
2-Vref / 512). The determination result of the voltage comparison is output to the output 23 of the chopper amplifier circuit 5, and the AD conversion value of b7 in the comparison cycle is determined. The control circuit 6 determines the decode signal in the next b6 comparison cycle based on the output 23.

The potential change amount of the node 22 in each comparison cycle with respect to the decode signals A7 to A0 is

[0013]

[Equation 1]

[0014] The comparison cycle of b7 to b0 is performed for each bit, and the comparison cycle of b0 is completed and the AD conversion operation is completed. As a result, the A / D converted values b7 to b0 of the analog input voltage Vin are determined.

In this method, when performing 8-bit A / D conversion, the capacitor 18 is made to bear the 4-bit high-order bit component, and the capacitor 19 is made to take the 4-bit low-order bit component. That is, the full ladder component is 4
It becomes a bit (higher-order bit component).

[0016]

By the way, the charge-balance type A-D converter circuit weights a plurality of capacitors respectively and assigns a high-bit component and a low-bit component of the conversion bit number to each capacitor. The divided analog input and the divided voltage of the resistance ladder circuit are compared. At this time, it is a well-known fact that the A-D conversion accuracy is improved mainly as the number of higher-order bit components (full ladder component) increases. However, there is a problem that the area of the resistance ladder circuit increases when the number of components is increased. Further, as described in the conventional example, the A / D conversion characteristic is set to 1 /
Two resistance elements are provided between the respective nodes of the resistance ladder circuit introduced into the multiplexer for shifting by two, and this is a problem in a semiconductor integrated circuit in that pattern waste occurs.

The present invention has been made to solve the above-mentioned problems, and the A-D conversion accuracy can be improved without increasing the number of resistance elements constituting the resistance ladder circuit. It is an object to provide a D conversion circuit.

[0018]

Means for Solving the Problems] A-D converter circuit according to the present invention, from ^the 2 ^N of the connection point in the 2 ^N resistive elements of the resistor ladder circuit 1 when performing A-D conversion of N + M bits First multiplexer 2 for selecting the divided voltage of
And a second multiplexer 3 that selects a divided voltage from every two (every other) connection points, and switches the analog input voltage and the output of the first multiplexer 2 from switching elements (gates 14 and 15). ), And then connect to the input end of the comparison means 22a via the capacitor 18, and connect the output of the second multiplexer 3 and the fixed connection point among the connection points in the resistance ladder circuit 1. The output voltage and the output voltage are commonly connected through the switching elements (gates 14 and 16), and then connected to the input terminal of the comparison means 22a through the weighted capacitor 19 of 1/2 ^{M + 1} , and the comparison means 22a. By comparing the size of both by
D conversion is performed.

[0019]

The output voltage and the analog input voltage of the first multiplexer 2 for inputting the divided voltages of the 2 ^N connection points in the resistance ladder circuit 1 and selecting one of them are the switching elements (gates 15 and 14) and the analog input voltage. It is input to the comparison means 22a via the capacitor 18. Further, the output voltage of the second multiplexer 3 for inputting 2 ^N divided voltages in the resistance ladder circuit 1 to select one of them and the output voltage of the fixed connection point in the resistance ladder circuit 1 are each switching element (gate 17). , 16) and the capacitor 19 to be input to the comparison means 22a. Thereby, the comparison means 22a
Performs A + D conversion of N + M bits.

[0020]

1 is a circuit configuration diagram of a successive approximation type A / D conversion circuit having 8-bit resolution according to an embodiment of the present invention.
In FIG. 1, 1 is a resistance ladder circuit in which 2 ^N (32 in this case) resistance elements having the same resistance value are connected in series, r
1 to r32 are resistance elements constituting the resistance ladder circuit 1, n
0 to n31 are nodes (connection points) in the resistance ladder circuit 1, and 2 is a first for selecting the voltage of one of the nodes n0 to n31 based on the decode signal of the upper N bits (in this case, the upper 5 bits). The multiplexer 3 of the resistance ladder circuit 1 outputs the voltage of one node from every two nodes (every other node) of the nodes n0 to n31 based on the decode signal of the lower M bits (lower 3 bits in this case). It is the second multiplexer to be selected. Reference numeral 4 is a capacitance ladder circuit including gates 14 to 17 as switching elements, capacitors 18 and 19 and comparing means 22a, 5 is a chopper amplifier circuit for amplifying the output of the comparing means 22a, and 6 is based on the output of the comparing means 22a. A control circuit for outputting a decode signal of upper 5 bits and a decode signal of lower 3 bits, 7 and 8 are decode signals input to the first and second multiplexers 2 and 3, and 9 is Vr.
An input terminal for supplying an ef voltage, 10 is an input terminal for supplying an analog input voltage, and 11 and 12 are first and second, respectively.
Output voltages of the multiplexers 2 and 3, 13 is a voltage at the node n1 of the resistance ladder circuit 1, 20 to 22 are nodes, 23 is a chopper amplifier circuit output, and 24 is a gate 14.
˜17, 25 is a control signal for controlling the chopper amplifier circuit 5, 26 is an inverter circuit, and 27 is a feedback gate of the chopper amplifier circuit 5.

The resistance elements r1 to r32 are connected in this order from GND in series. The terminal of the resistance element r32 has a terminal 9, and the Vref voltage is supplied to the terminal 9. n0 to n31 are r1 to GND in that order, respectively.
It represents the node of r31. The voltages from the nodes n0 to n31 are input to the multiplexer 2. Node n
Voltages from even-numbered nodes 0 to n14 are input to the multiplexer 3. The output 11 of the multiplexer 2 and the analog input voltage supplied to the terminal 10 are commonly connected to the node 20 via the gates 15 and 14, respectively. The voltage 13 at the node n1 of the resistance ladder circuit 1 and the output 12 of the multiplexer 3 are commonly connected to a node 21 via gates 16 and 17, respectively. Condenser 18
Each terminal of is connected to the node 20 and the node 22.
Each terminal of the capacitor 19 is connected to the node 21 and the node 22. The voltage of the node 22 (comparing means 22a) is input to the chopper amplifier circuit 5 and is input to the chopper amplifier circuit 5.
Output 23 is input to the control circuit 6. The decode signals 7 and 8 are outputs of the control circuit 6 and are input to the multiplexers 2 and 3, respectively.

Decode signal 7 is a 5-bit decode signal (A7 to A3) for decoding 32 different voltages of nodes n0 to n31 in multiplexer 2.
The decoded signal 8 is sent to the node n in the multiplexer 3.
A 3-bit decode signal (A2 to A0) for decoding eight kinds of voltages of 0, n2, n4, ..., N14
Is. Since the capacitor 19 has a weight of 1/2 ^{M + 1} and M = 3 in this example, the capacitances of the capacitors 18 and 19 are 16 C and C, respectively. Also r1
All of r32 have the same resistance value.

FIG. 2 shows the 8-bit successive approximation type A shown in FIG.
FIG. 7 is a timing diagram showing the operation of the −D conversion circuit.
2 is the control signal 24 shown in FIG.
Is. b7, b6, b5, ... Are conversion results from the upper bits when the analog input voltage is A-D converted, D7
Decode signals 7, 8 sent to the multiplexers 2, 3 in the comparison cycle of b7, b6, b5, ...
(A7 to A0).

Next, the operation of FIG. 2 will be described. One cycle of the control signal 24 is a comparison cycle of each bit of the AD conversion value. The decode signal D7 in the comparison cycle of b7 is A7, A6, ..., A0 = 1,0,0,0,
0,0,0,0. When the comparison cycle of b7 ends, the converted value of b7 is determined. Depending on the value of this b7, b6
The decode signal D6 in the comparison cycle is determined (A
7, A6, ..., A0 = b7,0,0,0,0,0,
0,0). Similarly, the decoded signal D5 is A7, A6,
..., A0 = b7, b6, 0, 0, 0, 0, 0, 0. By continuing this in sequence, the converted values of b7 to b0 are obtained. This procedure is a general A-D conversion method by successive comparison.

Next, the operation of FIG. 1 will be described. A-D
When the conversion is started, the b7 comparison cycle is first started. When the control signal 24 becomes “H”, the gates 14 and 1
6 is opened and gates 15 and 17 are closed. At this time, the potentials of the nodes 20 and 21 are the analog input voltage Vi.
n, Vref / 32. This control signal 24 is "H"
During this period, the control signal 25 also becomes “H”, the feedback gate 27 in the chopper amplifier circuit 5 becomes conductive, and the potential of the node 22 is fixed to the bias voltage VB. At this time, the capacitor 18 is charged with Q1 = 16C × (Vref / 32−VB) and the capacitor 19 is charged with Q2 = C × (Vin−VB). The total charge amount of the capacitors 18 and 19 is Q = Q1 + Q2.

Next, when the control signal 24 changes from "H" to "L", the gates 14 and 16 are closed and the gates 15 and 1 are closed.
7 is opened. At this time, the potentials of the nodes 20 and 21 become the output voltages of the multiplexers 2 and 3, respectively. In the conversion cycle of b7, the decode signal 7 input to the multiplexer 2 is A7, A6, ..., A3 = 1, 0, 0,
0,0 and the output of multiplexer 2 is 10000
The voltage ((Vref / 32) × 16 = Vre of the node having a number corresponding to the value of (binary) = 16, that is, the node n16.
f / 2). Next, the decoded signal 8 input to the multiplexer 3 becomes A2, A1, A0 = 0, 0, 0,
The output of the multiplexer 3 is a node corresponding to a number twice 000 (binary) (because only one node is input to the multiplexer 3), that is, the voltage (0V) of the node n0.
Becomes

When the control signal 24 is "L", the control signal 25
Becomes "L", the feedback gate 27 becomes non-conductive and the node 22 becomes in a floating state. When the potential of the node 22 at this time is VBD, the capacitor 18 is charged with Q1D = 16C × (Vref / 2−VBD) and the capacitor 19 is charged with Q2D = C × (0-VBD). The total charge amount of the capacitors 18 and 19 is QD = Q1D + Q2D.

Even if the control signal 24 changes from "H" to "L", since the node 22 is in a floating state, there is no charge and output, and Q = QD. That is, the potential change amount of the node 22 is VBD-VB = 1/17 {Vin- (Vref / 2)-
(Vref / 512)}. That is, the comparison means 22
a, the analog input voltage Vin from the input terminal 10
And a reference voltage (Vref / 2−Vref / 512) are compared. The determination result is output to the output 23 of the chopper amplifier circuit 5, and the conversion value of b7 is determined. The control circuit 6 determines the decode signal in the next b6 comparison cycle based on the output 23.

The potential change amount of the node 22 in each comparison cycle with respect to the decode signals A7 to A0 is

[0030]

[Equation 2]

It becomes The comparison cycle of b7 to b0 is performed for each bit, and the comparison cycle of b0 is completed and the AD conversion operation is completed. As a result, the A / D converted values b7 to b0 of the analog input voltage Vin are determined.

In this method, when performing 8-bit A / D conversion, the capacitor 18 is made to bear the higher bit component of 5 bits, and the capacitor 19 is made to take the lower bit component of 3 bits. That is, the full ladder component is 5
Become a bit.

[0033]

According to the present invention as described above, according to the present invention, the M pieces of the connection point to be input to the second multiplexer of the connection point of ^the 2 ^N of the series connected resistor elements in the resistor ladder circuit, 2 ^N Since every two connection points are taken out and connected to the input terminal of the second multiplexer, each connection point in the resistance ladder circuit can be used without waste, and the upper bit component is 1 bit. Therefore, it is possible to increase the number of resistance elements in the resistance ladder circuit, thereby improving the AD conversion accuracy.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an AD conversion circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an AD conversion operation by successive approximation in this embodiment.

FIG. 3 is an AD conversion characteristic diagram for explaining a quantization error.

FIG. 4 is a circuit configuration diagram of a conventional AD conversion circuit.

[Explanation of symbols]

 1 Resistance Ladder Circuit 2 1st Multiplexer 3 2nd Multiplexer 6 Control Circuit 14-17 Gate (Switching Element) 18, 19 Capacitor 22a Comparison Means r1-r32 Resistance Element n0-n31 Node (Connection Point)

[Procedure amendment]

[Submission date] August 24, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

Next, the operation of FIG. 1 will be described. A-D
When the conversion is started, the b7 comparison cycle is first started. When the control signal 24 becomes “H”, the gates 14 and 1
6 is opened and gates 15 and 17 are closed. At this time, the potentials of the nodes 20 and 21 are the analog input voltage Vi.
n, Vref / 32. This control signal 24 is "H"
During this period, the control signal 25 also becomes “H”, the feedback gate 27 in the chopper amplifier circuit 5 becomes conductive, and the potential of the node 22 is fixed to the bias voltage VB. At this time, the capacitor 18 is charged with Q1 = 16C * ( Vin -VB ) and the capacitor 19 is charged with Q2 = C * ( Vref / 32-VB ). The total charge amount of the capacitors 18 and 19 is Q = Q1 + Q2.

Claims (1)

[Claims] 1. A resistance ladder circuit in which 2 ^N resistance elements having the same resistance value are connected in series, and a voltage at one connection point among the connection points of 2 ^N resistance elements in this resistance ladder circuit A first multiplexer that selects based on the decode signal of the upper N bits and a voltage at one connection point of the connection points of the 2 ^M resistance elements in the resistance ladder circuit based on the decode signal of the lower M bits. And a second multiplexer for selecting the analog input voltage to be compared with the reference voltage obtained based on the outputs of the first and second multiplexers and outputting a digital signal. A control circuit for outputting the upper N-bit decode signal and the lower M-bit decode signal based on the output of the comparison means is provided, and the analog input voltage and the first round signal are provided. The outputs of the chipplexer are connected in common through respective switching elements, and then connected to the input terminal of the comparison means through a first predetermined number of weighted capacitors, and the output of the second multiplexer and the resistance ladder circuit are connected. The output voltage of a fixed connection point among the connection points of the resistance elements is commonly connected through the switching elements and then connected to the input terminal of the comparison means through the second predetermined number of weighted capacitors. By doing so, in the analog-digital conversion circuit that performs analog-digital conversion of the analog input voltage by successive comparison of N + M bits, the second of the connection points of 2 ^N series-connected resistance elements in the resistance ladder circuit is used. The M connection points to be input to the second multiplexer are extracted every two from the 2 ^N connection points, and the input terminal of the second multiplexer is extracted. An analog-digital conversion circuit characterized by being connected to.