JPH01225362A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate an electrostatic breakdown doe to ion implantation by a method wherein a substrate in an area to form a source region and a drain region is etched selectively by making use of a part to form a gate electrode as a mask, a recessed part is formed, a source and a drain are formed and, after that, a gate oxide film is formed. CONSTITUTION:A thick oxide film 2 for device isolation use is formed on a P-type silicon substrate 1; a gate electrode 4 of polycrystalline silicon is formed via a gate oxide film 3. Source and drain diffusion layers 5, 6 are formed in alignment with the gate electrode. A resist pattern 13 covering an area to form a gate electrode is formed. The silicon substrate 1 is etched anisotropically in self-alignment manner with a mask pattern and the oxide film 2 for device isolation use; a recessed area is formed. Ions are implanted into this recessed area in order to form a source and a drain. Then, the gate oxide film 3 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a process for manufacturing an MO8 field effect transistor.

[Conventional technology]

Conventionally, a field effect transistor used in an MO8 type semiconductor device has a source and a gate electrode 4 formed on a gate insulating film 3 in a self-aligned manner, as shown in FIG.
It has a structure in which drain diffusion layers 5 and 6 are arranged, and is manufactured through the manufacturing steps shown in FIGS. 6(a) to 6(d).

That is, as shown in FIG. 6(a), for example, a polycrystalline silicon film 4 is deposited on a semiconductor substrate 1 via a gate insulating film 3, and a resist pattern 13 for forming a gate electrode is formed by ordinary photolithography. Form. Next, the polycrystalline silicon film is selectively etched using this resist pattern as a mask, and after removing the oxide film on the area where the source/drain diffusion layer is to be formed, it is reoxidized to obtain the result shown in FIG. 6(b). .

Next, source/drain diffusion layers 5 and 6 are formed by ion-implanting impurities of a conductivity type opposite to that of the substrate into the gate electrode and the thick oxide film 2 for element isolation in a self-aligned manner. After that, as shown in FIG. 6(c), an interlayer insulating film 8 is deposited, and after forming an opening for electrical connection, a metal film 9 is formed as shown in FIG. 6(d). , by patterning this, the structure shown in FIG. 3 is obtained.

[Problem to be solved by the invention]

By the way, in the conventional manufacturing method described above, after forming a gate electrode through a gate oxide film, ion implantation is used to form source/drain diffusion layers in a self-aligned manner with respect to the gate electrode.

Therefore, charges due to the implanted ions are accumulated in the gate electrode. Conventionally, the gate oxide film was relatively thick at about 500 to 1000 layers, so the above-mentioned charging effect did not pose a problem, but as device dimensions became smaller, the gate oxide film became thinner, and A problem arises in that electrostatic breakdown of the gate insulating film occurs frequently due to charges accumulated in the gate electrode.

[Differences between the invention and the prior art]

In contrast to the conventional semiconductor device manufacturing method described above, the present invention etches the portion of the semiconductor substrate where the source/drain is to be formed, forms a source/drain diffusion layer there, and then forms a gate insulating film. Another difference is that the gate electrode can be formed in a self-aligned manner with respect to the source and drain.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes a step of patterning a film having masking properties against etching of a semiconductor substrate so as to cover a portion where a gate electrode is to be formed, and a step of patterning a film having a masking property against etching of a semiconductor substrate, and a step of patterning a film having a masking property against etching of a semiconductor substrate so as to cover a portion where a gate electrode is to be formed. a step of selectively etching the semiconductor substrate to form a recess in a self-aligned manner; and a step of forming a source/drain diffusion layer in the recess in a self-aligned manner with respect to the mask pattern and the element isolation region. After forming the source/drain diffusion layer, the method includes a step of removing the mask material and forming a gate insulating film, and a step of forming a gate electrode on the gate insulating film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view of an MO8 field effect transistor formed by an embodiment of the manufacturing method of the present invention. A thick oxide film 2 for element isolation is formed on a P-type silicon substrate l, and a gate electrode 4 of polycrystalline silicon is formed with a gate oxide film 3 interposed therebetween. Source/drain diffusion layers 5 and 6 are formed in alignment with the gate electrode.

The manufacturing method will be explained below using FIGS. 4(a) to 4(D). First, as shown in FIG. 4(a), a thick oxide film 2 for element isolation is formed by a selective oxidation method. 2 on the active area
After growing the oxide film 11 of 1,000 to 1,000 layers, a nitride film 12 of 1,000 to 2,000 layers is deposited by vapor phase growth. Then, a resist film is applied to cover the area where the gate electrode is to be formed.
The pattern 13 is formed by, for example, photolithography. Although not shown, impurities for adjusting the threshold voltage of the transistor may be introduced into the active region of the substrate surface region by ion implantation. It is also known to form an impurity layer for parasitic channel stop directly under the element isolation oxide film.

Next, as shown in FIG. 4(b), the nitride film 12 is anisotropically etched using the resist pattern 13 as a mask, and the oxide film 11 is further removed. Then, as shown in the fourth time (C), the silicon substrate 1 is anisotropically selectively etched in a self-aligned manner with respect to the mask pattern and the oxide film 2 for element isolation. Form a deep recess. Subsequently, arsenic, for example, is ion-implanted at a depth of about 10<15 >cm<-2 >into this recessed portion to form a source/drain. At this time, ion implantation may be performed while tilting and rotating the substrate with respect to the direction of incidence of the ion beam, or high-dose ion implantation may be performed perpendicular to the substrate, and then the substrate may be tilted for comparison. Ion implantation may be performed at a targeted low dose. Next, as shown in FIG. 4(d), spin-on glass, for example, is applied onto the substrate to fill the aforementioned recesses. Note that this material may be any other material than spin-on glass. Thereafter, as shown in FIG. 4(e), the previously applied spin-on glass 7 is etched back so that the nitride film 12 covering the gate region is exposed and remains in the recess. Then, the exposed nitride film 12 is wet-etched, and the oxide film 11 is further removed, as shown in FIG.
"). Next, as shown in Figure 4 (g),
After forming the gate oxide film 3, a conductive polycrystalline silicon film 4 is deposited on the substrate, and a resist pattern 13 is formed by photolithography or the like. Then, using this resist pattern 13 as a mask, the polycrystalline silicon film 4 is selectively etched to obtain the pattern shown in FIG. 4(h). Thereafter, in the same manner as before, an interlayer insulating film 8 is deposited as shown in FIG.
As shown in the figure (D), a metal wiring layer 9 is formed.

FIG. 2 is a sectional view of Example 2 of the present invention.

In this embodiment, since the degree of self-alignment between the gate electrode 4 and the source/drain diffusion layers 5 and 6 is higher than that in the first embodiment, there is an advantage that the parasitic capacitance can be lowered. Below, the fifth
The manufacturing method will be explained using Figures (a) to (k). First, as shown in FIG. 5(a), a thick oxide film 2 for element isolation is formed on a P-type silicon substrate, and a tungsten film 22 of about 2,000 to 6,000 layers is deposited on the substrate. Then, a resist pattern 13 is formed to cover the portion where the gate electrode is to be formed. After that, the tungsten film 22 is
Selective etching is performed as shown in FIG. 5(b), and the substrate is further subjected to, for example, reactive ion etching as shown in FIG. 5(c), and the source/drain diffusion layer 5 is , 6 are formed as shown in FIG. 5(d). Next, the fifth
As shown in Figure (e), an oxide film 10 is deposited on the substrate by vapor phase growth, and a coating film 7 is further formed. moreover,
A resist 13 is applied to flatten the substrate surface. Note that the material filling the recesses may be an insulating film, and the material is not particularly limited. Further, it is not particularly necessary to use a resist film to flatten the substrate surface. Next, Fig. 5 (f
), the multilayer film described above is etched back under conditions such that the etch rate of each layer is approximately the same, exposing the surface of the tungsten film 22, and as shown in FIG. 5(g). Then, the exposed tungsten film 22 and oxide film 11 are removed by wet etching. After that, Fig. 5 (h)
As shown in FIG. 2, a gate oxide film is formed and a conductive film 4 is deposited on the substrate. Next, as shown in FIG. 5(i), the conductive film is selectively etched back to form the gate electrode 4. Then, as shown in FIG. 5(j), a PSG film 8 is deposited as an interlayer insulating film, and a resist pattern 13 is formed to form openings for electrical connection with sources, drains, etc. Thereafter, according to the usual process, a metal wiring film 9 is deposited as shown in FIG. 5(k), and this is patterned to obtain the structure shown in FIG. 2.

〔Effect of the invention〕

As explained above, the present invention masks the area where the gate electrode is to be formed, selectively etches the substrate in the area where the source/drain region is to be formed to form a recess, and after forming the source/drain in the recess, the gate electrode is formed. Since an oxide film is formed, electrostatic damage caused by ion implantation is not a problem, and a very thin gate oxide film can be used. In addition, the source/drain diffusion layer is formed on the surface of the recess in the substrate, and a relatively thick insulating film is embedded between the gate electrode and the surface of the source/drain diffusion layer, so the overlap capacitance here is low. The effect is that it can be suppressed.

[Brief explanation of the drawing]

FIG. 1 shows an MO manufactured according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of an MO8 field-effect transistor manufactured according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of an MO8 field-effect transistor manufactured by a conventional manufacturing method. FIG. Fourth
Figures (a) to (D) are cross-sectional views showing the manufacturing process of the first embodiment, Figures 5 (a) to (k) are cross-sectional views showing the manufacturing process of the second example, and Figure 6. (a) to (d) are process cross-sectional views showing conventional manufacturing processes.]...Silicon substrate, 2...Oxide film,
3... Gate oxide film, 4... Gate electrode, 5, 6... Source/drain region, 7...
...Insulating film, 8...Interlayer insulating film, 9...
... Wiring, 10, 11... Oxide film, 12...
...Nitride film, 13...Resist, 22...
...Tungsten film. Agent Patent Attorney Uchihara Oto J:'r'-)d Shuiyodo I and M 5.6-Source Train 7:2 Oshi H Benbou II! f ll: Aifuyo ■Toji 2 Fig. 3rd ll: I'm going to have a good time 4 rMctL) $ 4 Fig. Cb) 4th r3! rcc> Kaya 4Ii? T(d) Printing 4- vMCC no Kaya 4 I! I (ffJ sheep 4 round (J,) 4th shi ``Cd'' broom + times (j) 5 ''riplay 5 r5! J (b) $ 5 1MCC) Seat 5 Area (d) No. '; I! T(e) $ 5 rMrf> 多1 5 te'J Uの茅 5 呵Ck) 5 茊（1,） 一茅 5 prisoner(j) ＄ 5 Kiσ(ro)

Claims (1)

[Claims] a step of forming a film on a semiconductor substrate that has a masking property against etching of the substrate; a step of selectively removing the mask film other than a portion where a gate electrode is to be formed on the semiconductor substrate; selectively moving the semiconductor substrate in a self-aligned manner with respect to the pattern and the element isolation region;
forming a recess in the substrate surface by anisotropic etching; forming a source/drain diffusion layer in the recess in a self-aligned manner with respect to the mask pattern and the element isolation region; After forming the source/drain diffusion layer, a step of filling the inside of the recess with an insulating film, a step of selectively removing the mask film covering the region where the gate electrode is to be formed, and a step of removing the gate electrode on the semiconductor substrate in the region where the gate electrode is to be formed. A method for manufacturing a semiconductor device, comprising the steps of forming an insulating film and forming a gate electrode on the gate insulating film.