JPH01225173A - Field effect transistor - Google Patents

Abstract

PURPOSE:To operate a field effect transistor at a high speed by utilizing electrons induced in a channel layer not doped with an impurity and having high mobility. CONSTITUTION:An undoped buffer layer 11, a first channel layer 12, a second channel layer 13, an undoped barrier layer 14, a source electrode 15, a drain electrode 16, and a gate electrode 17 are provided. Here, when large + voltage is applied to the electrode 17, the characteristic of an energy band diagram is largely improved. That is, a depleted layer is eliminated, and electrons are stored in the layer 13. Since an impurity is not doped in the layer 13, the mobility of the electrons is high, and its characteristics are improved. Thus, it can be operated at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor that operates at high speed.

[Conventional technology]

Conventionally, a field effect transistor (FET) having an n-type doped channel as shown in FIG. 5 has been proposed. (H,) t'ido, et, al, FBE
E EIeetron Device Lett,
vol fEDL-7+ pp, 625-626.19
86) FIG. 5 is a sectional view showing the structure of a conventional semiconductor, and FIG. 6 is an energy band diagram of the semiconductor. In the figure, 21 is an undoped buffer layer, 22 is a channel layer doped with impurities, 24 is an undoped barrier layer, 25 is a source electrode, 26 is a drain electrode, 27 is a gate electrode, and 28 is a depletion layer. Undoped buffer layer 21 made of GaAs
A GaAs channel layer 22 doped with n-type at a high concentration on top
, AJ! A laminate is constructed in which an undoped barrier layer 24 made of gGa+-gAs is deposited. A source electrode 25 made of ohmic AuGe is placed on this laminate.
A MiS type PET is constructed by providing a drain electrode 26 and a gate electrode 27 made of non-ohmic AN. between these two electrodes. This transistor has gate electrode 2
A voltage is applied to 7 to change the thickness of the depletion layer 28 extending into the channel layer 22, thereby performing FET operation.

In this case, since electron storage is performed in the channel layer doped with impurities, the movement of electrons becomes slow due to scattering of the electrons by the impurities, making it unsuitable for high-speed operation.

[Problem to be solved by the invention]

Conventional semiconductors have the drawback that the channel is doped with impurities at a high concentration, and the mobility of electrons passing through the channel is reduced due to impurity scattering, making them unsuitable for high-speed operation.

An object of the present invention is to solve the drawback of low electron mobility in conventional Mis-type FETs and to provide an FET that operates at high speed.

[Means to solve the problem]

A second channel layer made of a second semiconductor having a sufficiently low impurity concentration is formed on the channel layer made of the first semiconductor doped with n-type, and further formed thereon. A barrier layer made of a third semiconductor smaller than the semiconductor of the second channel layer was deposited and formed, and an FET was provided in which a source electrode, a drain electrode, and a gate electrode were provided on a stack of these layers.

〔effect〕

When a large voltage of 10 is applied to the gate electrode of the FET of the present invention, the depletion layer in the second channel layer that is not doped with impurities disappears, electrons are accumulated in the second channel layer, and the scattering of electrons by the impurities is also eliminated. Therefore, the mobility of electrons increases.

〔Example〕

The present invention will be described in detail below along with examples.

FIG. 1 is a sectional view showing the structure of an FET that is an embodiment of the present invention. In the figure, 11 is an undoped buffer layer;
2 is a first channel layer, 13 is a second channel layer, 14 is an undoped barrier layer, 15 is a source electrode, 16 is a drain electrode, and 17 is a gate electrode. The first channel layer 12 is a channel layer in which the first semiconductor is doped with impurities, the second channel layer 13 is a channel layer in which the second semiconductor is not doped with impurities, and the undoped barrier layer 14 is in which the impurity concentration of the semiconductor is sufficiently low and the electron This layer has a smaller affinity than the second channel layer 13. Film thickness of about 5,000 layers made of GaAs O7
On the substrate of the undoped buffer layer 11, a first channel layer 12 made of GaAs doped with n-type at a high concentration (~I x 10 "cra-") and having a thickness of about 300 layers is deposited. is the undoped thickness of GaAs, 20
A second channel layer 13 is deposited on the order of about 100 yen, and an AI layer is further deposited on top of the second channel layer 13.

Film J￥2 made of Ga+-z As (1<z<1)
Dope barrier Ji of about 00 people! 114 is deposited to form a stack, and this undoped barrier W! ! On the 14, an ohmic source electrode 15 and a drain electrode 16 made of AuGe, and a gate electrode 17 made of non-ohmic T i A II are provided between the two electrodes.
is configured.

FIG. 2 is an energy band diagram when the gate voltage is Ov in the FET according to the embodiment of the present invention. In the figure, 18
is a depletion layer. For other symbols, use the preceding ones. In this case, the depletion layer 18, which has no electrons, reaches as far into the first channel N12 doped with impurities.
In the channel it2, only a narrow region not reached by the depletion layer 18 serves as a current path, and electrons are scattered by impurities in this narrow region and have low mobility. The characteristics of the FET in this case are almost the same as those of the conventional embodiment, and are not suitable for high-speed operation.

However, when a large voltage of 10 is applied to the gate electrode 17, the characteristics of the energy band diagram in FIG. 2 are greatly improved. FIG. 3 is an energy band diagram when the gate voltage is high in the FET according to the embodiment of the present invention. That is, the depletion layer 18 disappears, electrons are accumulated in the second channel layer 13, and the characteristics of the FET are greatly improved in the Lugi band diagram.

FIG. 4 is a characteristic diagram of mutual conductance between the present invention and a conventional semiconductor. In the figure, the solid line represents the improvement effect on the figure of merit of the energy band of the embodiment of the present invention, and represents the mutual conductance with respect to the gate voltage. In the region where the gate voltage is high, a large mutual conductance is achieved due to the contribution of the second channel with high electron mobility. In contrast, in conventional embodiments, electron accumulation occurs between the channel layers doped with impurities, so the movement of electrons is slow due to impurity scattering and the source resistance is also large. Therefore, the mutual conductance is small as shown by the broken line. .

The above explanation is based on the first channel 12 and the second channel 13.
Although the same semiconductor material as GaAs is used as the first channel, the effect is also remarkable when GaAs is used for the first channel and InXGa1-XAs is used for the second channel. However, In, lGa1-X
Since the lattice constant of As is different from that of GaAs, it is desirable that X be in the range (0<x<0.4).

In another embodiment, the first channel is InXGa, -
8As (0,3<x<0.6) A similar effect is observed when In, Gap-y As (0,4<y<0°7) is used as the second channel. In this case, the barrier layer is In, Gap-, As, which have similar lattice constants.
(0,4<z<0.6), and the buffer layer is In
P or (nzAl!+-zAs is suitable.

The above explanation has been given for the case where the source electrode 15, drain electrode 16, and gate electrode 17 are formed directly on the barrier layer 14, but the effect also applies when the semiconductor layer for the surface protection film is deposited on the barrier layer. is remarkable.

〔Effect of the invention〕

As explained above, since the FET of the present invention can utilize high-mobility electrons induced in the channel layer that is not doped with impurities, the FET of the present invention can obtain a large mutual coductance, and is therefore suitable for high-frequency, high-speed operation. has advantages.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of an FET according to an embodiment of the present invention, FIG. 2 is an energy band diagram when the gate voltage is Ov in the FET according to an embodiment of the present invention, and FIG. 3 is a diagram showing the structure of an FET according to an embodiment of the present invention. An energy band diagram when the gate voltage is high in the FET of the example, FIG. 4 is a characteristic diagram of mutual conductance of the present invention and the conventional semiconductor, FIG. 5 is a cross-sectional view showing the structure of the conventional semiconductor, and FIG. The figure is an energy band diagram of a conventional semiconductor. 11 is an undoped buffer layer, 12 is a first channel layer, 13
1 is a second channel layer, 14 is an undoped barrier layer, 15 is a source electrode, 16 is a drain electrode, 17 is a gate electrode, 1
8 is a depletion layer, 21 is an undoped buffer layer, 22 is a channel layer doped with impurities, 24 is an undoped barrier layer, 25
26 is a source electrode, 26 is a drain electrode, 27 is a gate electrode, and 28 is a depletion layer. FIG. 1 is a sectional view showing the structure of the FET of the present invention. FIG. 2 is an energy band diagram. FIG. 6 is an energy band diagram of an embodiment of the present invention.

Claims (1)

[Claims] A first channel layer made of an n-type doped first semiconductor is formed on the substrate of the undoped buffer layer;
A second channel layer made of a second semiconductor having a sufficiently low impurity concentration is formed on the channel layer, and a third channel layer made of a second semiconductor having a sufficiently low impurity concentration and having an electron affinity smaller than that of the semiconductor of the second channel layer is further formed on the second channel layer. A field effect transistor characterized in that a barrier layer made of a semiconductor is deposited, and a source electrode, a drain electrode, and a gate electrode are provided on a stack of these layers.