JPH01221933A - Interference compensation circuit - Google Patents

Abstract

PURPOSE:To perform interference compensation even when the arrival direction of an interference signal coincides with that of a main signal by forming the interference signal by adding the main signals received by plural antennas with the same amplitude and negative phase via a variable coupler and an adder, etc., and using it. CONSTITUTION:A reception signal received by a first antenna 1 is separated to orthogonal components with the same phases by detectors 10 and 11, and are supplied to A/D converters 21, 21, and the reception signal of a second antenna 40 is also, separated to the orthogonal components with the same phases similarly, and are supplied to A/D converters 48 and 49. The output of the converter 48 is added on the output of the converters 22, 22 at the adders 54 and 56 via couplers 62 and 64, and similarly, the output of the converter 40 via the variable couplers 63 and 65 is added on the output of the adders 54 and 56 at the adders 55 and 57. The interference signal from which the main signal of the same phase and the orthogonal component is eliminated is formed from the adders 55 and 57 by those addition of the same amplitude and the negative phase, and by using the interference signal, it is possible to perform the interference compensation even when the arrival direction of the interference signal coincides with that of the main signal differently from a case where the antenna which receives the interference signal is used.

Description

DETAILED DESCRIPTION OF THE INVENTION r Industrial Field of Application J The present invention relates to an interference compensation circuit used in wireless communications.

"Conventional technology" An example of the configuration of a conventional interference compensation circuit is shown in FIG.

The signal received by the main antenna and tena 1 for receiving the main signal is passed through a bandpass filter 2 to improve the S/N as necessary, and then converted to an intermediate frequency band by frequency conversion g#3. . On the other hand, the interference signal received by the auxiliary antenna 4 for receiving the interference signal is passed through a band-pass filter 5 to improve the S/N ratio if necessary, and then frequency-converted using a local oscillator 7 common to the main signal. The signal is converted into an intermediate frequency band by the converter 6.

The main signal converted to the intermediate frequency is input to the demodulator 200. In the demodulator 200, the reference carrier wave 14 regenerated from the main signal is input to the quadrature phase detector 8.9, thereby performing quadrature phase detection.

This detection output is sent to the harmonic removal filter 15. '16 and extracted as in-phase and quadrature baseband signals.

On the other hand, the interference signal converted to the intermediate frequency band is input to a quadrature phase detector 10.11, is quadrature detected using the reference carrier 14 regenerated from the main signal, and is passed through a harmonic removal filter 17.18. After that, it is extracted as in-phase and quadrature baseband signals.

The in-phase and orthogonal baseband signals of the main signal and the interference signal are sent to A/D converters 19, 20, which have sufficient quantization accuracy,
Digitized by 21.22. Here, since digital processing is shown, an A/D converter is used.

If the main signal is a 16QAM signal, each A/D converter 19 to
The output of 22 becomes a four-value signal. Therefore, in order to output the error signal as a digital signal, sampling is performed using an A/D converter having an output of 3 bits or more. As a result, as shown in FIG. 10, a binary signal is obtained in which the upper two bits represent the identification result and the upper three bits represent the direction of the error. Note that the sampling signal of the A/D converters 19 to 22 is the clock signal 2 reproduced from the main signal.
Use 3.

The in-phase and quadrature components of the digitized interference signal are input to bipolar variable attenuators 28, 29, 30 and 31,
Adders 26, 27 and 24, 25 remove interference components mixed in the main signal components.

This control method involves detecting the correlation between the error signal remaining in the main signal and the interference signal, and controlling each bipolar variable attenuation 92B, 29.degree. 30, and 31 so that the influence thereof is minimized.

Specifically, the polarity signal on the in-phase side of the interference signal (this is
(obtained from the most significant bit of the D converter) and the error signal on the in-phase side of the main signal are multiplied by an exclusive OR circuit 34, and then passed through an integrator 37 that digitally integrates, and the output is used to calculate the interference signal in-phase. Bipolar variable attenuator 2 connected to the side
9, the polarity signal on the interference signal orthogonal side and the error signal on the main signal in-phase side are multiplied by an exclusive OR circuit 33, and then passed through an integrator 38 that integrates digitally, and the output is used to calculate the interference signal orthogonal. Bipolar variable attenuator 28 connected to the side
After multiplying the polarity signal on the in-phase side of the interference signal and the error signal on the orthogonal side of the main signal by the exclusive OR circuit 35,
Through an integrator 36 that integrates digitally, its output controls the bipolar variable attenuator 31 connected to the in-phase side of the interference signal, and the polarity signal on the side orthogonal to the interference signal and the error signal on the side orthogonal to the main signal are exclusively separated. After being multiplied by an OR circuit 32, the signal is passed through an integrator 39 that digitally integrates, and its output controls a bipolar variable attenuator 30 connected to the interference signal orthogonal side.

"Problem to be Solved by the Invention" In the conventional interference compensation circuit described above, an auxiliary antenna or the like is installed in a direction different from the main signal propagation path, and the interference signal that is the source necessary for interference compensation is transmitted to that antenna. I was getting it from. However, when the source interference signal cannot be obtained, such as when the propagation paths of the main signal and the interference signal are the same, there is a problem in that interference compensation is impossible.

The present invention was made against this background, and its object is to provide an interference compensation circuit that can compensate for interference even when a source interference signal cannot be obtained.

"Means for Solving the Problems" In order to solve the above problems, the present invention provides a main transmission line and a sub-transmission line for receiving a main signal, and a synthesis method for synthesizing the output signals of the main transmission line and the sub-transmission line. a first quadrature phase detector that decomposes the output of the combiner into an in-phase component and a quadrature component using a reference carrier recovered from the main signal;
second and third quadrature phase detectors that decompose the output signals of the main transmission line and the sub-transmission line into in-phase components and quadrature components;
, and first, second, third, fourth, fifth, and sixth A/D converters that sample and quantize the quadrature component output and the in-phase component output of the third quadrature phase detector, respectively; fifth and seventh variable couplers connected to the output of the fifth A/D converter; and sixth and eighth variable couplers connected to the output of the sixth A/D converter. and fifth and seventh full adders that add the outputs of the fifth and seventh variable couplers and the outputs of the fourth and third A/D converters, respectively; and the sixth and seventh full adders. sixth and eighth full adders that add the output of the eighth variable coupler and the output of the fifth and seventh full adders, respectively, to cancel the main signal and output an interference signal; first and third variable couplers connected to the outputs of the sixth full adder; second and fourth variable couplers connected to the outputs of the sixth full adder; first and third full adders that add the output of the third variable coupler and the outputs of the second and first A/D converters, respectively; and the second and fourth variable couplers. second and fourth full adders that add the output and the outputs of the first and third full adders, respectively, to cancel interference components included in the main signal; and the second and fourth full adders. a first variable coupler control circuit configured with a plurality of multiplier circuits and integrators that detect a correlation between an error signal obtained from the output of the adder and the output signals of the sixth and eighth full adders; , the outputs of the sixth and eighth full adders and the fifth and sixth full adders.
a second variable coupler control circuit constituted by a plurality of multiplier circuits and an integrator for detecting correlation between the output signal of the A/D converter of the first variable coupler control circuit; The output controls the first, second, third, and fourth variable couplers, respectively, and the output of the second variable coupler control circuit controls the fifth, sixth, seventh, and eighth variable couplers. It is characterized by controlling each variable coupler.

Further, a main transmission line and a sub-transmission line for receiving the main signal, a combiner that combines the output signals of the main transmission line and the sub-transmission line, and a reference carrier reproduced from the main signal, the output of the combiner is a first quadrature phase detector that decomposes into an in-phase component and a quadrature component, and a reference carrier that is the same as the first quadrature phase detector;
second and third quadrature phase detectors that decompose the output signals of the main transmission line and the sub-transmission line into in-phase components and quadrature components; fifth and seventh variable couplers, sixth and eighth variable couplers connected to the outputs of the in-phase components of the third quadrature phase detector, and outputs of the fifth and seventh variable couplers. and fifth and seventh adders that add the in-phase component output and quadrature component output of the second quadrature phase detector, respectively; 946 and an eighth adder that add the outputs of the adders No. 7 and 946, respectively, to cancel the main signal and output an interference signal; and the first and third adders connected to the output of the eighth adder. a variable coupler; second and fourth variable couplers connected to the outputs of the sixth adder; and outputs of the first and third variable couplers and the first quadrature phase detector. first and third adders that add in-phase component outputs and quadrature component outputs, respectively; and add outputs of the second and fourth variable couplers and outputs of the first and third adders, respectively. and second and fourth adders for canceling interference components contained in the main signal; and inputting the outputs of the second and fourth adders to an error signal generation circuit, and inputting the outputs of the second and fourth adders to an error signal generation circuit, and generating an output signal of the error signal generation circuit. and the output of the third quadrature phase detector and a first variable coupler control circuit configured by a plurality of multiplier circuits and integrators that detect the phase amount between the output signals of the sixth and eighth adders. and a second variable coupler control circuit configured by a plurality of multiplier circuits and an integrator that detect correlation between the output signals of the sixth and eighth adders, and the first variable coupler The output of the control circuit causes the first
, second, third, and fourth variable couplers, and the fifth and sixth variable couplers are controlled by the output of the second variable coupler control circuit.
, controlling the seventh and eighth variable couplers.

Note that in this specification, the main transmission path refers to the main antenna in wireless communication and the main transmission path in wired communication.
The sub-transmission path refers to the sub-antenna in wireless communication and the sub-transmission path in wired communication. The following description will be made using wireless communication as an example, but it can be similarly applied to wired communication.

"Operation" The present invention has a function of adding two systems of main signals received from a plurality of receiving antennas with mutually opposite phases and equal amplitudes,
The most important feature is that the added output is used as the interference signal of the conventional interference compensation circuit.

In this addition output, the main signal is significantly attenuated, and only the interference signal in the main signal remains. Therefore, interference compensation can be performed based on this added output signal.

Conventionally, it has been necessary to provide an auxiliary antenna in the interference direction that receives only the interference signal. Further, when the direction of interference signal propagation is the same as that of the main signal, it is impossible to obtain a highly pure interference signal and interference compensation is impossible.

"Example" Hereinafter, the present invention will be described in detail with reference to the drawings.

First Embodiment wc1 FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

In the figure, the main signal received by the main antenna 1 for main signal reception and the sub-antenna 40 is passed through band-pass filters 2 and 5 as necessary, and then processed using a local oscillator 7.
The frequency is converted into an intermediate frequency band by a frequency converter 3.6. Note that the phase shifter 41 inserted between the local oscillator 7 and the frequency converter 3 is connected to the main antenna 1 and the sub antenna 4.
It is used to vary the synthesis phase of the main signals received by 0, and is generally controlled so that the received power after synthesis is maximized.

The received signals of the main antenna 1 and the sub antenna 40 are combined by a combiner 42. This composite signal is input to first quadrature phase detectors 8 and 9, and is decomposed into in-phase and quadrature components by a reference carrier wave 14 regenerated from the main signal.

Further, the main antenna reception signal is transmitted to the second quadrature phase detector 1.
0.11, and is decomposed into in-phase and quadrature components by the reference carrier wave 14 mentioned above. - On the other hand, the received signal of the auxiliary antenna 40 is input to the third quadrature phase detector 43, 44, and is decomposed into in-phase and quadrature components by the reference carrier wave 14.

The in-phase and orthogonal components thus obtained are the first, second, and second components.
Third quadrature phase detector 8.9.10, 11.43.44
From, harmonic removal filters 15, 16.17.1B, 4
6.47, it is supplied to A/D converters 19, 20, 21, 22, 48, 49 with sufficient quantization accuracy and digitized. Note that these A/D converters 19 to
As the sampling signal of 22, 48, and 49, the clock signal 23 reproduced from the main signal is commonly used.

Eliminating the main signal component from the in-phase and quadrature components of the main signal output from the A/D converters 19 to 22, 48.49,
The circuit configuration for obtaining the interference signal is as follows.

The output signal of the fifth A/D converter 48 is input to the fifth and seventh variable couplers 62 and 64.
．． 64 and the output of the 4.3rd A/D converter 22.21 are respectively added by the 5.7th full adder 54.56.

Similarly, the output signal of the sixth A/D converter 49 is the output signal of the sixth A/D converter 49.
These outputs and the output of the full adder 54.56 are added by a 6.8 full adder 55.57.

From the outputs of these full adders 55 and 57, the main signal components of the in-phase and quadrature components are eliminated, and a signal alnaQ containing only interference components can be obtained. However, in this interference signal al+aQ, the main signal component is predominant at the time when interference compensation control is started, and as the control enters a steady state, the interference component increases.

Based on the interference signal aIT''Q, the interference component that has leaked into the main signal is canceled.

Therefore, the output signal of the eighth full adder 57, that is, the interference signal a0 of the orthogonal component is transmitted to the first and third variable coupler 58.
．． 60, the output of the variable coupler 58°60 and the second
．． The outputs of the No. 1 A/D converter 20.19 are added by the No. 1.3 full adder 50.52.

On the other hand, the output signal of the sixth full adder 55, that is, the in-phase component interference signal a, is transmitted to the 2.4th variable coupler 59.61.
The output of the variable coupler 59.61 and the output of the above-mentioned full adder 50.52 are input to the second and fourth full adder 5.
1.53, a compensation signal with the opposite phase and equal *i to the interference component mixed in the main signal system is created, and by adding this compensation signal to the interference component mixed in the main signal system, this interference component can be erased.

Next, a method of controlling the 1.2.3.4.5.6.7 and 8 variable couplers 5g, 59, 60, 61, 62, 63, 64, and 65 will be specifically described.

In order to eliminate the main signal and obtain only the interference signal, it is necessary to add the main signal received by the main antenna and the main signal received by the sub antenna with opposite phases and equal amplitudes.

Therefore, the variable couplers 62, 63,
Add through 64.65. In this case, the in-phase and quadrature component outputs after addition, ie, the outputs al+aQ of the full adders 55 and 57, must be controlled so that the main signal component is minimized.

To do this, correlation detection is performed between the main signal after addition and the output signal of the sub antenna or main antenna before addition, and the second variable coupler control circuit 67 detects the correlation between the main signal after addition and the output signal of the sub antenna or main antenna before addition. The variable couplers 82.63 and 64.65 are respectively feedback-controlled. Note that this figure shows an example in which correlation detection is performed using only the polar signal aQnal of the interference signal and the polar signals aQ, , al, of the main signal received by the sub antenna.

Based on the in-phase and quadrature component interference signals obtained above,
In order to cancel the interference component that has leaked into the main signal, the variable couplers 58, 59, 60, and 61 are controlled as described above.

In this case, the error signal eQ obtained from the output of the 2.4th full adder 51.53, that is, the main signal output after interference compensation
+el, and the output of the 6.8th full adder 55°57,
That is, the in-phase and quadrature components of the interference signal are input to the first variable coupler control circuit 66, correlation detection is performed between the two,
Feedback control is performed to minimize the amount.

For example, in the case of the 16QAM system, the error signal el+60 can be obtained from the third most significant bit, as shown in FIG. Note that here, an example has been shown in which correlation detection is performed using only the polarity signal a Q+ a l of the interference signal.

FIG. 2 shows the configuration of variable coupler control circuits 66 and 67.

In the figure, each error signal eQ+el and polarity signal a
Q+ a In aQ++ a In is multiplied by each of the four exclusive OR circuits 68, then integrated by an integrator 69, and output as control signals C1 to C4+ Cr (~Cr). Each variable coupler 58~
65 is controlled.

For example, when controlling the variable coupler 62, the polarity signal aQ+ of the main signal orthogonal component received by the sub antenna,
Control is performed using a control signal Cr obtained by performing correlation detection with the polarity signal a of the in-phase component of the interference signal. Regarding the other variable couplers 58 to 61 degrees 63 to 65, the corresponding correlation detection results C+"C, +Crz to Cr,
Control with. Here, as signals input to the variable coupler control circuit 67, the polarity signal al+aQ of the interference signal output from the adder 55.57 and the A/D converter 48.
Main signal polarity signal a g+1a l output from 49
Although an example using r is shown, it does not necessarily have to be a polar signal, and multi-bit input is also possible. In that case, a multi-bit multiplier may be used instead of the exclusive OR circuit in the variable coupler control circuit.

Second Embodiment FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

This embodiment is characterized in that the variable couplers 70 to 77 are constructed from delay lines with multiple taps (three-tap configuration in this example).

As a configuration example of the variable couplers 70 to 77, the variable coupler 70
The configuration is shown in Figure 4.

The variable coupler 70 includes a three-tap delay line 80 and bipolar variable attenuators 81, 82, . . . connected to each of these taps.
83 and an adder 84 that adds the outputs of the bipolar variable attenuators 81 to 83, and the amplitude of the signal input to the delay line 80 is adjusted and output from the adder 84. .

5 and 6 show the configuration of the variable coupler control circuits 78 and 79.

Each error signal eQ+els of the main signal and each polarity signal aQoal of the interference signal, or each polarity signal aQr* a of the main signal received by the sub antenna 40 8. +aQn
al is time-aligned by the delay line 80, correlated by the exclusive OR circuit 68, and the correlation output is input to the integrator 69 for integration.
2.73, 74, 75.76 and 77 are controlled.

In this way, by using a plurality of weighting circuits in the variable couplers 70 to 77, when the main signal and the interference signal have frequency characteristics, a larger compensation effect can be obtained compared to the first embodiment shown in FIG. .

Note that the delay adjustment line τ1 shown in FIG. 3 indicates that each signal passing through the quadrature phase detectors 8, 9 and 10. This is for time adjustment so that it is added at Similarly, the delay adjustment line τ2 is connected to the quadrature phase detector 10.1.
1 and the quadrature phase detectors 43 and 44, each signal passes through
This is for time adjustment so that the full adders 54, 55, 56, and 57 are added at the same time.

Third Embodiment In the first and second embodiments described above, the baseband signal is A/D converted and the interference compensation path is entirely constructed of digital circuits.

In contrast, in the present embodiment shown in FIG. 7, the interference compensation circuit is constructed from an analog circuit.

In FIG. 7, the main signal and interference signal received by the main antenna 1 and the auxiliary antenna 40 for receiving the main signal are passed through a band pass filter 2.5 as necessary, and then are processed using a local oscillator 7. Frequency conversion is performed by frequency converters 3 and 6 to an intermediate frequency band. Note that the phase shifter 41 inserted between the local oscillator 7 and the frequency converter 3 is connected to the main antenna 1.
and the combined phase of the received signals of the sub antenna 40 is varied.

Received signals from the main antenna 1 and the sub antenna 40 are combined by a combiner 42 and input to first quadrature phase detectors 8 and 9. The quadrature phase detectors 8 and 9 decompose the multiplexed signal into an in-phase component and a quadrature component using a reference carrier wave 14 regenerated from the main signal.

The received signal from the main antenna 1 is also input to the second quadrature phase detector 10.11, and is decomposed into an in-phase component and a quadrature component by the reference carrier 14. Furthermore, the received signal of the sub antenna 40 is transmitted to a third quadrature phase detector 43 .
44, and is decomposed into an in-phase component and a quadrature component by the reference carrier wave 14.

Quadrature phase detector 8, 9.10°11 of 1.2.3 above
．． Each output of 43 and 44 is passed through harmonic removal filters 15 and 1.
6.17, 18.46.47, respectively, and harmonics are removed. The output signal of the harmonic removal filter 46 is input to the fifth and seventh variable couplers 97.99, and the output of these variable couplers 97.99 and the output of the harmonic removal filter 18.17 are combined. is the 5.7th adder 89
．． 91 is added. Further, the output signal of the harmonic removal filter 47 is input to the 6.8th variable coupler 98, 100, and its output and the output of the adder 89.91 are
are added by adders 90 and 92, and interference signals mixed in the main signal are extracted.

The output signal of the adder 92 is input to the first and third variable couplers 93.95, and these variable couplers 93.95
and the output of the harmonic removal filter 16°15 are the first
．． 3 adders 85 and 87. Further, the output signal of the adder 90 is transmitted to the second and fourth variable couplers 94 and 96.
The outputs of these variable couplers 94.96 and the outputs of adders 85.87 are input to the second and fourth adders 86.88.
The interference components mixed in the main signal are eliminated.

Above 1.2.3.4.5.6.7 and 8 variable combination 9
3. Control of 94, 95, 96, 97, 98, 99, and 100 is performed as follows.

That is, the outputs of adders 88 and 86 are input to error signal generation circuits 101 and 102, and the outputs of adders 92 and 90 are input to error signal generation circuits 101 and 102.
The output of
error signal eQ+el, polarity signal aQnal of interference signal,
A polarity signal aQ++alt of the main signal is formed, and an error signal e
. +el and the polarity signal aQ+al of the interference signal are input to the first variable coupler control circuit 66, and the polarity signal aQ of the interference signal is inputted to the first variable coupler control circuit 66.
nal and the polarity signal aQ++al+ of the main signal are input to the second variable coupler control circuit 67. Then, the outputs of the variable coupler control circuits 66 and 67 control the variable couplers 93 to 67.
100 controls. Here, the error signal generation circuit 1
01, 102, and the binary discrimination circuits 103 to 106 are operated by the clock signal 23 reproduced from the main signal.

Note that the adders 90, 92 . and harmonic removal filter 4
6.47 output signal to the identification circuits 103, 104, 10
Although an example has been shown in which the data is passed through 5,106 pixels and binarized, binarization is not necessarily necessary.

In that case, an analog multiplier may be used instead of the digital multiplier (exclusive OR) in the variable coupler control circuit.

Fourth Embodiment FIG. 8 is a block diagram showing the configuration of a fourth embodiment of the present invention. This embodiment differs from the third embodiment shown in FIG. 7 in that the variable couplers 107 to 114 are constructed from delay lines with multiple taps (three-tap configuration in this example). . That is, in this embodiment, the variable coupler 10
7,108,109゜110.111,112,113
, 114, a variable coupler having the configuration shown in FIG. 4 is used.

"Effects of the Invention" As explained above, the interference compensation circuit of the present invention is configured to extract the interference component mixed in the main signal component and use it as an interference signal, so even when the interference signal from the outside cannot be secured. , has the function of extracting the interference signal by itself and performing interference compensation based on it.

Therefore, even if the propagation path of the interference signal is the same as that of the main signal, there is an advantage of having a large interference compensation effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention,
FIG. 2 is a block diagram showing the configuration of the variable coupler control circuit;
FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention;
Fig. 4 is a block diagram showing the configuration of the variable coupler, Fig. 5.6
The figure is a block diagram showing the configuration of the variable coupler control circuit.
The figure is a block diagram showing the configuration of the third embodiment of the present invention.
The figure is a block diagram showing the configuration of the fourth embodiment of the present invention.
The figure is a block diagram showing the configuration of a conventional interference compensation circuit.
The θ diagram is an explanatory diagram of a level diagram of a four-value identification circuit (A/D converter). l...Main antenna, 2.5...Band pass filter, 3.6...Frequency converter, 4...
...Auxiliary antenna, 7...Local oscillator, 8.9,10.11...Quadrature phase detector, 12
．． 13... 90 degree phase shifter, 14... Reference carrier wave, 15.16, 17.18... Harmonic removal filter, 19.20, 21.22... ...A/D converter, 23...Clock signal, 24, 25, 26.27...Adder, 28.2
9,30.31... Bipolar variable attenuator, 32.
33, 34.35...Exclusive OR, 36.3
7, 38. 39... Integrator, 40...
Sub-antenna, 41... Phase shifter, 42...
・Synthesizer, 43.44...Quadrature phase detector, 4
5... 90 degree phase shifter, 46.47... Harmonic removal filter, 48.4
9...A/D converter, 50.51, 52, 53
, 54, 55, 56.57...Full adder, 5g, 59, 60, 61, 62, 63.64.65...
...Variable coupler, 66.67...Variable coupler control circuit, 68...
...Exclusive OR, 69...Integrator, 70
．． 71, 72, 73, 74, 75, 76.77...
...Variable coupler, 78.79...Variable coupler control circuit, 80...
...Delay line, 81.82.83...Bipolar variable attenuator, 84
・・・・・・Adder, 85.86, 87, 88, 89, 90, 9 1.92・
... Adder, 93.94, 95, 96, 97, 98, 99, 100-
...Variable coupler, 101.102...Error signal generation circuit, 103
．． 104, 105, 106... binary identification circuit,
107.108,109,110,111.1'12゜113.114...Variable coupler, 200...
...Demodulator. Applicant Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] (1) A main transmission line and a sub-transmission line for receiving the main signal, a combiner that combines the output signals of the main transmission line and the sub-transmission line, and an output of the combiner using a reference carrier reproduced from the main signal. a first quadrature phase detector that decomposes
second and third quadrature phase detectors that decompose the output signals of the main transmission line and the sub-transmission line into in-phase components and quadrature components;
, and first, second, third, fourth, fifth, and sixth A/D converters that sample and quantize the quadrature component output and the in-phase component output of the third quadrature phase detector, respectively; fifth and seventh variable couplers connected to the output of the fifth A/D converter; and sixth and eighth variable couplers connected to the output of the sixth A/D converter. and fifth and seventh full adders that add the outputs of the fifth and seventh variable couplers and the outputs of the fourth and third A/D converters, respectively; and the sixth and seventh full adders. sixth and eighth full adders that add the output of the eighth variable coupler and the output of the fifth and seventh full adders, respectively, to cancel the main signal and output an interference signal; first and third variable couplers connected to the outputs of the sixth full adder; second and fourth variable couplers connected to the outputs of the sixth full adder; first and third full adders that add the output of the third variable coupler and the outputs of the second and first A/D converters, respectively; and the second and fourth variable couplers. second and fourth full adders that add the output and the outputs of the first and third full adders, respectively, to cancel interference components included in the main signal; and the second and fourth full adders. a first variable coupler control circuit configured with a plurality of multiplier circuits and integrators that detect a correlation between an error signal obtained from the output of the adder and the output signals of the sixth and eighth full adders; , the outputs of the sixth and eighth full adders and the fifth and sixth full adders.
a second variable coupler control circuit constituted by a plurality of multiplier circuits and an integrator for detecting correlation between the output signal of the A/D converter of the first variable coupler control circuit; The output controls the first, second, third, and fourth variable couplers, respectively, and the output of the second variable coupler control circuit controls the fifth, sixth, seventh, and eighth variable couplers. An interference compensation circuit characterized in that each variable coupler is controlled. (2) A main transmission line and a sub-transmission line for receiving the main signal, a combiner that combines the output signals of the main transmission line and the sub-transmission line, and an output of the combiner using a reference carrier reproduced from the main signal. a first quadrature phase detector that decomposes
second and third quadrature phase detectors that decompose the output signals of the main transmission line and the sub-transmission line into in-phase components and quadrature components; fifth and seventh variable couplers; sixth and eighth variable couplers connected to the outputs of the in-phase components of the third quadrature phase detector; and outputs of the fifth and seventh variable couplers. and fifth and seventh adders that add the in-phase component output and quadrature component output of the second quadrature phase detector, respectively; 6th and 8th adders that add the outputs of the 7th adder to eliminate the main signal and output an interference signal; and 1st and 3rd adders connected to the output of the 8th adder. a variable coupler, second and fourth variable couplers connected to the output of the sixth adder, and outputs of the first and third variable couplers and the first quadrature phase detector. first and third adders that add the in-phase component output and quadrature component output of , respectively; and the outputs of the second and fourth variable couplers and the outputs of the first and third adders, respectively. second and fourth adders that add and cancel interference components included in the main signal; outputs of the second and fourth adders are input to an error signal generation circuit; and the output of the error signal generation circuit is a first variable coupler control circuit configured by a plurality of multiplier circuits and an integrator that detect a correlation between the signal and the output signals of the sixth and eighth adders; and the output of the third quadrature phase detector. and a second variable coupler control circuit configured by a plurality of multiplier circuits and an integrator for detecting correlation between the output signals of the sixth and eighth adders, and the first variable coupler The first, second, third, and fourth variable couplers are controlled by the output of the control circuit, and the fifth, sixth, seventh, and eighth variable couplers are controlled by the output of the second variable coupler control circuit. An interference compensation circuit characterized by controlling a variable coupler of.