JPH0654890B2 - Interference compensation circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an interference compensation circuit that cancels interference from other systems in a digital wireless system.

"Prior Art" FIG. 13 shows a configuration example of a conventional interference compensation circuit (for example, Japanese Patent Application No. 60-287881).

In the figure, the main signal (here, a digital signal is considered) received from the main antenna 1 for receiving the main signal receives interference from another system. The received signal is passed through the bandpass filter 2 as required, and then frequency-converted into an intermediate frequency band by the frequency converter 3.

On the other hand, for the signal that is the source of interference, the auxiliary antenna 6
After receiving 0 by directing 0 toward the interference source and passing it through a bandpass filter 5 for improving S / N as necessary, a frequency converter 6 using a local oscillator 7 common to the main signal is used. The frequency is converted to the intermediate frequency band by.

A circuit 16 for varying the phase and amplitude of the interference signal,
The opposite phase of the interference component leaked into the main signal through 18
An interference component is eliminated by creating a compensation signal of equal amplitude and adding it to the main signal by the adder 19.

In order to control the variable phase circuit 16 and the variable amplitude circuit 18, first, the adder 19 adds the signals, and then the added signals are passed to the demodulator 120 to detect the in-phase and quadrature components of the remaining interference components. This signal is detected by the quadrature phase detection circuits 30 and 31 using the reference carrier wave 34 reproduced from the main signal, and decomposed into the in-phase component and the quadrature component.
These signals are passed through the harmonic elimination filters 32 and 33 and then passed through the error signal generation circuits 130 and 131 for detecting the residual interference component, and the error signals of the in-phase component and the quadrature component are obtained.

On the other hand, the interference signal, after passing through the variable phase circuit 16, is divided into two by the distributor 17, one of which is sent to the variable amplitude circuit 18 described above, and the other decomposes the interference signal into an in-phase component and a quadrature component. Are input to the quadrature phase detectors 41 and 42. Here, the reference carrier wave 34 is the same as the main signal demodulator 120. The interference signal divided into the in-phase component and the quadrature component passes through the harmonic elimination filters 43 and 44, and is then binarized through the identification circuits 45 and 46. These identification circuits 45 and 46 perform binarization using the timing signal obtained by the main signal demodulator 120. Since the case where digital processing is performed is shown here, an identification circuit for binarization is required, but when performing analog processing, this circuit is unnecessary.

An A / D converter may be used when outputting the outputs of the error signal generating circuits 130 and 131 as digital signals. For example, when the main signal is a 16QAM signal, the demodulated signal is a four-valued signal, and therefore, A having an output of 3 bits or more
By sampling with the / D converter, as shown in FIG. 14, a binary signal in which the upper 2 bits represent the identification result and the upper 3 bits represent the direction of the error is obtained. Therefore,
This upper 3rd bit can be used as an error signal. The most significant bit of the upper 2 bits is a polarity signal.

When the in-phase and quadrature component error signals and the in-phase and quadrature component interference signals are obtained in this way, correlation detection is performed between them.

That is, the exclusive OR of the quadrature components or the in-phase components is taken by the exclusive OR circuits 70 and 71, and the output thereof is passed through the integrator 77 through the resistors 65 and 66, so that the variable amplitude circuit 18 becomes Get control signal. The exclusive OR circuit 72 calculates the exclusive OR of the in-phase component and the quadrature component.
In addition, the exclusive inversion OR of the quadrature component and the in-phase component is obtained by the exclusive inversion OR circuit 73, and these signals are passed through the integrator 76 via the resistors 67 and 68 to control the variable phase circuit 16. Get the signal.

[Problems to be Solved by the Invention] In the above-described conventional interference compensation circuit, the interference signal required for interference compensation is installed from the antenna by installing an auxiliary antenna or the like in a direction different from the main signal propagation path. I was getting.

However, when the propagation paths of the main signal and the interference signal are the same, a high-purity interference signal as a source cannot be obtained, and there is a problem that interference compensation becomes impossible.

The present invention has been made under such a background, and an object thereof is to provide an interference compensation circuit capable of performing interference compensation even when a source interference signal is not obtained.

[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a main transmission line and a sub transmission line for receiving a main signal, and a reception signal of the main transmission line and the sub transmission line. A combiner of 1 and a variable amplitude circuit and a variable phase circuit, or a quadrature amplitude modulator, and is supplied with a reception signal of one of the reception signals of the main transmission line and the sub transmission line. And an amplitude / phase adjusting circuit, a second combiner for combining the output of the first amplitude / phase adjusting circuit and a received signal received by the other transmission line, and the second combiner. A first control circuit for controlling the first amplitude / phase adjusting circuit so that the two main signals have opposite phases and equal amplitudes; and a variable amplitude circuit and a variable phase circuit, or a quadrature amplitude modulator. , A second to which the output of the second combiner is supplied Amplitude / phase adjusting circuit, a third combiner for combining the output of the second amplitude / phase adjusting circuit and the output of the first combiner, and the main output from the third combiner. A second control circuit for controlling the second amplitude / phase adjusting circuit so that the interference component in the signal is minimized.

The main transmission line and the sub transmission line for receiving the main signal, the automatic gain control circuits to which the received signals of the main transmission line and the sub transmission line are respectively supplied, and the outputs of the two automatic gain control circuits are connected. A phase control circuit that detects a phase difference from the received signals of the main transmission line and the sub transmission line and outputs phase control information, and is connected to the output of one of the two automatic gain control circuits.
A phase shifter that makes the received signals of the main transmission line and the sub transmission line in phase by the output of the phase control circuit, and the output of the phase shifter and the other automatic gain control circuit of the two automatic gain control circuits A distributor for respectively distributing the output of the distributor and a distributor for connecting the output of the distributor connected to the phase shifter and the output of the distributor connected to the other automatic gain control circuit.
And a first variable amplitude controlled by an output of a differential amplifier to which outputs of a divider connected to the phase shifter are input, and to which control voltages of the two automatic gain control circuits are input. A circuit, a second combiner for combining the output of the distributor connected to the other automatic gain control circuit and the output of the first variable amplitude circuit by shifting their phases by 180 °, and A first variable phase circuit having an output of the second combiner as an input; a second variable amplitude circuit having an output of the first variable phase circuit as an input; an output of the first combiner; A third combiner for combining the signals passed through the first variable phase circuit and the second variable amplitude circuit, and a reference carrier wave obtained by reproducing the main signal output from the third combiner from the main signal. And a quadrature phase detector that decomposes into an in-phase component and a quadrature component, And two error signal generating circuits each having a quadrature component as an input, a phase detector for phase-detecting the output signal of the first variable phase circuit with the same reference carrier as the quadrature phase detector, and an exclusive OR circuit And two integrators, each of which independently detects the correlation between the output of the phase detector and the output of the two error signal generating circuits, and an output related to the in-phase component of the outputs. And a correlation detection circuit for controlling the first variable phase circuit by the output related to the quadrature component.

Further, a main transmission line and a sub transmission line for receiving the main signal, a first combiner for synthesizing the reception signals of the main transmission line and the sub transmission line, and a reception signal of the main transmission line and the sub transmission line are distributed. And a first amplitude / phase adjusting circuit for adjusting the amplitude / phase of the output signal of one of the two distributors as an input signal, and the first amplitude / phase adjusting circuit. A second combiner for combining the output signal of the circuit and the output signal of the other distributor of the two distributors, and the amplitude and phase of the output signal of the second combiner as an input signal A second amplitude / phase adjusting circuit, a third combiner for combining the output signal of the second amplitude / phase adjusting circuit and the output of the first combiner, and the two distributors. The output signal of the other distributor of
A first quadrature phase detector that performs quadrature phase detection using a carrier wave regenerated from the output signal of the third combiner, and a phase detector that detects the output signal of the second combiner using the carrier wave A first correlation detection circuit for detecting a correlation between the output signal of the phase detector and the output signal of the first quadrature phase detector having the same phase relationship with the output signal of the phase detector; and the output signal of the phase detector. A second correlation detecting circuit for detecting a correlation between the output signals of the first quadrature phase detector having a quadrature relationship with the output signal of the third combiner; A second quadrature phase detector, two error signal generating circuits each having an in-phase signal and a quadrature component signal of the output of the second quadrature phase detector as input signals, and an output of the in-phase side error signal generating circuit Signal and the phase in phase with it Correlation detection between a third correlation detection circuit that performs correlation detection with the output signal of the wave detector, an output signal of the quadrature-side error signal generation circuit, and an output signal of the phase detector that is in an orthogonal relationship with the detection signal. And a fourth correlation detecting circuit for controlling the first amplitude / phase circuit by the first and second correlation detecting circuits, and outputting the output signals from the third and fourth correlation detecting circuits. It is characterized by controlling the second amplitude / phase circuit.

In this specification, the main transmission line refers to the main antenna in wireless communication and the main transmission line in wired communication, and the sub transmission line refers to the sub antenna in wireless communication and the sub transmission line in wired communication. And In the following description, wireless communication will be described as an example, but it can be similarly applied to wired communication.

"Operation" The present invention, the main signal received from a plurality of receiving antennas,
It has a function of synthesizing with mutually opposite phases and equal amplitudes, and the most main feature is to use an interference signal of high purity output from the synthesizer as an interference signal of an interference compensation circuit.

In this case, the phase difference between the main signal and the interfering signal received by one receiving antenna and the phase difference between the main signal and the interfering signal received by the other receiving antenna are usually different in magnitude. Even if is canceled, the interference signal remains.

That is, the main signal is significantly attenuated at the output of the second combiner, and an interference signal in which only the interference component in the main signal remains is obtained, and interference compensation can be performed based on this interference signal.

Conventionally, it is necessary to provide an auxiliary antenna in the interference direction so as to receive only the interference signal. Further, when the incoming direction of the interference signal is in the same direction as the main signal, it is impossible to obtain a highly pure interference signal and it is impossible to perform interference compensation. However, the interference compensation circuit according to the present invention is used. Can solve these problems.

[Examples] Examples of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

In the figure, the receiving antennas of the main antenna 1 and the sub-antenna 4 are directed to the main signal (digital signal) transmission source. In this case, since the interference source is also in the same direction, the interference signal is simultaneously received in addition to the main signal, which causes interference.

In many cases, the space diversity method is adopted in the normal digital wireless method, and in that case, 2
The reception signals of the main antenna 1 and the sub-antenna 4 are input to the first combiner 10 and combined by using one antenna.

Hereinafter, a method of extracting an interference signal mixed in the main signal will be described.

The received signal of the main antenna 1 is distributed to the second combiner 1
Enter one of the four inputs. Similarly, the reception signal of the sub antenna 4 is also distributed, passes through the first variable amplitude circuit 11 and the first variable phase circuit 12, and enters the other input of the second combiner 14.

Here, in order to extract the interference signal from the output of the combiner 14, the main signal may have opposite phase and equal amplitude at one and the other inputs of the combiner 14. Therefore, the sub antenna 4
The relative amplitude and phase difference between the received signal distributed from the main antenna 1 and the received signal distributed from the main antenna 1.
The first variable amplitude circuit 11 and the first variable phase circuit 12 may be controlled by the detection by the output signal 41. As a result, from the output of the combiner 14, it is possible to extract the interference signal in which the main signal is canceled and remains.

A method of canceling the interference signal mixed in the main signal based on the interference signal extracted as described above will be described.

The interference signal output from the combiner 14 passes through the second variable amplitude circuit 18 and the second variable phase circuit 16 and enters one of the inputs of the third combiner 19. In addition, the first synthesizer 10
The received signal output from the above enters the other input of the combiner 19. Here, in order to cancel the interference signal from the output of the combiner 19, it is sufficient if the interference signal has a condition of opposite phase and equal amplitude at one and the other of the inputs of the combiner 19.

Therefore, the relative amplitude difference and phase difference between the interference signal output from the second combiner 14 and the interference component in the main signal output from the first combiner 10 are determined by the second control circuit 14
From 0, the second variable amplitude circuit 18 and the second variable phase circuit 16 may be controlled so that the interference signal and the interference component have equal amplitude and opposite phase.

As described above, it is possible to automatically extract the interference signal mixed in the main signal, and automatically perform the interference compensation based on the interference signal.

The specific configurations of the control circuits 140 and 141 will be described in the third and subsequent embodiments.

Second Embodiment FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention.

In the figure, the main antenna 1 and the sub-antenna 4 are directed to the transmission source of the main signal (digital signal), but are subject to interference.

In many cases, the space diversity method is adopted in the normal digital wireless method, and in that case, 2
Only one antenna should be used.

The signals received by both antennas 1 and 4 are S / S as required.
After passing through the band pass filters 2 and 5 for improving N, they are converted into intermediate frequency bands by the frequency converters 3 and 6 using the common local oscillator 7.

The signals converted to the intermediate frequency band are passed through automatic gain control circuits 61 and 62, respectively, and both outputs have equal amplitude. Of the outputs having the same amplitude, the output of the automatic gain control circuit 61 is supplied to the distributor 8 and the phase control circuit 86, and the output of the automatic gain control circuit 62 is supplied to the distributor 9 via the variable phase circuit 64.
And the phase control circuit 86.

The phase of the variable phase circuit 64 is adjusted by the phase control circuit 86, and the outputs of the distributors 8 and 9 have the same phase and are supplied to the first combiner 10.

In addition, the constituent elements 1 to 10 and 61, 62, 64,
The in-phase synthesis circuit 100 is configured by 86.

Next, the interference signal leaked into the main signal is extracted as follows.

First, the control voltages of the two automatic gain control circuits 61 and 62 are input to the differential amplifier 63, and the output thereof outputs the distributor 9
The variable amplitude circuit 11 connected to is controlled, and the output of the variable amplitude circuit 11 and the output of the distributor 8 are made equal in amplitude. Since the output of the variable amplitude circuit 11 and the output of the distributor 8 are adjusted to have the same phase, they can be realized by inputting each to the 180 ° combiner 14 (second combiner) for reverse phase combination. The 180 ° combiner 14 outputs only an interference signal in which the main signal is canceled in the opposite phase.

Using this interference signal, the interference component remaining in the main signal combined in phase by the combiner 10 is eliminated.

That is, the interference signal obtained above is sequentially input to the first variable phase circuit 16 for controlling the phase and the second variable amplitude circuit 18 for controlling the amplitude, and the output of the variable amplitude circuit 18 and the first combination. The output of the device 10 is combined by the third combiner 19.

Here, since the output signal of the variable amplitude circuit 18 is controlled so as to have almost the opposite phase and equal amplitude to the interference component leaked into the main signal output from the first combiner 10, the combination is performed. At the output of the container 19, the interference component is eliminated.

In this case, it is necessary to match the delay times of the two main signals in the second combiner 14 that combines the two main signals with opposite phases and equal amplitudes.

The control method of the above-mentioned first variable phase circuit 16 and second variable amplitude circuit 18 will be described below.

The main signal combined by the combiner 19 is demodulated by the demodulator 120.
Entered in. The demodulator 120 uses the reference carrier wave 34 regenerated from the main signal, performs quadrature detection of the main signal by the quadrature phase detectors 30 and 31, and passes the output signals to the low-pass filters 32 and 33, respectively, to obtain the in-phase signal. And a quadrature baseband signal. The obtained baseband signals are input to the error signal generation circuits 130 and 131, respectively. The error signal generation circuits 130 and 131 are respectively composed of identification circuits 37 and 38 and subtractors 39 and 40 that take the difference between the input and output thereof, and these subtractors 39 and 40.
Outputs an error signal.

When using a 16QAM signal as the main signal,
An A / D converter of 3 bits or more may be used as the error signal generating circuit. When 16QAM is demodulated, a 4-valued baseband signal is obtained. When the 4-valued signal is passed through an identification circuit (A / D conversion circuit) having an output of 3 bits or more, as shown in FIG. Of the outputs, the upper 2 bits are the identification signal and the upper 3 bits are the error signal.
An error signal can be obtained from the upper 3rd bit.

On the other hand, the variable phase circuit 1 is output from the second combiner 14.
6. The interference signal that has passed through the distributor 17 is phase-detected by the phase detector 41 using the reference carrier 34 described above, and is passed through the low-pass filter 43 that removes harmonic components.
The signal is passed through the identification circuit 45 and binarized to obtain a binary interference signal. In addition, the identification circuit 45 uses the main signal demodulator 120.
The binarization operation is performed using the clock signal 36 reproduced in step 1.

Next, correlation detection is performed between the in-phase and quadrature component error signals obtained by the main signal demodulator 120 and the binarized interference signal. That is, the error signal of the in-phase component and the interference signal are passed through the exclusive OR circuit 71 to be digitally multiplied, and the output thereof is integrated by the integrator 77, and the variable amplitude circuit 18 is controlled by the output. On the other hand, the error signal of the quadrature component and the interference signal are passed through the exclusive OR circuit 70 to be digitally multiplied, the output thereof is integrated by the integrator 76, and the variable phase circuit 16 is controlled by the output signal. The control circuit 140 is configured by these constituent elements 70, 71, 76, 77.

In this way, interference compensation can be automatically performed. Here, the binary multiplication by the exclusive OR circuits 70 and 71 is shown as an example, but the binarization circuit of the interference signal is not always necessary. In that case, the exclusive OR circuit is replaced by the analog multiplication circuit. You can use a vessel.

Third Embodiment FIG. 3 is a block diagram showing the configuration of the third embodiment of the present invention.

The main difference of this embodiment from the second embodiment shown in FIG. 2 is the configuration of the in-phase combining circuit 100 and the first control circuit 14.
This is the point where 1 is provided. The configuration of the second control circuit 140 is similar to that of the second embodiment.

In the second embodiment shown in FIG. 2, in the in-phase combining circuit 100 for aligning the phases of the received signals from the main antenna 1 and the sub antenna 4, the control voltages for making the outputs of the automatic gain control circuits 61 and 62 constant are applied. It is input to the differential amplifier 63 and adjusted in advance so that the output has the same amplitude.
The interference signal was obtained by canceling the main signal by the combiner 14, but in the present embodiment shown in FIG. 3, the first variable amplitude circuit 11 and the variable phase circuit 12 for adjusting the amplitude and phase of the main signal are used. Are prepared so that the signals received by the two antennas 1 and 4 have the same amplitude and opposite phase to each other.
Feedback control of 1 and 12 is performed.

This feedback control is performed as follows.
The two main signals received by the two antennas 1 and 4 are
In the second combiner 14, the signals are combined so that they have opposite phases and equal amplitudes, and correlation detection is performed between the main signal remaining after combination and one of the two main signals before combination. , The amplitude and phase of the other main signal are controlled by the above-mentioned first variable amplitude circuit 11 and variable phase circuit 12 so that the amount of correlation is minimized, that is, the residual main signal is minimized. . As a result, the main signal remaining after combining can be minimized at all times.

Regarding the main signal remaining after the above-mentioned combination, the main signal is dominant at the time when the interference compensation operation is started, but as the interference compensation operation progresses to the steady operation, the interference component contained in the main signal is It emerges, and this is output as an interference signal from the combiner 14.

Specifically, using the reference carrier wave 34 regenerated by the main signal demodulator 120, the output of the combiner 14, that is, the interference signal remaining after the main signal is erased, is phase-detected by the phase detector 42, and then the higher harmonic wave is detected. Low-pass filter 4 for removing components
4 and outputs the output of the filter 44 to the main signal demodulator 1
Using the clock signal 36 reproduced in 20, the discrimination circuit 4
6 is binarized to obtain a binarized interference signal.

Further, the distributor 13 distributes the signal received by the sub-antenna 4, and inputs the signal to the quadrature phase detector 121 which decomposes the signal into the in-phase component and the quadrature component. This input is
The phase is detected by the phase detectors 48 and 49 using the reference carrier wave 34, passed through the low-pass filters 50 and 51 for removing harmonic components, and then binarized by the discrimination circuits 52 and 53 to be binary. The main signals of the converted in-phase component and quadrature component are obtained. The discrimination circuits 52 and 53 are supplied with the clock signal 36 reproduced by the main signal demodulator 120, and binarized by this.

The main signal of the in-phase component obtained from the discriminating circuit 53 and the residual main signal (interference signal) output from the discriminating circuit 46 having a relatively in-phase relationship with this are digitally multiplied by the exclusive OR circuit 79. The result is integrated by the integrator 85, and the output of the integrator 85 controls the variable amplitude circuit 11.

Similarly, the main signal of the quadrature component output from the identification circuit 52 and the residual main signal (interference signal) output from the identification circuit 46, which is in a relatively orthogonal relationship with this, pass through the exclusive OR circuit 78. Digital multiplication is performed, and the result is integrated by the integrator 84, and the output of the integrator 84 controls the variable phase circuit 12.

The components 78, 79, 84, 85 form the control circuit 141. It goes without saying that the identification circuits 46, 52 and 53 for binarization are not always necessary.

As described above, the interference signal leaked into the main signal can be automatically extracted and canceled. In this case, the delay times of the two main signals need to be adjusted in the combiner 14 so that they match.

Fourth Embodiment FIG. 4 is a block diagram showing the structure of the fourth embodiment of the present invention.

The fourth embodiment differs from the third embodiment shown in FIG. 3 in that a phase detector (phase detector 42 shown in FIG. 3) for extracting an interference signal from a signal obtained by combining the main signals, The common phase detector 41 is used for the phase detector (phase detector 41 in FIG. 3) for obtaining the interference signal for canceling the interference component in the main signal. There is an advantage that simplification can be realized.

The control method of the variable amplitude circuits 11 and 18 and the variable phase circuits 12 and 16 is the same as that of the third embodiment.

Fifth Embodiment FIG. 5 is a block diagram showing the configuration of the fifth embodiment of the present invention.

This embodiment is different from the fourth embodiment in FIG. 4 in that when the amplitude and phase of the main signal and the amplitude and phase of the interference signal are controlled, the variable amplitude circuit and the variable phase circuit are used in the fourth embodiment. Although they have been used respectively, in the present embodiment, the point is that a quadrature amplitude modulator is used.

That is, in the fourth embodiment, the integrators 84, 85, 76,
By the correlation output from 77, the variable amplitude circuits 11, 18,
Although the variable phase circuits 12 and 16 are controlled respectively, the same function can be achieved by using the quadrature amplitude modulators 110 and 111 instead of them.

The quadrature amplitude modulator 110 divides an amplitude of a divider 20 for dividing an input signal, a 90 ° phase shifter 21 for shifting one of the outputs of the divider 20 by 90 degrees, and an output of the phase shifter 21. The π / 2-phase bipolar variable attenuator 22 for adjustment, the 0-phase bipolar variable attenuator 23 for adjusting the amplitude of the other output of the distributor 20, and the outputs of the bipolar variable attenuators 22, 23 are combined. And a synthesizer 24 that operates.

Similarly, the quadrature amplitude modulator 111 also includes the distributors 25 and 90.
The transporter 26, the bipolar variable attenuators 27 and 28, and the combiner 29 are included.

Then, the 0-phase bipolar variable attenuator 23 in the quadrature amplitude modulator 110 is controlled by the output of the integrator 85 of the first control circuit 141, and the π / 2-phase bipolar variable attenuator 22 is integrated by the integrator 84. It is controlled by the output of.

Similarly, the 0-phase bipolar variable attenuator 28 and the π / 2-phase bipolar variable attenuator 27 in the other quadrature amplitude modulator 111 also have the second
Are controlled by the outputs of the integrator 77 and the integrator 76 in the control circuit 140.

Sixth Embodiment FIG. 6 is a block diagram showing the structure of the sixth embodiment of the present invention.

The sixth embodiment differs from the fifth embodiment shown in FIG. 5 in that the exclusive logic circuit is not used for the correlation detection and the multiplier 9 is used.
The point is that the control gain is increased by performing analog multiplication using 1, 92, 93 and 94.

Seventh Embodiment FIG. 7 is a block diagram showing the configuration of the seventh embodiment of the present invention.

The seventh embodiment differs from the fifth embodiment shown in FIG. 5 in that the error signal generating circuits 130 and 131 and the discrimination circuit 4 are different.
Instead of 5, 52, 53, A / D converters 55, 56,
57, 58, and 59 are used.

When 16QAM is considered as the main signal, when an A / D converter having an output of 3 bits or more is used as shown in FIG. 14, the upper 2 bits of the output indicate the discrimination result, and the upper 3 bits. Represents an error signal. Therefore, the error signal can be taken out from the upper 3rd bit.

The A / D converters 55 to 59 are sampled using the clock signal 36 reproduced by the main signal demodulator 120. Then, the upper first bit (polarity signal) of the output of the A / D converter 57 that converts the baseband signal of the interference signal into a digital signal and the upper third bit (error of the A / D converters 55 and 56 (error Signal), and the bipolar variable attenuators 27 and 28 of the quadrature amplitude modulator 111 are controlled by the correlation signal. This makes it possible to eliminate the interference signal.

On the other hand, the A / D converters 58 and 59 of the quadrature phase detector 121 connected to the output of the distributor 13 of the main signal output the upper first bits (polarity signal) of the quadrature component and the in-phase component, respectively. Correlation detection is performed between the high-order first bit and the high-order first bit of the A / D converter 57, and the bipolar signals of the quadrature amplitude modulator 110 are controlled by the correlation signal.
3 is controlled, and the interference signal leaked into the main signal is extracted.

Eighth Embodiment FIG. 8 is a block diagram showing the structure of the eighth embodiment of the present invention.

This embodiment is different from the fourth embodiment in FIG. 4 in that the extracted interference signal is binarized by the quadrature phase detector 121 instead of the phase detector, and the main signal distributor 1 is used.
The output of 3 is binarized by the phase detector 48 and the discriminating circuit 52 instead of the quadrature phase detector, and the respective correlations are detected.

Although the configuration of the control circuit 140 is also slightly different, this is because the control circuit 1 of the conventional interference compensation circuit shown in FIG.
Similar to 40.

Ninth Embodiment FIG. 9 is a block diagram showing the structure of a ninth embodiment of the present invention.

This embodiment differs from the fourth embodiment shown in FIG. 4 in that
The quadrature phase detectors 41 and 42 are used for binarizing the extracted interference signal.
The point is to use. As a result, although the circuit scale is larger than that in FIG. 4, the control gain is doubled,
It has the advantage of good control response and convergence.

The control circuits 140 and 141 are similar to the control circuit of the eighth embodiment described above.

FIG. 10 shows the effect of the present invention.

When 16QAM is received as the D signal desired to be received and FM signal is received as the U signal not desired to be received, the ratio of the respective signal intensities received by the antennas 1 and 4 is D
/U=8.5 dB.

Under control of the control circuit 141, these signals
Phase control is performed, and in the combiner 14, they are added with equal amplitude and opposite phase, and as an output of the second combiner 14, D ₀ / U ₀ = −
A signal of 18.8 dB was given.

Therefore, by the operation of the control circuit 141, it was possible to obtain about 27 dB as the improvement amount of D / U (that is, Di / Ui-D ₀ / U ₀ ).

The output of the second combiner 14 is applied to the third combiner 19 with the same amplitude and opposite phase as the FM signal mixed in the output of the first combiner 10 that combines the reception signals of the antennas 1 and 4. .
As a result, the synthesizer 19 outputs a signal in which the FM signal has been canceled. In the figure, the control circuit 14
The output waveforms when 0 and 141 are operated and stopped are shown.

FIG. 11 shows eye patterns when the control circuits 140 and 141 are operated or stopped. As is clear from the figure, the control circuit 140,
The most effective interference compensation effect is obtained when 141 is operated.

FIG. 12 is a diagram showing the improvement effect of the present invention. When the control circuits 140 and 141 are OFF or only the control circuit 141 is OFF, almost the same characteristics are exhibited.

With respect to these characteristics, when all of the control circuits 140 and 141 are ON, there is an improvement effect of about 10 dB, which shows the effectiveness of the present invention.

[Advantages of the Invention] As described above, the present invention extracts only the interference signal from the main signal in digital wireless communication even when the main antenna and the sub-antenna also receive the interference signal in addition to the main signal. The interference component leaked into the main signal can be removed by using the extracted interference signal as a source.

Further, even if the interference signal is transmitted in the same direction as the main signal, the interference compensating circuit according to the present invention first detects the interference signal from the main signal, and has the advantage that the interference component can be eliminated based on the detected signal. Have.

[Brief description of drawings]

1 to 9 are block diagrams showing the configurations of the first to ninth embodiments of the present invention, FIG. 10, FIG. 11 and FIG. 12 are diagrams showing the effect example of the present invention, and FIG. FIG. 14 is a block diagram showing a configuration of a conventional interference compensation circuit, and FIG. 14 is a level diagram explanatory diagram of a 4-value discrimination circuit (A / D converter). 1 ... Main antenna, 2,5 ... Band pass filter, 3,
6 ... Frequency converter, 4 ... Sub antenna, 7 ... Local oscillator, 8, 9, 13, 15, 17, 20, 25 ... Distributor, 10, 14, 19, 24, 29 ... Combiner , 11,
18 ... Variable amplitude circuit, 12, 16, 64 ... Variable phase circuit, 21, 26, 35, 47, 54 ... 90 ° phase shifter, 22, 23, 27, 28 ... Bipolar variable attenuator, Three
0, 31, 41, 42, 48, 49 ... Phase detector, 3
2, 33, 43, 44, 50, 51 ... Low-pass filter, 34 ... Regenerated carrier wave, 36 ... Regenerated clock, 3
7, 38, 45, 46, 52, 53 ... Identification circuit, 3
9, 40 ... Subtractor, 55, 56, 57, 58, 59 ...
... A / D conversion circuit, 60 ... auxiliary antenna, 61, 62
...... Automatic gain control circuit, 63 ...... Differential amplifier, 64 ......
Variable phase circuit, 65, 66, 67, 74, 75, 82,
83 ... Resistance circuit, 70, 71, 72, 78, 79, 8
0 ... Exclusive OR circuit, 73, 81 ... Exclusive inversion OR circuit, 76, 77, 84, 85 ... Integrator, 86 ...
... Phase control circuit, 91, 92, 93, 94 ... Multiplier,
100 ... In-phase synthesis circuit, 110, 111 ... Quadrature amplitude modulator, 120 ... Main signal demodulator, 121, 122 ...
Quadrature phase detector, 130, 131 ... Error signal generating circuit, 140, 141 ... Control circuit.

Claims (3)

[Claims] 1. A main transmission line and a sub-transmission line for receiving a main signal,
A first combiner for combining the reception signals of the main transmission line and the sub transmission line; and a variable amplitude circuit and a variable phase circuit, or a quadrature amplitude modulator, for the reception signals of the main transmission line and the sub transmission line. A first amplitude / phase adjusting circuit to which a reception signal of one of the transmission lines is supplied, and a second combining the output of the first amplitude / phase adjusting circuit and the reception signal received by the other transmission line. And a first control circuit for controlling the first amplitude / phase adjusting circuit so that the two main signals input to the second synthesizer have opposite phases and equal amplitudes to each other. A second amplitude / phase adjusting circuit, which comprises an amplitude circuit and a variable phase circuit, or a quadrature amplitude modulator, and is supplied with the output of the second combiner; and the output of the second amplitude / phase adjusting circuit. A third combiner for combining the output of the first combiner And a second control circuit for controlling the second amplitude / phase adjusting circuit so that an interference component in the main signal output from the third combiner is minimized. Compensation circuit. 2. A main transmission line and a sub transmission line for receiving a main signal, automatic gain control circuits to which received signals of the main transmission line and the sub transmission line are respectively supplied, and outputs of the two automatic gain control circuits. Connected to a phase control circuit that detects a phase difference from the received signals of the main transmission line and the sub transmission line and outputs phase control information, and to the output of one of the two automatic gain control circuits. Is
A phase shifter that makes the received signals of the main transmission line and the sub transmission line in phase by the output of the phase control circuit, and the output of the phase shifter and the other automatic gain control circuit of the two automatic gain control circuits A distributor for respectively distributing the output of the distributor and a distributor for connecting the output of the distributor connected to the phase shifter and the output of the distributor connected to the other automatic gain control circuit.
And a first variable amplitude controlled by an output of a differential amplifier to which outputs of a divider connected to the phase shifter are input, and to which control voltages of the two automatic gain control circuits are input. A circuit, a second combiner for combining the output of the distributor connected to the other automatic gain control circuit and the output of the first variable amplitude circuit by shifting their phases by 180 °, and A first variable phase circuit having an output of the second combiner as an input; a second variable amplitude circuit having an output of the first variable phase circuit as an input; an output of the first combiner; A third combiner for combining the signals passed through the first variable phase circuit and the second variable amplitude circuit, and a reference carrier wave obtained by reproducing the main signal output from the third combiner from the main signal. And a quadrature phase detector that decomposes into an in-phase component and a quadrature component, And two error signal generating circuits each having a quadrature component as an input, a phase detector for phase-detecting the output signal of the first variable phase circuit with the same reference carrier as the quadrature phase detector, and an exclusive OR circuit And two integrators, each of which independently detects the correlation between the output of the phase detector and the output of the two error signal generating circuits, and an output related to the in-phase component of the outputs. And a correlation detection circuit for controlling the first variable phase circuit by the output related to the quadrature component. 3. A main transmission line and a sub transmission line for receiving a main signal, a first combiner for synthesizing received signals of the main transmission line and the sub transmission line, and reception of the main transmission line and the sub transmission line. Two distributors for distributing signals, a first amplitude / phase adjusting circuit for adjusting the amplitude / phase of the output of one of the two distributors as an input signal, and the first amplitude A second combiner for combining the output signal of the phase adjusting circuit and the output signal of the other distributor of the two distributors, and the output signal of the second combiner as an input signal, A second amplitude / phase adjusting circuit for adjusting amplitude and phase; a third combiner for combining an output signal of the second amplitude / phase adjusting circuit and an output of the first combiner; The output signal of the other of the two
A first quadrature phase detector that performs quadrature phase detection using a carrier wave regenerated from the output signal of the third combiner, and a phase detector that detects the output signal of the second combiner using the carrier wave A first correlation detection circuit for detecting a correlation between the output signal of the phase detector and the output signal of the first quadrature phase detector having the same phase relationship with the output signal of the phase detector; and the output signal of the phase detector. A second correlation detecting circuit for detecting a correlation between the output signals of the first quadrature phase detector having a quadrature relationship with the output signal of the third combiner; A second quadrature phase detector, two error signal generating circuits each having an in-phase signal and a quadrature component signal of the output of the second quadrature phase detector as input signals, and an output of the in-phase side error signal generating circuit Signal and the phase in phase with it Correlation detection between a third correlation detection circuit that performs correlation detection with the output signal of the wave detector, an output signal of the quadrature-side error signal generation circuit, and an output signal of the phase detector that is in an orthogonal relationship with the detection signal. And a fourth correlation detecting circuit for controlling the first amplitude / phase circuit by the first and second correlation detecting circuits, and outputting the output signals from the third and fourth correlation detecting circuits. An interference compensation circuit characterized by controlling a second amplitude / phase circuit.