JPH01220929A - Spread spectrum receiver - Google Patents

Abstract

PURPOSE:To attain sure data demodulation by latching a value of a peak hold circuit storing a peak value being an output of correlation period for each one period of the output of a correlation device and setting a threshold level for one period of the next output of the correlation device. CONSTITUTION:A peak value for correlation spike one period of a latch circuit 8 is stored so as to discriminate whether or not the peak value data for one period of the correlation spike stored at present is revised or not in the succeeding correlation spike one period through the presence of a positive correlation pulse. Thus, the peak value of the correlation spike is held surely in one period of the correlation spike (a) and the fluctuation of the peak value is to be followed and it is possible to avoid malfunction if the polarity of the correlation spike (a) is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a receiver used in a spread spectrum communication system, and particularly to a correlated pulse generation circuit thereof.

B6 Summary of the Invention In a spread spectrum receiver, a correlation spike is obtained by correlating a received signal with a reference signal using a correlator, and the correlation spike is passed through a comparison circuit to obtain a correlation pulse. , a hold circuit that holds the hold value of the peak hold circuit, and a spread spectrum reception that obtains the threshold signal of the comparison circuit via a threshold setting circuit that sets a threshold from the hold value held in the hold circuit. Machine.

C0 Conventional technology In the spread spectrum communication system, even if the correlator output fluctuates, it is necessary to be able to follow it and obtain an appropriate threshold signal to detect the desired correlation output.

As a conventional method, for example, there is a method shown in Japanese Patent Publication No. 60-5639 [Receiving Circuit in Spread Spectrum Communication System].

In this method, the positive and negative correlated spikes of the matched filter output are peak held by a peak hold circuit, and then combined, a threshold signal proportional to this peak hold value is generated, the threshold circuit is used, the correlated spike is detected, and the data is It performs demodulation, and its circuit configuration is shown in Figure 3. In Figure 3, 21 is a correlator, 22 is a peak hold circuit, 23 is an arithmetic circuit, 24 is a flip-flop, and 25
is a shift clock generator, and 26 is a shift circuit.

27 is a PN code, 28 is a delay circuit, and 29.30 is a multiplier, which here multiplies by -1 and plays the role of an inverter. That is, the peak hold circuit 31 holds a positive polarity peak, and the peak hold circuit 32 holds a negative polarity peak. A threshold signal is obtained from the peak value via the variable resistor R1, a positive correlation spike is detected at 33, and a negative correlation spike is detected at the comparator 34.

D0 Problems to be Solved by the Invention However, this circuit configuration has the following problems. When this peak hold circuit 22 holds the peak of a correlated spike completely, the width of the correlated spike is very narrow, so the time constant due to the internal resistance of the diode D1 or D2 and the capacitor C□ or C2 must be made very small. In other words, it is necessary to reduce the charging time constant.

Conversely, when holding the peak value of the correlation spike period, the time constant consisting of the resistor R1 or R2 and the capacitor C1 or C2 must be increased in order to suppress a decrease in the hold value called droop. In other words, it is necessary to increase the discharge time constant.

The circuit configuration shown in FIG. 3 allows the discharge time constant R of the peak hold circuit 31 or 32 to be set in response to the varying correlation spike φ(1).
As shown in FIG. 4, it is clear that 1G, R, and C must be increased.

Next, when considering follow-up to fluctuations in peak value, in the case of a peak hold circuit with good holding performance, that is, a peak hold circuit with a large discharge time constant, follow-up performance with respect to decrease in peak value becomes poor.

This will be explained with reference to FIG.

Correlation spikes φ(t) causing level fluctuations as shown in FIG. 5 (in this case, the data is 1° 1.0, 0.
) is input to the peak hold circuit 22, the values of the peak hold circuits 31 and 32 are b)
and C) sA and Sa.

Here, if a correlation spike 2 smaller than the positive correlation spike 1 or a correlation spike 4 smaller than the negative correlation spike 3 is obtained, the capacitor C1 or C2 is not charged and continues to discharge. That is, if the peak value decreases more than the droop due to discharge, the peak value cannot be detected. Furthermore, the threshold signal S
If C and 51) are set as shown in Figure 5 a), correlation spike 1 can be detected, but correlation spike 2.3
．． 4 means that it cannot be detected.

Accordingly, the demodulated data d(1) becomes incorrect data with respect to the input data. In Figure 5, d) and e) are the third
The waveforms of SB and d(t) in the figure are shown, respectively.

An object of the present invention is to provide a circuit that can reliably demodulate data by setting an appropriate threshold signal and obtaining correlation pulses even when the correlator output fluctuates due to fluctuations in the received signal level. It is.

Means for Solving the E0 Problem In order to achieve the above object, the present invention is provided. In a spread spectrum receiver that obtains a correlation spike by correlating a received signal and a reference signal with a correlator, and passes the correlation spike through a comparison circuit to obtain a correlation pulse, the spread spectrum receiver includes a first peak hold circuit for a correlation spike value; a second hold circuit that holds the hold value of the first peak hold circuit; a threshold setting circuit that sets a threshold from the hold value held in the second hold circuit; and a threshold value signal that outputs the output of the threshold setting circuit. and a comparison circuit for comparing correlated spikes.

In an advantageous embodiment of the present invention, the first peak hold circuit further includes means for clearing the hold value held by the first peak hold circuit at a desired timing, and the threshold value setting circuit.
outputting a value obtained by multiplying the output value of the second hold circuit by a multiplication coefficient;

and a control means for controlling whether or not to hold the hold value of the first peak hold circuit in the second hold circuit. The control means is controlled in response to the output of the comparison circuit.

The multiplication coefficient is controlled by the CPU.

The value of the peak hold circuit that holds the peak value of the correlator output every 10-effect correlator output cycle is further latched, and a threshold value for the next correlator output cycle is set.

G. EXAMPLES The present invention will be explained in more detail below using examples with reference to the drawings, but these are merely illustrative and various modifications and improvements can be made without going beyond the scope of the present invention. Of course it is possible.

FIG. 1 is a block diagram showing the configuration of a correlation pulse generation circuit used in a spread spectrum receiver according to the present invention, and FIG.
The figure is a timing chart of signals in each part of the circuit shown in FIG. In FIG. 1, 1 is a correlator and P D
I (Po5t Detection I ntegr
ation: Integrating circuit), 2 is A/D converter, 3 is inverting circuit, 4, 5, 8.11 is latch circuit, 6.7, 14
．． 15 is a comparison circuit, 9.10 is a gate circuit, 12.13
16.17 represents a threshold value setting circuit, and 16.17 represents a peak hold circuit.

The A/D converter 2 performs A/D conversion on the correlation spike a based on the sampling signal S to obtain an output C.

Here, the result of sampling the period in which the correlation spike a exists is in the shaded area of the output C of the A/D converter 2.

Next, the output C of the A/D converter 2 is branched into a path 1 and a path 2. Path 1 is a path for detecting positive polarity correlated spikes, and Path 2 is a path for detecting negative polarity correlated spikes.

Path 2 can be realized with the same circuit configuration as path 1 by inverting the polarity of the N-bit data of output C of A/D converter 2. Therefore, after A/D converter 2, path 2
is input to the inverting circuit 3.

In path 2, the circuit configuration from inversion circuit 3 onwards is the same as path 1, so the operation of only path 1 will be described.

Output C of A/D converter 2 is input to latch circuit 4 and comparison circuit 6. The comparison circuit 6 compares the output C of the A/D converter 2 and the data f stored in the latch circuit 4, and if it is determined that the data of the output C of the A/D converter 2 is larger, , obtain a pulse output d. Using this pulse d as a trigger, the latch circuit 4 stores the data of the output C of the A/D converter 2 and updates the data f of the latch circuit 4.

In this way, the maximum value of the output C of the A/D converter 2 can be determined by sequentially comparing the output C of the A/D converter 2 and the data f of the latch circuit 4, and updating the data f stored in the latch circuit 4. The desired peak hold circuit 16 is constructed.

The latch circuit 4 sends a clear signal e every correlation spike period.
The stored content f is cleared, and peak hold for a new correlation spike period is performed. The period of the pulse of the clear signal e is the same as the period of the correlation spike. In other words, the peak hold circuit with this circuit configuration can reliably hold the peak value for the period corresponding to the correlation spike.

Next, the correlation spike stored in the latch circuit 4 -
The maximum value of the output C of the A/D converter 2 for a period is stored in the latch circuit 8 by using the signal e as a trigger to clear the latch circuit 4 with the clear signal e. here,
If the positive correlation pulse j is input before the pulse of the clear signal e is input, the gate circuit 9 passes the enable signal g and inputs the signal to the latch circuit 8.

When the positive correlation pulse j does not exist, the gate is applied and nothing is output as a signal, and the latch circuit 8 does not receive the trigger pulse, so the output i of the latch circuit 8 does not change.

The peak value for the correlation spike period of the latch circuit 8 is held, and due to the presence of the positive correlation pulse, the currently held peak value data for the correlation spike period is updated in the next correlation spike period. Decide whether to do it or not.

By adopting such a configuration, it is possible to reliably maintain the peak value of the correlated spike within one period of the correlated spike a, and also to follow fluctuations in the peak value, and also to be able to track changes in the polarity of the correlated spike when the polarity of the correlated spike changes. It is possible to eliminate malfunctions.

Next, the output data i of the latch circuit 8 is input to the threshold value setting circuit 12. Here, an operation is performed on the output data i of the latch circuit 8 and a control signal representing a multiplication coefficient to generate a threshold signal Q. This threshold signal Q is an N-bit digital signal. Note that the control signal is generated by, for example, a CPU.

Next, the threshold signal Q obtained by the threshold setting circuit 12 is input to the comparison circuit 14. The comparison circuit 14 compares the output C of the A/D converter 2 and the threshold signal Ω, and when the output C of the A/D converter 2, which is larger than the threshold signal Q, is input, an output j is obtained. In this way, a correlation pulse j corresponding to a correlation spike is obtained.

Additionally, by storing the peak value of the output C of the A/D converter 2 within the correlated spike period obtained by the peak hold circuit 16 in the latch circuit 8, the threshold signal Q in the next cycle is It will be possible to set it. Even if there is no output C of the A/D converter 2 that exceeds the threshold signal Q within one period and a correlation pulse j is not obtained, the data i of the latch circuit 8 is still held, so that The threshold signal Q will be set to the same value in the next cycle as well.

Therefore, as shown in FIG. 2, the data f stored in the latch circuit 4 of the peak hold circuit 16 within the period in which the negative polarity correlation spike exists indicates the noise level, but As long as the peak value of j is held in the latch circuit 8, the comparison circuit 14 will not erroneously detect the correlation pulse j.

Further, a threshold signal Q for detecting a correlated spike in the next period of the negative polarity correlated spike can be set by the output i of the latch circuit 8, and only correlated spikes can be detected.

Note that although the peak hold circuit configuration described above is premised on digital signal processing, the present invention can be applied even when analog signal processing is performed by replacing the latch circuit with a hold circuit.

As described in detail of the H0 invention, the present invention has the advantage that accurate data demodulation can be performed even when correlator output fluctuations occur due to input level fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a correlation pulse generation circuit used in a spread spectrum receiver according to the present invention, and FIG.
The figure is a timing chart of signals in each part of the circuit shown in Figure 1, Figure 3 is a circuit diagram of a conventional correlated pulse generation circuit, and Figure 4 is a voltage waveform when the discharge time constant is small and when the discharge time constant is large. 5 are signal waveform diagrams at various parts of the circuit shown in FIG. 3. ■・・・・・・Correlator and PDI, 2...
...A/D converter, 3...Inversion circuit, 4, 5, 8.11...Latch circuit,
6, 7, 14.15... Comparison circuit, 9.
10......Gate circuit, 12.13...
...Threshold setting circuit, 16.17...
...Peak hold circuit. Patent Applicant Clarion Co., Ltd. Agent Patent Attorney Nagai 1) Takeshi Part 3 Figure 4 Procedural Amendment Date F, December 1986

Claims (6)

[Claims] (1) In a spread spectrum receiver that obtains a correlation spike by correlating the received signal and a reference signal with a correlator and passes the correlation spike through a comparison circuit to obtain a correlation pulse, (a) the first correlation spike value (b) a second hold circuit that holds the hold value of the first peak hold circuit; (c) a threshold setting circuit that sets a threshold from the hold value held in the second hold circuit. (d) A spread spectrum receiver comprising a comparison circuit that uses the output of the threshold setting circuit as a threshold signal and compares it with a correlation spike. (2) The spread spectrum receiver according to claim 1, further comprising means for clearing the hold value held by the first peak hold circuit at a desired timing. (3) The spread spectrum receiver according to claim 1, wherein the threshold value setting circuit outputs a value obtained by multiplying the output value of the second peak hold circuit by a multiplication coefficient. (4) Spread spectrum reception according to claim 1, further comprising control means for controlling whether or not to hold the hold value of the first peak hold circuit in the second hold circuit. Machine. (5) The spread spectrum receiver according to claim 4, wherein the control means is controlled in response to the output of the comparison circuit. (6) The spread spectrum receiver according to claim 3, wherein the multiplication coefficient is controlled by a CPU.