JPH01220051A - Information processor - Google Patents

Abstract

PURPOSE:To improve system performance and to attain efficient input/output action by suppressing an access from plural input/output processor to a common area and accessing queues in the input/output processors at high speed. CONSTITUTION:When an input/output device activating factor from a central processing unit 0 occurs, when an access path able to access input/output devices 4-6 exists in plural input/output processors 2 and 3, it is connected to a queue 11 existing in a main storage (common area) 1 which can be accessed from the plural input/output processors 2 and 3 and when the access path able to access the input/output devices 4-6 can be limited to one input/output processor 2 or 3, it is connected to a queue 12 or 13 existing in the input/output processor 2 or 3. Consequently, the access from the plural input/output processor 2 and 3 to the common area 1 is suppressed and the queue 12 or 13 in the input/output processor 2 or 3 can be accessed at higher speed in comparison with the access to the common area 1. Thus, the performance of the system can be improved and the efficient input/output action can be attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used for information processing. The present invention relates to an information processing apparatus in which a plurality of input/output devices are controlled by a plurality of input/output processing devices.

〔overview〕

The present invention provides an information processing device in which a plurality of input/output devices are controlled by a plurality of input/output processing devices. If the queue exists in multiple I/O processing devices, it connects to a queue that exists in a common storage area that is accessible from multiple I/O devices, and if it can be limited to - I/O processing devices, it By connecting to an existing queue, accesses from multiple input/output processing devices to the common area can be suppressed, and access to the queue in the output processing device can be made faster compared to accessing the common area. It is designed to improve system performance and enable efficient input/output operations.

[Conventional technology]

Conventionally, in this type of information processing device, when an input/output device activation factor occurs due to an input/output command from the central processing unit, the information processing device is sequentially connected to a queue existing in a common area accessible by multiple input/output processing devices. , the input/output processing device was controlled to extract the input/output device activation factor from the queue, select an access route, and then start executing the input/output operation.

[Problem that the invention seeks to solve]

In the conventional information processing device described above, the input/output device activation factor is connected to a queue that exists in a common area that can be accessed by multiple input/output processing devices, so accesses from multiple input/output processing devices are concentrated. In addition to degrading system performance, even if the access path from the input/output device can be limited to one input/output processing device, access to the common area is always required, causing a reduction in the processing efficiency of input/output operations. was.

The present invention solves these problems by suppressing access from multiple input/output processing units to a common area, making it possible to speed up access to the queue within the input/output processing unit, and improving system performance. The purpose of the present invention is to provide a device capable of improved and efficient input/output operations.

[Means for solving problems]

The present invention includes a central processing unit, a plurality of input/output processing devices accessible from the central processing unit, and one or more input/output devices each connected to the input/output processing device,
In an information processing device in which each input/output processing device includes a queue means for setting the access order of the input/output devices connected under it, some of the input/output devices are connected to multiple input/output processing devices. and the queues for the I/O devices connected to the multiple I/O processing devices are
The queue means is characterized in that it is provided in a common storage area separately from the queue means.

[Effect]

When an input/output device activation factor occurs due to an input/output command from the central processing unit, if multiple input/output processing devices have access paths that allow access to the input/output device, Connect to a queue that exists in an accessible common area, or connect to a queue that exists within an I/O device if the accessible access path to the I/O device can be limited to one I/O processing device. .

In this way, access from multiple input/output processing devices to the common area can be suppressed, and access to the queue in the input/output processing device can be performed faster than accessing the common area, and the system performance and efficient input/output operations.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an apparatus according to an embodiment of the present invention.

The device according to the embodiment of the present invention includes a central processing unit 0 and a plurality of input/output processing units 2.3 that can be accessed from the central processing unit 0.
and 1 connected to this input/output processing device 2.3, respectively.
The input/output device 4.5.6 is provided with the above input/output device 4.5.6, and the input/output processing device 2.3 has an input/output device 4.5.6 connected under it.
queuing means 12.13 for setting the access order of the .

Some of the input/output devices are connected to a plurality of input/output processing devices, and a queue for the input/output devices connected to the plurality of input/output processing devices is defined as the above-mentioned queuing means 12.13. is separately provided as a queue means 11 in the main memory 1 as a common storage area.

The operation of the embodiment of the present invention configured as described above will be explained. FIG. 2 is a flow chart of the operation of the embodiment of the present invention.

When an input/output command is executed by the central processing unit 0 and a activation factor for the input/output device 4 occurs, it is verified whether the access path accessible from the input/output device 4 can be limited to the input/output processing device 2 ( Process 200), here, since the access route 7 that can access the input/output device 4 can be limited to the input/output processing device 2, the activation factor of the input/output device 4 is connected to the queue 12 in the input/output processing device 2. (Processing 204)
.

Next, when an input/output command is executed by the central processing unit 0 and an activation factor for the input/output device 5 occurs, an access path accessible from the input/output device 5 is transferred to the input/output processing device 2 or the input/output processing device 3. It is verified whether the access path can be limited to the input/output processing device 3 (process 200.201), and if the accessible access route can be limited to the input/output processing device 3, the activation factor of the input/output device 5 is the queue 13 in the input/output processing device 3. (process 203), and if it cannot be limited, the accessible access routes to the input/output device 5 are access route 1 and access route 9, and it cannot be limited to - input/output processing devices, so the input/output processing device The activation factor of the input/output device 5 is connected to the queue 11 in the main storage device 1 that can be accessed by the input/output processing device 2 and the input/output processing device 3 (process 202).

Thereafter, each time an activation factor occurs, it is connected to the queue in the same way, and the input/output processing device 2 is connected to the queue from the queues 11 and 12.
The input/output processing device 3 sequentially extracts input/output device activation factors from the queues 11 and 13, selects an access route,
Starts input/output operations.

The access path to each input/output device may include not only the condition that it is physically accessible but also the condition that it is logically accessible.

〔Effect of the invention〕

As explained above, according to the present invention, when an input/output device activation factor due to an input/output command from a central processing unit is present in a plurality of input/output processing devices, An input/output processing device if it connects to a queue that exists in a common storage area that can be accessed by multiple input/output devices, and if the access path to the input/output device can be limited to one input/output processing device. By controlling and connecting to the queue existing in the input/output processing unit, accesses from multiple input/output processing units to the common area are suppressed, and the queue in the input/output processing unit is controlled compared to access to the common area. can be accessed at high speed, which has the effect of improving system performance and enabling efficient input/output operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flow chart of one embodiment of the present invention. 0...Central processing unit, 1...Main storage device, 2.3.
...I/O processing device, 4.5.6...I/O device, 7
．． 8.9.10...Access route, IL 12.13
···Queue.

Claims (1)

[Claims] 1. A central processing unit (0), a plurality of input/output processing units (2, 3) accessible from this central processing unit, and one or more input/output processing units each connected to this input/output processing unit. An information processing device comprising input/output devices (4, 5, 6), each input/output processing device including a queue means for setting the access order of the input/output devices connected under it, the input/output device Some of the input/output processing devices are connected to a plurality of input/output processing devices, and queues for the input/output devices connected to the plurality of input/output processing devices are stored in a common storage area separately from the above-mentioned queue means. An information processing device characterized in that: